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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-01 08:42:01 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-10 21:57:20 +0000 |
| commit | 6d44437ec1310ba7f896275d1b416eb35de467a9 (patch) | |
| tree | 416477702a921f722957f0c281a64d7624e64ce0 /src | |
| parent | bd5b4aa683a634a73a6a63d1f197e2bb74b6a80e (diff) | |
| download | coreboot-6d44437ec1310ba7f896275d1b416eb35de467a9.tar.gz coreboot-6d44437ec1310ba7f896275d1b416eb35de467a9.tar.bz2 coreboot-6d44437ec1310ba7f896275d1b416eb35de467a9.zip | |
soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore
switch cannonlake boards to this method.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/pmc.c | 10 |
3 files changed, 11 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f2a316aba92f..8abe93000934 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -80,6 +80,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index fa75673e450f..052847d08c12 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -39,6 +39,3 @@ /* GbE 0:1f.6 */ #include <soc/intel/common/block/acpi/acpi/pch_glan.asl> - -/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 59f4be5564c5..817cdd77dcc1 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> @@ -119,10 +120,19 @@ static void soc_acpi_mode_init(struct device *dev) pmc_set_acpi_mode(); } +static void pmc_fill_ssdt(const struct device *dev) +{ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) + generate_acpi_power_engine(); +} + struct device_operations pmc_ops = { .read_resources = soc_pmc_read_resources, .set_resources = noop_set_resources, .init = soc_acpi_mode_init, .enable = pmc_init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = pmc_fill_ssdt, +#endif .scan_bus = scan_static_bus, }; |