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| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-07 18:41:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-09 00:31:54 +0000 |
| commit | 8ad0a4c0b88718a0b0ba4ba934ff526fe6875702 (patch) | |
| tree | 065bdf3f22cef26df4c73f34bdfc6683132bdd1f /src | |
| parent | 2f3456a8734d4fb9b4ab492f4bdd7f3b1885706c (diff) | |
| download | coreboot-8ad0a4c0b88718a0b0ba4ba934ff526fe6875702.tar.gz coreboot-8ad0a4c0b88718a0b0ba4ba934ff526fe6875702.tar.bz2 coreboot-8ad0a4c0b88718a0b0ba4ba934ff526fe6875702.zip | |
nb/intel/gm45/iommu.c: Fix regression when updating PCI command
Commit 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
uses `pci_read_config8` to read the PCI command register, which does not
correspond with what has been stated in the commit message. Moreover, it
potentially breaks things, as the upper byte of the PCI command register
is now being cleared.
So, restore the original behaviour of the code, using 16-bit accesses.
Fixes: 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/gm45/iommu.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 10e0d02066b4..439127d17d36 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -43,9 +43,7 @@ void init_iommu() memset(bar, 0, 2<<20); /* and now disable again */ - u16 cmd = pci_read_config8(igd, PCI_COMMAND); - cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config16(igd, PCI_COMMAND, cmd); + pci_and_config16(igd, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)); pci_write_config32(igd, PCI_BASE_ADDRESS_0, 0); } |