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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-22 16:48:58 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-26 16:34:05 +0200 |
| commit | 0c0b79689a804bff6cba25869d810812302ff9fc (patch) | |
| tree | bf8a0e7af128186c922a54dfd9dd8f66315ced8a /src | |
| parent | 58ab3bed82c5696b1cb00382cff26e97fb44b0d8 (diff) | |
| download | coreboot-0c0b79689a804bff6cba25869d810812302ff9fc.tar.gz coreboot-0c0b79689a804bff6cba25869d810812302ff9fc.tar.bz2 coreboot-0c0b79689a804bff6cba25869d810812302ff9fc.zip | |
mb/intel/d510mo: Add romstage timestamps
Change-Id: I324edce44ad82217ac1fba177f4a0bb3c799308c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19426
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/d510mo/romstage.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 1bf2b61018e3..c6406e6f9fdd 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -33,6 +33,7 @@ #include <arch/stages.h> #include <cbmem.h> #include <romstage_handoff.h> +#include <timestamp.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) @@ -105,6 +106,9 @@ void mainboard_romstage_entry(unsigned long bist) int s3resume = 0; int boot_path; + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (bist == 0) enable_lapic(); @@ -137,7 +141,9 @@ void mainboard_romstage_entry(unsigned long bist) } printk(BIOS_DEBUG, "Initializing memory\n"); + timestamp_add_now(TS_BEFORE_INITRAM); sdram_initialize(boot_path, spd_addrmap); + timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "Memory initialized\n"); post_code(0x31); |