amd/pi/hudson: Clean up whitespace in header files

Change spaces to tabs and do general whitespace cleanup.

Change-Id: I4a4ecd42f91c9c6015a4f065b7386b17523ac6d9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19401
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 195 insertions, 192 deletions

diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h
index ecb9fb0350fd..6b6343bc10bd 100644
--- a/src/southbridge/amd/pi/hudson/hudson.h
+++ b/src/southbridge/amd/pi/hudson/hudson.h
@@ -26,29 +26,32 @@
  * This is defined by AGESA, but we don't include AGESA headers to avoid
  * polluting the namespace.
  */
-#define PM_MMIO_BASE 0xfed80300
+#define PM_MMIO_BASE			0xfed80300
 
 /* Power management index/data registers */
-#define BIOSRAM_INDEX	0xcd4
-#define BIOSRAM_DATA	0xcd5
-#define PM_INDEX	0xcd6
-#define PM_DATA		0xcd7
-#define PM2_INDEX	0xcd0
-#define PM2_DATA	0xcd1
-
-#define PM_SERIRQ_CONF		0x54
-#define PM_EVT_BLK		0x60
-#define PM1_CNT_BLK		0x62
-#define PM_TMR_BLK		0x64
-#define PM_CPU_CTRL		0x66
-#define PM_GPE0_BLK		0x68
-#define PM_ACPI_SMI_CMD		0x6A
-#define PM_ACPI_CONF		0x74
-#define PM_MANUAL_RESET		0xD3
-#define PM_HUD_SD_FLASH_CTRL	0xE7
-#define PM_YANG_SD_FLASH_CTRL	0xE8
-
-#define HUDSON_ACPI_IO_BASE 0x600
+#define BIOSRAM_INDEX			0xcd4
+#define BIOSRAM_DATA			0xcd5
+#define PM_INDEX			0xcd6
+#define PM_DATA				0xcd7
+#define PM2_INDEX			0xcd0
+#define PM2_DATA			0xcd1
+
+#define PM_ACPI_MMIO_EN			0x24
+#define PM_SERIRQ_CONF			0x54
+#define PM_EVT_BLK			0x60
+#define PM1_CNT_BLK			0x62
+#define PM_TMR_BLK			0x64
+#define PM_CPU_CTRL			0x66
+#define PM_GPE0_BLK			0x68
+#define PM_ACPI_SMI_CMD			0x6A
+#define PM_ACPI_CONF			0x74
+#define PM_PMIO_DEBUG			0xD2
+#define PM_MANUAL_RESET			0xD3
+#define PM_HUD_SD_FLASH_CTRL		0xE7
+#define PM_YANG_SD_FLASH_CTRL		0xE8
+#define PM_PCIB_CFG			0xEA
+
+#define HUDSON_ACPI_IO_BASE		0x600
 #define ACPI_PM_EVT_BLK		(HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
 #define ACPI_PM1_CNT_BLK	(HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
 #define ACPI_PM_TMR_BLK		(HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
@@ -62,51 +65,51 @@
 #define ACPI_SMI_CMD_ENABLE		0xef
 #define ACPI_SMI_CMD_S4_REQ		0xc0
 
-#define REV_HUDSON_A11	0x11
-#define REV_HUDSON_A12	0x12
-
-#define SPIROM_BASE_ADDRESS_REGISTER  0xA0
-#define SPI_ROM_ENABLE                0x02
-#define SPI_BASE_ADDRESS              0xFEC10000
-
-#define LPC_IO_PORT_DECODE_ENABLE     0x44
-#define DECODE_ENABLE_PARALLEL_PORT0  BIT(0)
-#define DECODE_ENABLE_PARALLEL_PORT1  BIT(1)
-#define DECODE_ENABLE_PARALLEL_PORT2  BIT(2)
-#define DECODE_ENABLE_PARALLEL_PORT3  BIT(3)
-#define DECODE_ENABLE_PARALLEL_PORT4  BIT(4)
-#define DECODE_ENABLE_PARALLEL_PORT5  BIT(5)
-#define DECODE_ENABLE_SERIAL_PORT0    BIT(6)
-#define DECODE_ENABLE_SERIAL_PORT1    BIT(7)
-#define DECODE_ENABLE_SERIAL_PORT2    BIT(8)
-#define DECODE_ENABLE_SERIAL_PORT3    BIT(9)
-#define DECODE_ENABLE_SERIAL_PORT4    BIT(10)
-#define DECODE_ENABLE_SERIAL_PORT5    BIT(11)
-#define DECODE_ENABLE_SERIAL_PORT6    BIT(12)
-#define DECODE_ENABLE_SERIAL_PORT7    BIT(13)
-#define DECODE_ENABLE_AUDIO_PORT0     BIT(14)
-#define DECODE_ENABLE_AUDIO_PORT1     BIT(15)
-#define DECODE_ENABLE_AUDIO_PORT2     BIT(16)
-#define DECODE_ENABLE_AUDIO_PORT3     BIT(17)
-#define DECODE_ENABLE_MIDI_PORT0      BIT(18)
-#define DECODE_ENABLE_MIDI_PORT1      BIT(19)
-#define DECODE_ENABLE_MIDI_PORT2      BIT(20)
-#define DECODE_ENABLE_MIDI_PORT3      BIT(21)
-#define DECODE_ENABLE_MSS_PORT0       BIT(22)
-#define DECODE_ENABLE_MSS_PORT1       BIT(23)
-#define DECODE_ENABLE_MSS_PORT2       BIT(24)
-#define DECODE_ENABLE_MSS_PORT3       BIT(25)
-#define DECODE_ENABLE_FDC_PORT0       BIT(26)
-#define DECODE_ENABLE_FDC_PORT1       BIT(27)
-#define DECODE_ENABLE_GAME_PORT       BIT(28)
-#define DECODE_ENABLE_KBC_PORT        BIT(29)
-#define DECODE_ENABLE_ACPIUC_PORT     BIT(30)
-#define DECODE_ENABLE_ADLIB_PORT      BIT(31)
+#define REV_HUDSON_A11			0x11
+#define REV_HUDSON_A12			0x12
+
+#define SPIROM_BASE_ADDRESS_REGISTER	0xA0
+#define   SPI_ROM_ENABLE		0x02
+#define   SPI_BASE_ADDRESS		0xFEC10000
+
+#define LPC_IO_PORT_DECODE_ENABLE	0x44
+#define   DECODE_ENABLE_PARALLEL_PORT0	BIT(0)
+#define   DECODE_ENABLE_PARALLEL_PORT1	BIT(1)
+#define   DECODE_ENABLE_PARALLEL_PORT2	BIT(2)
+#define   DECODE_ENABLE_PARALLEL_PORT3	BIT(3)
+#define   DECODE_ENABLE_PARALLEL_PORT4	BIT(4)
+#define   DECODE_ENABLE_PARALLEL_PORT5	BIT(5)
+#define   DECODE_ENABLE_SERIAL_PORT0	BIT(6)
+#define   DECODE_ENABLE_SERIAL_PORT1	BIT(7)
+#define   DECODE_ENABLE_SERIAL_PORT2	BIT(8)
+#define   DECODE_ENABLE_SERIAL_PORT3	BIT(9)
+#define   DECODE_ENABLE_SERIAL_PORT4	BIT(10)
+#define   DECODE_ENABLE_SERIAL_PORT5	BIT(11)
+#define   DECODE_ENABLE_SERIAL_PORT6	BIT(12)
+#define   DECODE_ENABLE_SERIAL_PORT7	BIT(13)
+#define   DECODE_ENABLE_AUDIO_PORT0	BIT(14)
+#define   DECODE_ENABLE_AUDIO_PORT1	BIT(15)
+#define   DECODE_ENABLE_AUDIO_PORT2	BIT(16)
+#define   DECODE_ENABLE_AUDIO_PORT3	BIT(17)
+#define   DECODE_ENABLE_MIDI_PORT0	BIT(18)
+#define   DECODE_ENABLE_MIDI_PORT1	BIT(19)
+#define   DECODE_ENABLE_MIDI_PORT2	BIT(20)
+#define   DECODE_ENABLE_MIDI_PORT3	BIT(21)
+#define   DECODE_ENABLE_MSS_PORT0	BIT(22)
+#define   DECODE_ENABLE_MSS_PORT1	BIT(23)
+#define   DECODE_ENABLE_MSS_PORT2	BIT(24)
+#define   DECODE_ENABLE_MSS_PORT3	BIT(25)
+#define   DECODE_ENABLE_FDC_PORT0	BIT(26)
+#define   DECODE_ENABLE_FDC_PORT1	BIT(27)
+#define   DECODE_ENABLE_GAME_PORT	BIT(28)
+#define   DECODE_ENABLE_KBC_PORT	BIT(29)
+#define   DECODE_ENABLE_ACPIUC_PORT	BIT(30)
+#define   DECODE_ENABLE_ADLIB_PORT	BIT(31)
 
 #define LPC_IO_OR_MEM_DECODE_ENABLE	0x48
-#define   LPC_WIDEIO2_ENABLE	BIT(25)
-#define   LPC_WIDEIO1_ENABLE	BIT(24)
-#define   LPC_WIDEIO0_ENABLE	BIT(2)
+#define   LPC_WIDEIO2_ENABLE		BIT(25)
+#define   LPC_WIDEIO1_ENABLE		BIT(24)
+#define   LPC_WIDEIO0_ENABLE		BIT(2)
 
 #define LPC_WIDEIO_GENERIC_PORT		0x64
 
@@ -117,43 +120,43 @@
 
 #define LPC_WIDEIO2_GENERIC_PORT	0x90
 
-#define SPI_CNTRL0                    0x00
-#define SPI_READ_MODE_MASK            (BIT(30) | BIT(29) | BIT(18))
+#define SPI_CNTRL0 			0x00
+#define   SPI_READ_MODE_MASK		(BIT(30) | BIT(29) | BIT(18))
 /* Nominal is 16.7MHz on older devices, 33MHz on newer */
-#define SPI_READ_MODE_NOM             0x00000000
-#define SPI_READ_MODE_DUAL112         (          BIT(29)          )
-#define SPI_READ_MODE_QUAD114         (          BIT(29) | BIT(18))
-#define SPI_READ_MODE_DUAL122         (BIT(30)                    )
-#define SPI_READ_MODE_QUAD144         (BIT(30) |           BIT(18))
-#define SPI_READ_MODE_NORMAL66        (BIT(30) | BIT(29)          )
+#define   SPI_READ_MODE_NOM		0x00000000
+#define   SPI_READ_MODE_DUAL112		(          BIT(29)          )
+#define   SPI_READ_MODE_QUAD114		(          BIT(29) | BIT(18))
+#define   SPI_READ_MODE_DUAL122		(BIT(30)                    )
+#define   SPI_READ_MODE_QUAD144		(BIT(30) |           BIT(18))
+#define   SPI_READ_MODE_NORMAL66	(BIT(30) | BIT(29)          )
 /* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */
-#define SPI_READ_MODE_FAST_HUDSON1    (                    BIT(18))
-#define SPI_READ_MODE_FAST            (BIT(30) | BIT(29) | BIT(18))
-#define SPI_ARB_ENABLE                BIT(19)
+#define   SPI_READ_MODE_FAST_HUDSON1	(                    BIT(18))
+#define   SPI_READ_MODE_FAST		(BIT(30) | BIT(29) | BIT(18))
+#define   SPI_ARB_ENABLE		BIT(19)
 
-#define SPI_CNTRL1                    0x0c
+#define SPI_CNTRL1			0x0c
 /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
-#define SPI_CNTRL1_SPEED_MASK         (BIT(15) | BIT(14) | BIT(13) | BIT(12))
-#define SPI_NORM_SPEED_SH             12
-#define SPI_FAST_SPEED_SH             8
-
-#define SPI100_ENABLE                 0x20
-#define SPI_USE_SPI100                BIT(0)
-
-#define SPI100_SPEED_CONFIG           0x22
-#define SPI_SPEED_66M                 (0x0)
-#define SPI_SPEED_33M                 (                  BIT(0))
-#define SPI_SPEED_22M                 (         BIT(1)         )
-#define SPI_SPEED_16M                 (         BIT(1) | BIT(0))
-#define SPI_SPEED_100M                (BIT(2)                  )
-#define SPI_SPEED_800K                (BIT(2) |          BIT(0))
-#define SPI_NORM_SPEED_NEW_SH         12
-#define SPI_FAST_SPEED_NEW_SH         8
-#define SPI_ALT_SPEED_NEW_SH          4
-#define SPI_TPM_SPEED_NEW_SH          0
-
-#define SPI100_HOST_PREF_CONFIG       0x2c
-#define SPI_RD4DW_EN_HOST             BIT(15)
+#define   SPI_CNTRL1_SPEED_MASK 	(BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define   SPI_NORM_SPEED_SH		12
+#define   SPI_FAST_SPEED_SH		8
+
+#define SPI100_ENABLE			0x20
+#define   SPI_USE_SPI100		BIT(0)
+
+#define SPI100_SPEED_CONFIG		0x22
+#define   SPI_SPEED_66M			(0x0)
+#define   SPI_SPEED_33M			(                  BIT(0))
+#define   SPI_SPEED_22M			(         BIT(1)         )
+#define   SPI_SPEED_16M			(         BIT(1) | BIT(0))
+#define   SPI_SPEED_100M		(BIT(2)                  )
+#define   SPI_SPEED_800K		(BIT(2) |          BIT(0))
+#define   SPI_NORM_SPEED_NEW_SH		12
+#define   SPI_FAST_SPEED_NEW_SH		8
+#define   SPI_ALT_SPEED_NEW_SH 		4
+#define   SPI_TPM_SPEED_NEW_SH		0
+
+#define SPI100_HOST_PREF_CONFIG 	0x2c
+#define   SPI_RD4DW_EN_HOST		BIT(15)
 
 static inline int hudson_sata_enable(void)
 {
diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h
index 2caa44c2222b..76480e51ee8e 100644
--- a/src/southbridge/amd/pi/hudson/pci_devs.h
+++ b/src/southbridge/amd/pi/hudson/pci_devs.h
@@ -16,107 +16,107 @@
 #ifndef _PI_HUDSON_PCI_DEVS_H_
 #define _PI_HUDSON_PCI_DEVS_H_
 
-#define BUS0 0
+#define BUS0			0
 
 /* XHCI */
-#define XHCI_DEV 0x10
-#define XHCI_FUNC 0
-#define XHCI_DEVID 0x7814
-#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
+#define XHCI_DEV		0x10
+#define XHCI_FUNC		0
+#define XHCI_DEVID		0x7814
+#define XHCI_DEVFN		PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
 
-#define XHCI2_DEV 0x10
-#define XHCI2_FUNC 1
-#define XHCI2_DEVID 0x7814
-#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
+#define XHCI2_DEV		0x10
+#define XHCI2_FUNC		1
+#define XHCI2_DEVID		0x7814
+#define XHCI2_DEVFN		PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
 
 /* SATA */
-#define SATA_DEV 0x11
-#define SATA_FUNC 0
-#define SATA_IDE_DEVID 0x7800
-#define AHCI_DEVID_MS 0x7801
-#define AHCI_DEVID_AMD 0x7804
-#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC)
+#define SATA_DEV		0x11
+#define SATA_FUNC		0
+#define SATA_IDE_DEVID		0x7800
+#define AHCI_DEVID_MS		0x7801
+#define AHCI_DEVID_AMD		0x7804
+#define SATA_DEVFN		PCI_DEVFN(SATA_DEV,SATA_FUNC)
 
 /* OHCI */
-#define OHCI1_DEV 0x12
-#define OHCI1_FUNC 0
-#define OHCI2_DEV 0x13
-#define OHCI2_FUNC 0
-#define OHCI3_DEV 0x16
-#define OHCI3_FUNC 0
-#define OHCI4_DEV 0x14
-#define OHCI4_FUNC 5
-#define OHCI_DEVID 0x7807
-#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
-#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
-#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
-#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
+#define OHCI1_DEV		0x12
+#define OHCI1_FUNC		0
+#define OHCI2_DEV		0x13
+#define OHCI2_FUNC		0
+#define OHCI3_DEV		0x16
+#define OHCI3_FUNC		0
+#define OHCI4_DEV		0x14
+#define OHCI4_FUNC		5
+#define OHCI_DEVID		0x7807
+#define OHCI1_DEVFN		PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
+#define OHCI2_DEVFN		PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
+#define OHCI3_DEVFN		PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
+#define OHCI4_DEVFN		PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
 
 /* EHCI */
-#define EHCI1_DEV 0x12
-#define EHCI1_FUNC 2
-#define EHCI2_DEV 0x13
-#define EHCI2_FUNC 2
-#define EHCI3_DEV 0x16
-#define EHCI3_FUNC 2
-#define EHCI_DEVID 0x7808
-#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
-#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
-#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
+#define EHCI1_DEV		0x12
+#define EHCI1_FUNC		2
+#define EHCI2_DEV		0x13
+#define EHCI2_FUNC		2
+#define EHCI3_DEV		0x16
+#define EHCI3_FUNC		2
+#define EHCI_DEVID		0x7808
+#define EHCI1_DEVFN		PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
+#define EHCI2_DEVFN		PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
+#define EHCI3_DEVFN		PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
 
 /* SMBUS */
-#define SMBUS_DEV 0x14
-#define SMBUS_FUNC 0
-#define SMBUS_DEVID 0x780B
-#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
+#define SMBUS_DEV		0x14
+#define SMBUS_FUNC		0
+#define SMBUS_DEVID		0x780B
+#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
 
 /* IDE */
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
-#define IDE_DEV 0x14
-#define IDE_FUNC 1
-# define IDE_DEVID 0x780C
-# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC)
+#define IDE_DEV			0x14
+#define IDE_FUNC		1
+#define IDE_DEVID		0x780C
+#define IDE_DEVFN		PCI_DEVFN(IDE_DEV,IDE_FUNC)
 #endif
 
 /* HD Audio */
-#define HDA_DEV 0x14
-#define HDA_FUNC 2
-#define HDA_DEVID 0x780D
-#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC)
+#define HDA_DEV			0x14
+#define HDA_FUNC		2
+#define HDA_DEVID		0x780D
+#define HDA_DEVFN		PCI_DEVFN(HDA_DEV,HDA_FUNC)
 
 /* LPC BUS */
-#define PCU_DEV 0x14
-#define LPC_FUNC 3
-#define LPC_DEVID 0x780E
-#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)
+#define PCU_DEV			0x14
+#define LPC_FUNC		3
+#define LPC_DEVID		0x780E
+#define LPC_DEVFN		PCI_DEVFN(LPC_DEV,LPC_FUNC)
 
 /* PCI Ports */
-#define SB_PCI_PORT_DEV 0x14
-#define SB_PCI_PORT_FUNC 4
-# define SB_PCI_PORT_DEVID 0x780F
-# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
+#define SB_PCI_PORT_DEV		0x14
+#define SB_PCI_PORT_FUNC	4
+#define SB_PCI_PORT_DEVID	0x780F
+#define SB_PCI_PORT_DEVFN	PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
 
 /* SD Controller */
-#define SD_DEV 0x14
-#define SD_FUNC 7
-#define SD_DEVID 0x7806
-#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
+#define SD_DEV			0x14
+#define SD_FUNC			7
+#define SD_DEVID		0x7806
+#define SD_DEVFN		PCI_DEVFN(SD_DEV,SD_FUNC)
 
 /* PCIe Ports */
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
-#define SB_PCIE_DEV 0x15
-#define SB_PCIE_PORT1_FUNC 0
-#define SB_PCIE_PORT2_FUNC 1
-#define SB_PCIE_PORT3_FUNC 2
-#define SB_PCIE_PORT4_FUNC 3
-#define SB_PCIE_PORT1_DEVID 0x7820
-#define SB_PCIE_PORT2_DEVID 0x7821
-#define SB_PCIE_PORT3_DEVID 0x7822
-#define SB_PCIE_PORT4_DEVID 0x7823
-#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
-#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
-#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
-#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
+#define SB_PCIE_DEV		0x15
+#define SB_PCIE_PORT1_FUNC	0
+#define SB_PCIE_PORT2_FUNC	1
+#define SB_PCIE_PORT3_FUNC	2
+#define SB_PCIE_PORT4_FUNC	3
+#define SB_PCIE_PORT1_DEVID	0x7820
+#define SB_PCIE_PORT2_DEVID	0x7821
+#define SB_PCIE_PORT3_DEVID	0x7822
+#define SB_PCIE_PORT4_DEVID	0x7823
+#define SB_PCIE_PORT1_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
+#define SB_PCIE_PORT2_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
+#define SB_PCIE_PORT3_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
+#define SB_PCIE_PORT4_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
 #endif
 
 #endif /* _PI_HUDSON_PCI_DEVS_H_ */
diff --git a/src/southbridge/amd/pi/hudson/smbus.h b/src/southbridge/amd/pi/hudson/smbus.h
index 7bf29ad8d008..ac197a3c6b5f 100644
--- a/src/southbridge/amd/pi/hudson/smbus.h
+++ b/src/southbridge/amd/pi/hudson/smbus.h
@@ -18,29 +18,29 @@
 
 #include <stdint.h>
 
-#define SMBHSTSTAT 0x0
-#define SMBSLVSTAT 0x1
-#define SMBHSTCTRL 0x2
-#define SMBHSTCMD  0x3
-#define SMBHSTADDR 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBHSTBLKDAT 0x7
+#define SMBHSTSTAT		0x0
+#define SMBSLVSTAT		0x1
+#define SMBHSTCTRL		0x2
+#define SMBHSTCMD		0x3
+#define SMBHSTADDR		0x4
+#define SMBHSTDAT0		0x5
+#define SMBHSTDAT1		0x6
+#define SMBHSTBLKDAT		0x7
 
-#define SMBSLVCTRL 0x8
-#define SMBSLVCMD_SHADOW 0x9
-#define SMBSLVEVT 0xa
-#define SMBSLVDAT 0xc
+#define SMBSLVCTRL		0x8
+#define SMBSLVCMD_SHADOW	0x9
+#define SMBSLVEVT		0xa
+#define SMBSLVDAT		0xc
 
-#define AX_INDXC  0
-#define AX_INDXP  2
-#define AXCFG     4
-#define ABCFG     6
-#define RC_INDXC  1
-#define RC_INDXP  3
+#define AX_INDXC		0
+#define AX_INDXP		2
+#define AXCFG			4
+#define ABCFG			6
+#define RC_INDXC		1
+#define RC_INDXP		3
 
-#define AB_INDX   0xCD8
-#define AB_DATA   (AB_INDX+4)
+#define AB_INDX			0xCD8
+#define AB_DATA			(AB_INDX+4)
 
 /* Between 1-10 seconds, We should never timeout normally
  * Longer than this is just painful when a timeout condition occurs.