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| author | Furquan Shaikh <furquan@chromium.org> | 2017-12-07 18:39:34 -0800 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2018-01-10 19:26:27 +0000 |
| commit | 1876f3ae4530fa691c9d6e88f3f7f8807d57d318 (patch) | |
| tree | 660a1ff0519ffbab6ae9d7db4fd62ac920e3e0f2 /src | |
| parent | 044dfe9b6926397ed017bd101b887ef55f6a4d18 (diff) | |
| download | coreboot-1876f3ae4530fa691c9d6e88f3f7f8807d57d318.tar.gz coreboot-1876f3ae4530fa691c9d6e88f3f7f8807d57d318.tar.bz2 coreboot-1876f3ae4530fa691c9d6e88f3f7f8807d57d318.zip | |
soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock
This change adds a call to gspi_early_bar_init in bootblock to
allocate a temporary BAR for any GSPI buses that are accessed before
resource allocation is done in ramstage.
Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22781
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/bootblock/pch.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index cca70c21ad0b..47eaceb3f98c 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/pmclib.h> @@ -98,6 +99,7 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); enable_p2sbbar(); /* * Enabling PWRM Base for accessing |