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| author | Angel Pons <th3fanbus@gmail.com> | 2021-09-08 15:23:22 +0200 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2024-04-16 01:46:42 +0000 |
| commit | 41d107019b6bcbdad80a1d76abca7a181fd339d5 (patch) | |
| tree | a61c836cb2f7f3eed815ae340de95ad5e92cbdc9 /src | |
| parent | 6ef23316c235d14213d0bdc48c6853d3059a0b64 (diff) | |
| download | coreboot-41d107019b6bcbdad80a1d76abca7a181fd339d5.tar.gz coreboot-41d107019b6bcbdad80a1d76abca7a181fd339d5.tar.bz2 coreboot-41d107019b6bcbdad80a1d76abca7a181fd339d5.zip | |
sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
Program the AER capability header register in a single write because
it's write-once. In addition, only PCH-LP supports L1 sub-states, so
only report the L1 sub-state capability on PCH-LP. This follows what
Lynx Point PCH reference code version 1.9.1 does.
Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 30a34f757afd..766ed433d5d2 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -670,20 +670,22 @@ static void pch_pcie_early(struct device *dev) /* Set EOI forwarding disable. */ pci_or_config32(dev, 0xd4, 1 << 1); - /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - if (CONFIG(PCIEXP_AER)) - pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); - else - pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); - - /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - if (CONFIG(PCIEXP_L1_SUB_STATE)) - pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); - else - pci_update_config32(dev, 0x200, ~0xfffff, 0); + /* Set AER Extended Cap ID to 01h */ + u32 aech = CONFIG(PCIEXP_AER) ? 0x10001 : 0; + /* For PCH-LP, set Next Cap Pointer to 200h. */ if (is_lp) - pci_or_config32(dev, 0x100, 1 << 29); + aech |= 1 << 29; + + pci_update_config32(dev, 0x100, ~0xfffff, aech); + + if (is_lp) { + /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pci_update_config32(dev, 0x200, ~0xfffff, 0x001e); + else + pci_update_config32(dev, 0x200, ~0xfffff, 0); + } /* Read and write back write-once capability registers. */ pci_update_config32(dev, 0x34, ~0, 0); |