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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-11-18 14:56:01 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-01-15 09:34:51 +0000 |
| commit | 4520fc6af9b1a5973fabfd76028ca164d1333be2 (patch) | |
| tree | da4d72ad2d61df4d9b1fe20541d0284b2403fdd4 /src | |
| parent | a48debdaa0124c57bef67c9ac90e955e69671d56 (diff) | |
| download | coreboot-4520fc6af9b1a5973fabfd76028ca164d1333be2.tar.gz coreboot-4520fc6af9b1a5973fabfd76028ca164d1333be2.tar.bz2 coreboot-4520fc6af9b1a5973fabfd76028ca164d1333be2.zip | |
sb/intel/bd82x6x/sata: Enable SATA clock gating
Program SATA IOBP and enable clock gating after port enable
bits have been written.
The same registers are already set for DMI and PCIe.
TEST: Lenovo X220 still boots over SATA.
Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79146
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/sata.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 9dc58fdcedd6..a30c01a94ce8 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -219,6 +219,10 @@ static void sata_init(struct device *dev) ~(1 << 16 | 0x3f << 7 | 3 << 5 | 3 << 3), 1 << 24 | 1 << 22 | 1 << 20 | 1 << 19 | 1 << 18 | 1 << 14 | 0x04 << 7 | 1 << 3); + + /* SATA clock gating. Must be done after writing register 0x94. */ + pch_iobp_update(0xEA007F07, ~0U, (1 << 31)); + pch_iobp_update(0xEA004000, ~0U, (1 << 7)); } static void sata_enable(struct device *dev) |