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| author | Weimin Wu <wuweimin@huaqin.corp-partner.google.com> | 2023-12-13 10:15:00 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-12-14 13:07:55 +0000 |
| commit | 5ba045c715d7c8cbd4abee0c844e8a1a3e3a1370 (patch) | |
| tree | 864d30c4f1f3924789a605bca1ae3f480c213d49 /src | |
| parent | 6215ef47cdc05445fae6070cea27dba9dca40a24 (diff) | |
| download | coreboot-5ba045c715d7c8cbd4abee0c844e8a1a3e3a1370.tar.gz coreboot-5ba045c715d7c8cbd4abee0c844e8a1a3e3a1370.tar.bz2 coreboot-5ba045c715d7c8cbd4abee0c844e8a1a3e3a1370.zip | |
mb/google/nissa/var/anraggar: Update DTT settings for thermal control
Update DTT settings based on the suggestion of the thermal.
BUG=b:313833488
TEST=emerge-nissa coreboot
Change-Id: I2296990062cadc05202e3d1ab90af04234bda885
Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/anraggar/overridetree.cb | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index 9ceed5446d4a..938b575f414c 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -132,31 +132,31 @@ chip soc/intel/alderlake device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""Memory"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[0].desc" = ""CPU_VR"" + register "options.tsr[1].desc" = ""CPU"" register "options.tsr[2].desc" = ""Ambient"" + register "options.tsr[3].desc" = ""Charger"" # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), - [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000), + [4] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_3, 75, 5000), }" ## Critical Policy register "policies.critical" = "{ - [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), - [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), - [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN), }" register "controls.power_limits" = "{ .pl1 = { - .min_power = 3000, - .max_power = 6000, + .min_power = 6000, + .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200 @@ -172,7 +172,7 @@ chip soc/intel/alderlake ## Charger Performance Control (Control, mA) register "controls.charger_perf" = "{ - [0] = { 255, 1700 }, + [0] = { 255, 3000 }, [1] = { 24, 1500 }, [2] = { 16, 1000 }, [3] = { 8, 500 } |