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| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-08-18 11:15:43 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-08-18 11:15:43 +0000 |
| commit | 1b226223237a3e3bcd9bdbe12316d06b323b34b3 (patch) | |
| tree | deef770a49ec17fa1c255d8b0f9ccd3aad7019c6 /superio | |
| parent | 7102949d768c0bc187d9b27b6beccdbb237b1b1c (diff) | |
| download | coreboot-1b226223237a3e3bcd9bdbe12316d06b323b34b3.tar.gz coreboot-1b226223237a3e3bcd9bdbe12316d06b323b34b3.tar.bz2 coreboot-1b226223237a3e3bcd9bdbe12316d06b323b34b3.zip | |
Change v3 makefile rules to be source-based, part I.
The individual makefiles in lib/ mainboard/ southbridge/ and superio/
have been changed accordingly and the big glue layer in
arch/x86Makefile has been modified to wrap the new rules correctly.
This pepares the way for additional optimizations during compile and
link time.
Build tested and boot tested on Qemu.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@782 f3766cd6-281f-0410-b1cd-43a5c92072e9
Diffstat (limited to 'superio')
| -rw-r--r-- | superio/fintek/f71805f/Makefile | 4 | ||||
| -rw-r--r-- | superio/ite/it8716f/Makefile | 4 | ||||
| -rw-r--r-- | superio/winbond/w83627hf/Makefile | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/superio/fintek/f71805f/Makefile b/superio/fintek/f71805f/Makefile index 078b6e0c934c..e37e696d711f 100644 --- a/superio/fintek/f71805f/Makefile +++ b/superio/fintek/f71805f/Makefile @@ -20,8 +20,8 @@ ifeq ($(CONFIG_SUPERIO_FINTEK_F71805F),y) -STAGE0_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/stage1.o -STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o +STAGE0_CHIPSET_SRC += $(src)/superio/fintek/f71805f/stage1.c +STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c # Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c diff --git a/superio/ite/it8716f/Makefile b/superio/ite/it8716f/Makefile index b1c60ee9fc3c..801d35b3ddc3 100644 --- a/superio/ite/it8716f/Makefile +++ b/superio/ite/it8716f/Makefile @@ -20,8 +20,8 @@ ifeq ($(CONFIG_SUPERIO_ITE_IT8716F),y) -STAGE0_CHIPSET_OBJ += $(obj)/superio/ite/it8716f/stage1.o -STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o +STAGE0_CHIPSET_SRC += $(src)/superio/ite/it8716f/stage1.c +STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c # Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8716f/superio.c diff --git a/superio/winbond/w83627hf/Makefile b/superio/winbond/w83627hf/Makefile index 0b64378d0fb8..cedf89c1c37f 100644 --- a/superio/winbond/w83627hf/Makefile +++ b/superio/winbond/w83627hf/Makefile @@ -21,8 +21,8 @@ ifeq ($(CONFIG_SUPERIO_WINBOND_W83627HF),y) -STAGE0_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/stage1.o -STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o +STAGE0_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/stage1.c +STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c # Always add to variables, as there could be more than one Super I/O. STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c |