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author | Johnny Lin <johnny_lin@wiwynn.com> | 2023-05-11 09:40:58 +0800 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-23 20:26:13 +0000 |
commit | b7dc12dc6c55f5664fb716095f9faea107a48771 (patch) | |
tree | 60182f9dbf0c86ed28a03ce91934e5cfb10c5d74 /tests/data | |
parent | f89cd1cf43b4afbd78dbf14ad71bfba92a28029f (diff) | |
download | coreboot-b7dc12dc6c55f5664fb716095f9faea107a48771.tar.gz coreboot-b7dc12dc6c55f5664fb716095f9faea107a48771.tar.bz2 coreboot-b7dc12dc6c55f5664fb716095f9faea107a48771.zip |
mb/intel/archercity_crb: Add EWL Hob processing for MRC error
Override the weak function mainboard_ewl_check() and select OCP_EWL.
Select IPMI_KCS_ROMSTAGE and IPMI_OCP for OCP IPMI commands which are
needed for OCP EWL driver, but they are Meta-specific BMC commands
and don't really work for AC, this change is just for a demonstration
with AC.
Note that FSP UPD promoteWarnings needs to be disabled so that
FSP won't block and can return to coreboot for EWL processing
when memory EWL type 3 error occurs.
Tested=On Intel AC, connected with a faulty DIMM can see
EWL type 3 error being generated and halted with coreboot log:
[DEBUG] Number of EWL entries 3
[ERROR] EWL type: 3 size:32 severity level:1
[ERROR] Major Warning Code = 0x29, Minor Warning Code = 0x04,
[ERROR] Major Checkpoint: 0xb7
[ERROR] Minor Checkpoint: 0x74
[ERROR] Socket 0
[ERROR] Channel 4
[ERROR] Dimm 0
[ERROR] Rank 0
[ERROR] IPMI: ipmi_get_board_config command failed (ret=3 resp=0xc1)
[DEBUG] ipmi send memory training error
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e968: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e978: 00 00 00
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e97b: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e98b: 00 00 01
[EMERG] Memory Training Error!
Change-Id: I4602ae356aa6e55ed0611b8ac9a206db127c297c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'tests/data')
0 files changed, 0 insertions, 0 deletions