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author | Siyuan Wang <wangsiyuanbuaa@gmail.com> | 2012-10-28 18:19:38 +0800 |
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committer | Marc Jones <marcj303@gmail.com> | 2012-11-30 20:11:54 +0100 |
commit | 8ff97b2973329ee7e3b50471a10f63bbbe13b0ee (patch) | |
tree | bcdd77a57d164f2461efd658ba747a2ea850864c /util/cbfstool/common.c | |
parent | e7d6f02ca4934319b11ad99fdd92c3e4cf2234be (diff) | |
download | coreboot-8ff97b2973329ee7e3b50471a10f63bbbe13b0ee.tar.gz coreboot-8ff97b2973329ee7e3b50471a10f63bbbe13b0ee.tar.bz2 coreboot-8ff97b2973329ee7e3b50471a10f63bbbe13b0ee.zip |
Supermicro h8scm: add agesa version of supermicro
Supermicro h8scm has a C32 CPU socket, the details of this board is:
http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm
We are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support
family 15 CPU, so we update this mainboard with this patch.
This code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation.
If you want to change the frequency of memory, please edit the macros
"BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT" and "BLDCFG_MEMORY_CLOCK_SELECT"
in src/mainboard/supermicro/h8scm/buildOpts.c
Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1510
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'util/cbfstool/common.c')
0 files changed, 0 insertions, 0 deletions