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| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-11-29 14:35:49 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-13 17:36:19 +0200 |
| commit | 11093995e4cddfc6db16ad654c3e0d39440f74ff (patch) | |
| tree | a41c1843acd11e9eb32e9ad6c072f4e07717f844 /util/ipqheader | |
| parent | e230313ff76cdc9bf6342a56c9974ec64267dc80 (diff) | |
| download | coreboot-11093995e4cddfc6db16ad654c3e0d39440f74ff.tar.gz coreboot-11093995e4cddfc6db16ad654c3e0d39440f74ff.tar.bz2 coreboot-11093995e4cddfc6db16ad654c3e0d39440f74ff.zip | |
mips: disable caches in bootblock startup code
Until proper MIPS cache management is available it is necessary to
disable data and instruction caches, otherwise code placed in memory
stays in data cache and is not available for instruction fetched.
BRANCH=none
BUG=chrome-os-partner:31438,chrome-os-partner:34127
TEST=coreboot loading rombase and rambase now succeeds.
Change-Id: I4147e1325edc0b9bb951cd7ce18d5f104f3eaec0
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 93d5bfa1d01fbbabbabef33a22287ceeea28b15b
Original-Change-Id: Ib195ed6e5f08ccaa6bbe3325c2199171bfb63b88
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/232191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9569
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'util/ipqheader')
0 files changed, 0 insertions, 0 deletions