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| author | Eric Biederman <ebiederm@xmission.com> | 2003-06-18 11:03:18 +0000 |
|---|---|---|
| committer | Eric Biederman <ebiederm@xmission.com> | 2003-06-18 11:03:18 +0000 |
| commit | d3283ec05f51056faa18610e952ccc81cb738313 (patch) | |
| tree | 71279430d699e679cda9371fa7cf26005cc8b927 /util/romcc/Makefile | |
| parent | 99acb49cf71ee7038216391ae2b0d09675ab6ce5 (diff) | |
| download | coreboot-d3283ec05f51056faa18610e952ccc81cb738313.tar.gz coreboot-d3283ec05f51056faa18610e952ccc81cb738313.tar.bz2 coreboot-d3283ec05f51056faa18610e952ccc81cb738313.zip | |
- A new test case for romcc
- Minor romcc fixes
- In smbus_wail_until_done a romcc glitch with || in romcc where it likes
to run out of registers. Use | to be explicit that I don't need the short
circuiting behavior.
- Remove unused #defines from coherent_ht.c
- Update the test in auto.c to 512M
- Add definition of log2 to romcc_io.h
- Implement SPD memory sizing in raminit.c
- Reduce the number of memory devices back 2 to for the SOLO board.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/romcc/Makefile')
| -rw-r--r-- | util/romcc/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/util/romcc/Makefile b/util/romcc/Makefile index be2d031055a6..9722ca3fc7c7 100644 --- a/util/romcc/Makefile +++ b/util/romcc/Makefile @@ -51,6 +51,7 @@ TESTS=\ simple_test30.c \ simple_test31.c \ simple_test32.c \ + simple_test33.c \ raminit_test.c \ raminit_test2.c \ raminit_test3.c \ |