diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-27 06:56:47 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-27 06:56:47 +0000 |
| commit | 14e22779625de673569c7b950ecc2753fb915b31 (patch) | |
| tree | 14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /util/romcc/tests | |
| parent | 0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff) | |
| download | coreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.gz coreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.bz2 coreboot-14e22779625de673569c7b950ecc2753fb915b31.zip | |
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'util/romcc/tests')
58 files changed, 1327 insertions, 1327 deletions
diff --git a/util/romcc/tests/fail_test10.c b/util/romcc/tests/fail_test10.c index 1993e0e59cfc..7cfd9a9c3bbd 100644 --- a/util/romcc/tests/fail_test10.c +++ b/util/romcc/tests/fail_test10.c @@ -14,6 +14,6 @@ static struct result main(int a, int b, struct big_arg d) result.b = 1; result.c = b + 1; result.d = a + 1; - + } diff --git a/util/romcc/tests/fail_test2.c b/util/romcc/tests/fail_test2.c index 74d6eb1d94ee..6a02486a8dc2 100644 --- a/util/romcc/tests/fail_test2.c +++ b/util/romcc/tests/fail_test2.c @@ -3,16 +3,16 @@ static void main(void) unsigned min; int value, latency; - - + + latency = -2; - + if (latency > (((min) >> 8) & 0xff)) { value = 0xa; } - + if (value < 0) return; - + ((min) = (((min) & ~0xff))); } diff --git a/util/romcc/tests/hello_world.c b/util/romcc/tests/hello_world.c index b5ce540dc958..cba88a9a6d01 100644 --- a/util/romcc/tests/hello_world.c +++ b/util/romcc/tests/hello_world.c @@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -96,7 +96,7 @@ void uart_init(void) void __console_tx_char(unsigned char byte) { uart_tx_byte(byte); - + } void __console_tx_string(char *str) diff --git a/util/romcc/tests/hello_world1.c b/util/romcc/tests/hello_world1.c index b5ce540dc958..cba88a9a6d01 100644 --- a/util/romcc/tests/hello_world1.c +++ b/util/romcc/tests/hello_world1.c @@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -96,7 +96,7 @@ void uart_init(void) void __console_tx_char(unsigned char byte) { uart_tx_byte(byte); - + } void __console_tx_string(char *str) diff --git a/util/romcc/tests/hello_world2.c b/util/romcc/tests/hello_world2.c index 18380d37e894..c6e8092ed31d 100644 --- a/util/romcc/tests/hello_world2.c +++ b/util/romcc/tests/hello_world2.c @@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -96,7 +96,7 @@ void uart_init(void) void __console_tx_char(unsigned char byte) { uart_tx_byte(byte); - + } void __console_tx_string(char *str) diff --git a/util/romcc/tests/include/linux_console.h b/util/romcc/tests/include/linux_console.h index 861c701e5d5f..5f9dec21f95e 100644 --- a/util/romcc/tests/include/linux_console.h +++ b/util/romcc/tests/include/linux_console.h @@ -6,37 +6,37 @@ static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; diff --git a/util/romcc/tests/include/linuxi386_syscall.h b/util/romcc/tests/include/linuxi386_syscall.h index d202661c67ba..30b4a2c6e004 100644 --- a/util/romcc/tests/include/linuxi386_syscall.h +++ b/util/romcc/tests/include/linuxi386_syscall.h @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 diff --git a/util/romcc/tests/linux_console.h b/util/romcc/tests/linux_console.h index 0837dfc5771e..1b6466eca11c 100644 --- a/util/romcc/tests/linux_console.h +++ b/util/romcc/tests/linux_console.h @@ -6,37 +6,37 @@ static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; diff --git a/util/romcc/tests/linux_test13.c b/util/romcc/tests/linux_test13.c index 83ef239854b7..9bc80eac7dbe 100644 --- a/util/romcc/tests/linux_test13.c +++ b/util/romcc/tests/linux_test13.c @@ -43,5 +43,5 @@ static void main(void) print_debug("A\n"); dimm_mask = spd_detect_dimms(cpu); print_debug("B\n"); - _exit(0); + _exit(0); } diff --git a/util/romcc/tests/linux_test2.c b/util/romcc/tests/linux_test2.c index 8f40fa0d473b..766f498a0a5a 100644 --- a/util/romcc/tests/linux_test2.c +++ b/util/romcc/tests/linux_test2.c @@ -70,14 +70,14 @@ static void setup_coherent_ht_domain(void) (((FN) & 0x07) << 8) | \ ((WHERE) & 0xFF)) - /* Routing Table Node i - * F0:0x40 i = 0, + /* Routing Table Node i + * F0:0x40 i = 0, * F0:0x44 i = 1, - * F0:0x48 i = 2, + * F0:0x48 i = 2, * F0:0x4c i = 3, - * F0:0x50 i = 4, + * F0:0x50 i = 4, * F0:0x54 i = 5, - * F0:0x58 i = 6, + * F0:0x58 i = 6, * F0:0x5c i = 7 * [ 0: 3] Request Route * [0] Route to this node @@ -104,7 +104,7 @@ static void setup_coherent_ht_domain(void) PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101, PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101, - /* Hypetransport Transaction Control Register + /* Hypetransport Transaction Control Register * F0:0x68 * [ 0: 0] Disable read byte probe * 0 = Probes issues @@ -146,7 +146,7 @@ static void setup_coherent_ht_domain(void) * [12:12] Change ISOC to Ordered * 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization * 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering. - * [14:13] Buffer Release Priority select + * [14:13] Buffer Release Priority select * 00 = 64 * 01 = 16 * 10 = 8 @@ -253,7 +253,7 @@ static void setup_coherent_ht_domain(void) * [13:13] HT Stop Tristate Enable * 0 = Driven during an LDTSTOP_L * 1 = Tristated during and LDTSTOP_L - * [14:14] Extended CTL Time + * [14:14] Extended CTL Time * 0 = CTL is asserted for 16 bit times during link initialization * 1 = CTL is asserted for 50us during link initialization * [18:16] Max Link Width In (Read-Only?) @@ -519,7 +519,7 @@ static void setup_coherent_ht_domain(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003, @@ -580,7 +580,7 @@ static void setup_coherent_ht_domain(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -588,7 +588,7 @@ static void setup_coherent_ht_domain(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003, diff --git a/util/romcc/tests/linux_test3.c b/util/romcc/tests/linux_test3.c index 97187ae5e6c3..4c7a882f7553 100644 --- a/util/romcc/tests/linux_test3.c +++ b/util/romcc/tests/linux_test3.c @@ -4,15 +4,15 @@ static void goto_test(void) { int i; print_debug("goto_test\n"); - + i = 0; goto bottom; { top: - print_debug("i = "); - print_debug_hex8(i); + print_debug("i = "); + print_debug_hex8(i); print_debug("\n"); - + i = i + 1; } bottom: diff --git a/util/romcc/tests/linux_test4.c b/util/romcc/tests/linux_test4.c index 1f099183625b..71f4d6541e11 100644 --- a/util/romcc/tests/linux_test4.c +++ b/util/romcc/tests/linux_test4.c @@ -7,7 +7,7 @@ struct socket_desc { short across; }; -static void main(void) +static void main(void) { static const struct socket_desc cpu_socketsA[] = { { .up = 2, .down = -1, .across = 1 }, /* Node 0 */ diff --git a/util/romcc/tests/linux_test5.c b/util/romcc/tests/linux_test5.c index 13093fb0fcdf..473f57289deb 100644 --- a/util/romcc/tests/linux_test5.c +++ b/util/romcc/tests/linux_test5.c @@ -4,7 +4,7 @@ inline int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -91,8 +91,8 @@ static unsigned spd_to_dimm(unsigned device) static void disable_dimm(unsigned index) { - print_debug("disabling dimm"); - print_debug_hex8(index); + print_debug("disabling dimm"); + print_debug_hex8(index); print_debug("\r\n"); #if 0 pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0); @@ -175,8 +175,8 @@ static const struct mem_param *spd_set_memclk(void) min_latency = 2; #if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); + print_debug("min_cycle_time: "); + print_debug_hex8(min_cycle_time); print_debug(" min_latency: "); print_debug_hex8(min_latency); print_debug("\r\n"); @@ -236,8 +236,8 @@ static const struct mem_param *spd_set_memclk(void) #if 1 print_debug("device: "); print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); + print_debug(" new_cycle_time: "); + print_debug_hex8(new_cycle_time); print_debug(" new_latency: "); print_debug_hex8(new_latency); print_debug("\r\n"); @@ -249,8 +249,8 @@ static const struct mem_param *spd_set_memclk(void) #if 1 print_debug("device: "); print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); + print_debug(" new_cycle_time: "); + print_debug_hex8(new_cycle_time); print_debug(" new_latency: "); print_debug_hex8(new_latency); print_debug("\r\n"); @@ -270,8 +270,8 @@ static const struct mem_param *spd_set_memclk(void) #if 1 print_debug("device: "); print_debug_hex8(device); - print_debug(" min_cycle_time: "); - print_debug_hex8(min_cycle_time); + print_debug(" min_cycle_time: "); + print_debug_hex8(min_cycle_time); print_debug(" min_latency: "); print_debug_hex8(min_latency); print_debug("\r\n"); @@ -309,11 +309,11 @@ static const struct mem_param *spd_set_memclk(void) if ((latency != min_latency) || (index >= 3)) { goto dimm_err; } - + /* Read the min_cycle_time for this latency */ value = smbus_read_byte(device, latency_indicies[index]); - - /* All is good if the selected clock speed + + /* All is good if the selected clock speed * is what I need or slower. */ if (value <= min_cycle_time) { @@ -324,8 +324,8 @@ static const struct mem_param *spd_set_memclk(void) disable_dimm(spd_to_dimm(device)); } #if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); + print_debug("min_cycle_time: "); + print_debug_hex8(min_cycle_time); print_debug(" min_latency: "); print_debug_hex8(min_latency); print_debug("\r\n"); @@ -347,7 +347,7 @@ static const struct mem_param *spd_set_memclk(void) value |= latencies[min_latency - 2]; pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value); #endif - + return param; } diff --git a/util/romcc/tests/linuxi386_syscall.h b/util/romcc/tests/linuxi386_syscall.h index 7eb513db36f1..96a5936c3c4e 100644 --- a/util/romcc/tests/linuxi386_syscall.h +++ b/util/romcc/tests/linuxi386_syscall.h @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 diff --git a/util/romcc/tests/raminit_test.c b/util/romcc/tests/raminit_test.c index 2c6fa8c750d8..569d75ba62e8 100644 --- a/util/romcc/tests/raminit_test.c +++ b/util/romcc/tests/raminit_test.c @@ -136,7 +136,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -355,7 +355,7 @@ int smbus_read_byte(unsigned device, unsigned address) /* CAS latency 2 */ #if (CAS_LATENCY == 2) #define CAS_NB 0x17 - /* + /* * 7 == 0111 * 1 == 0001 */ @@ -367,7 +367,7 @@ int smbus_read_byte(unsigned device, unsigned address) #endif /* CAS latency 3 */ -#if (CAS_LATENCY == 3) +#if (CAS_LATENCY == 3) #define CAS_NB 0x13 /* * 3 == 0011 @@ -381,11 +381,11 @@ int smbus_read_byte(unsigned device, unsigned address) #endif #ifndef CAS_NB -#error "Nothing defined" +#error "Nothing defined" #endif /* Default values for config registers */ - + static void set_nbxcfg(void) { /* NBXCFG 0x50 - 0x53 */ @@ -417,7 +417,7 @@ static void set_nbxcfg(void) * ECC Diagnostic Mode Enable == 0 Not Enabled * MDA present == 0 Not Present * USWC Write Post During During I/O Bridge Access Enable == 1 Enabled - * In Order Queue Depth (IQD) (RO) == ?? + * In Order Queue Depth (IQD) (RO) == ?? */ pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c); } @@ -486,7 +486,7 @@ static void set_mbsc(void) * MD[63:0]# Buffer Strength Control 1 == 3x * MECC[7:0] Buffer Strength Control 2 == 3x * MECC[7:0] Buffer Strength Control 1 == 3x - * CSB7# Buffer Strength == 3x + * CSB7# Buffer Strength == 3x * CSA7# Buffer Strength == 3x * CSB6# Buffer Strength == 3x * CSA6# Buffer Strength == 3x @@ -575,13 +575,13 @@ static void set_pgpol(void) static void set_mbfs(void) { /* MBFS - Memory Buffer Frequencey Select Register */ - /* 0xffff7f - * [23:20] f == 1111 - * [19:16] f == 1111 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 7 == 0111 - * [ 3: 0] f == 1111 + /* 0xffff7f + * [23:20] f == 1111 + * [19:16] f == 1111 + * [15:12] f == 1111 + * [11: 8] f == 1111 + * [ 7: 4] 7 == 0111 + * [ 3: 0] f == 1111 * MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled * MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled * MD[63:0] Control 2 == 100 Mhz Buffer Enable @@ -622,12 +622,12 @@ static void set_drtc(void) static void set_pmcr(void) { - /* PMCR -- BIOS sets 0x90 into it. + /* PMCR -- BIOS sets 0x90 into it. * 0x10 is REQUIRED. * we have never used it. So why did this ever work? */ pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90); - + } void sdram_set_registers(void) { @@ -651,7 +651,7 @@ void sdram_set_registers(void) int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -670,7 +670,7 @@ static void spd_set_drb(void) unsigned end_of_memory; unsigned device; unsigned drb_reg; - + end_of_memory = 0; /* in multiples of 8MiB */ device = SMBUS_MEM_DEVICE_START; drb_reg = 0x60; @@ -704,13 +704,13 @@ static void spd_set_drb(void) #else side1_bits += log2((byte2 << 8) | byte); #endif - + /* now I have the ram size in bits as a power of two (less 1) */ /* Make it mulitples of 8MB */ side1_bits -= 25; - + /* side two */ - + /* number of physical banks */ byte = smbus_read_byte(device, 5); if (byte > 1) { @@ -783,8 +783,8 @@ static void spd_set_dramc(void) } dramc = 0x8; if ((byte & 0x12) != 0) { - /* this is a registered part. - * observation: for register parts, BIOS zeros (!) + /* this is a registered part. + * observation: for register parts, BIOS zeros (!) * registers CA-CC. This has an undocumented meaning. */ /* But it does make sense the oppisite of registered @@ -835,7 +835,7 @@ static void spd_enable_refresh(void) } byte &= 0x7f; /* Default refresh rate be conservative */ - refresh_rate = 5; + refresh_rate = 5; /* see if the ram refresh is a supported one */ if (byte < 6) { #if HAVE_STATIC_ARRAY_SUPPORT @@ -856,7 +856,7 @@ static void spd_set_sdramc(void) static void spd_set_rps(void) { /* - * Effects: Uses serial presence detect to set the row size + * Effects: Uses serial presence detect to set the row size * on a given DIMM * FIXME: Check for illegal/unsupported ram configurations and abort */ @@ -881,16 +881,16 @@ static void spd_set_rps(void) page_size = byte & 0xf; /* make it in multiples of 2Kb */ page_size -= 11; - + if (page_size <= 0) continue; - + /* FIXME: do something with page sizes greather than 8KB!! */ page_sizes |= (page_size << index); - + /* side two */ byte = smbus_read_byte(device, 5); if (byte <= 1) continue; - + /* For now only handle the symmetrical case */ page_sizes |= (page_size << (index +2)); } @@ -898,10 +898,10 @@ static void spd_set_rps(void) /* we have just verified that we have to have this code. It appears that * the registered SDRAMs do indeed set the RPS wrong. sheesh. */ - /* at this point, page_sizes holds the RPS for all ram. - * we have verified that for registered DRAM the values are + /* at this point, page_sizes holds the RPS for all ram. + * we have verified that for registered DRAM the values are * 1/2 the size they should be. So we test for registered - * and then double the sizes if needed. + * and then double the sizes if needed. */ dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); @@ -909,9 +909,9 @@ static void spd_set_rps(void) /* registered */ /* BIOS makes weird page size for registered! */ - /* what we have found is you need to set the EVEN banks to - * twice the size. Fortunately there is a very easy way to - * do this. First, read the WORD value of register 0x74. + /* what we have found is you need to set the EVEN banks to + * twice the size. Fortunately there is a very easy way to + * do this. First, read the WORD value of register 0x74. */ page_sizes += 0x1111; } @@ -938,8 +938,8 @@ static void spd_set_pgpol(void) bank_sizes = 0; bank = 0; device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; - bank += 2, device += SMBUS_MEM_DEVICE_INC) { + for(; device <= SMBUS_MEM_DEVICE_END; + bank += 2, device += SMBUS_MEM_DEVICE_INC) { int byte; /* logical banks */ @@ -947,7 +947,7 @@ static void spd_set_pgpol(void) if (byte < 0) continue; if (byte < 4) continue; bank_sizes |= (1 << bank); - + /* side 2 */ /* Number of physical banks */ byte = smbus_read_byte(device, 5); @@ -974,14 +974,14 @@ static void spd_set_nbxcfg(void) /* Say all dimms have no ECC support */ reg = 0xff; index = 0; - + device = SMBUS_MEM_DEVICE_START; for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) { int byte; byte = smbus_read_byte(device, 11); if (byte < 0) continue; -#if !USE_ECC +#if !USE_ECC byte = 0; /* Disable ECC */ #endif /* 0 == None, 1 == Parity, 2 == ECC */ @@ -1015,7 +1015,7 @@ static void spd_set_nbxcfg(void) /* try this. * We should be setting bit 2 in register 76 and we're not * technically we should see if CL=2 for the ram, - * but registered is so screwed up that it's kind of a lost + * but registered is so screwed up that it's kind of a lost * cause. */ byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); @@ -1098,7 +1098,7 @@ static void dimms_read(unsigned long offset) int i; for(i = 0; i < 8; i++) { unsigned long dummy; - unsigned long addr; + unsigned long addr; unsigned long next_base; next_base = dimm_base(i +1); @@ -1108,8 +1108,8 @@ static void dimms_read(unsigned long offset) } addr += offset; #if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr); + print_debug("Reading "); + print_debug_hex32(addr); print_debug("\n"); #endif #if HAVE_POINTER_SUPPORT @@ -1120,8 +1120,8 @@ static void dimms_read(unsigned long offset) #endif #endif #if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr ^ 0xddf8); + print_debug("Reading "); + print_debug_hex32(addr ^ 0xddf8); print_debug("\n"); #endif #if HAVE_POINTER_SUPPORT @@ -1132,9 +1132,9 @@ static void dimms_read(unsigned long offset) #endif #endif #if HAVE_STRING_SUPPORT - print_debug("Read "); - print_debug_hex32(addr); - print_debug_hex32(addr ^ 0xddf8); + print_debug("Read "); + print_debug_hex32(addr); + print_debug_hex32(addr ^ 0xddf8); print_debug("\n"); #endif } @@ -1212,9 +1212,9 @@ void sdram_enable(void) #if HAVE_STRING_SUPPORT print_debug("Ram Enable 2\n"); #endif - + /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ - + sdram_set_command_cbr(); sdram_assert_command(); sdram_assert_command(); @@ -1224,11 +1224,11 @@ void sdram_enable(void) sdram_assert_command(); sdram_assert_command(); sdram_assert_command(); - + #if HAVE_STRING_SUPPORT print_debug("Ram Enable 3\n"); #endif - + /* mode register set */ sdram_set_mode_register(); /* MAx[14:0] lines, @@ -1245,7 +1245,7 @@ void sdram_enable(void) /* normal operation */ sdram_set_command_none(); - + #if HAVE_STRING_SUPPORT print_debug("Ram Enable 5\n"); #endif @@ -1270,7 +1270,7 @@ void sdram_initialize(void) print_debug("Ram3\n"); #endif /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for use while on others + * Some chipsets do the work for use while on others * we need to it by hand. */ sdram_enable(); diff --git a/util/romcc/tests/raminit_test1.c b/util/romcc/tests/raminit_test1.c index 2c6fa8c750d8..569d75ba62e8 100644 --- a/util/romcc/tests/raminit_test1.c +++ b/util/romcc/tests/raminit_test1.c @@ -136,7 +136,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -355,7 +355,7 @@ int smbus_read_byte(unsigned device, unsigned address) /* CAS latency 2 */ #if (CAS_LATENCY == 2) #define CAS_NB 0x17 - /* + /* * 7 == 0111 * 1 == 0001 */ @@ -367,7 +367,7 @@ int smbus_read_byte(unsigned device, unsigned address) #endif /* CAS latency 3 */ -#if (CAS_LATENCY == 3) +#if (CAS_LATENCY == 3) #define CAS_NB 0x13 /* * 3 == 0011 @@ -381,11 +381,11 @@ int smbus_read_byte(unsigned device, unsigned address) #endif #ifndef CAS_NB -#error "Nothing defined" +#error "Nothing defined" #endif /* Default values for config registers */ - + static void set_nbxcfg(void) { /* NBXCFG 0x50 - 0x53 */ @@ -417,7 +417,7 @@ static void set_nbxcfg(void) * ECC Diagnostic Mode Enable == 0 Not Enabled * MDA present == 0 Not Present * USWC Write Post During During I/O Bridge Access Enable == 1 Enabled - * In Order Queue Depth (IQD) (RO) == ?? + * In Order Queue Depth (IQD) (RO) == ?? */ pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c); } @@ -486,7 +486,7 @@ static void set_mbsc(void) * MD[63:0]# Buffer Strength Control 1 == 3x * MECC[7:0] Buffer Strength Control 2 == 3x * MECC[7:0] Buffer Strength Control 1 == 3x - * CSB7# Buffer Strength == 3x + * CSB7# Buffer Strength == 3x * CSA7# Buffer Strength == 3x * CSB6# Buffer Strength == 3x * CSA6# Buffer Strength == 3x @@ -575,13 +575,13 @@ static void set_pgpol(void) static void set_mbfs(void) { /* MBFS - Memory Buffer Frequencey Select Register */ - /* 0xffff7f - * [23:20] f == 1111 - * [19:16] f == 1111 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 7 == 0111 - * [ 3: 0] f == 1111 + /* 0xffff7f + * [23:20] f == 1111 + * [19:16] f == 1111 + * [15:12] f == 1111 + * [11: 8] f == 1111 + * [ 7: 4] 7 == 0111 + * [ 3: 0] f == 1111 * MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled * MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled * MD[63:0] Control 2 == 100 Mhz Buffer Enable @@ -622,12 +622,12 @@ static void set_drtc(void) static void set_pmcr(void) { - /* PMCR -- BIOS sets 0x90 into it. + /* PMCR -- BIOS sets 0x90 into it. * 0x10 is REQUIRED. * we have never used it. So why did this ever work? */ pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90); - + } void sdram_set_registers(void) { @@ -651,7 +651,7 @@ void sdram_set_registers(void) int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -670,7 +670,7 @@ static void spd_set_drb(void) unsigned end_of_memory; unsigned device; unsigned drb_reg; - + end_of_memory = 0; /* in multiples of 8MiB */ device = SMBUS_MEM_DEVICE_START; drb_reg = 0x60; @@ -704,13 +704,13 @@ static void spd_set_drb(void) #else side1_bits += log2((byte2 << 8) | byte); #endif - + /* now I have the ram size in bits as a power of two (less 1) */ /* Make it mulitples of 8MB */ side1_bits -= 25; - + /* side two */ - + /* number of physical banks */ byte = smbus_read_byte(device, 5); if (byte > 1) { @@ -783,8 +783,8 @@ static void spd_set_dramc(void) } dramc = 0x8; if ((byte & 0x12) != 0) { - /* this is a registered part. - * observation: for register parts, BIOS zeros (!) + /* this is a registered part. + * observation: for register parts, BIOS zeros (!) * registers CA-CC. This has an undocumented meaning. */ /* But it does make sense the oppisite of registered @@ -835,7 +835,7 @@ static void spd_enable_refresh(void) } byte &= 0x7f; /* Default refresh rate be conservative */ - refresh_rate = 5; + refresh_rate = 5; /* see if the ram refresh is a supported one */ if (byte < 6) { #if HAVE_STATIC_ARRAY_SUPPORT @@ -856,7 +856,7 @@ static void spd_set_sdramc(void) static void spd_set_rps(void) { /* - * Effects: Uses serial presence detect to set the row size + * Effects: Uses serial presence detect to set the row size * on a given DIMM * FIXME: Check for illegal/unsupported ram configurations and abort */ @@ -881,16 +881,16 @@ static void spd_set_rps(void) page_size = byte & 0xf; /* make it in multiples of 2Kb */ page_size -= 11; - + if (page_size <= 0) continue; - + /* FIXME: do something with page sizes greather than 8KB!! */ page_sizes |= (page_size << index); - + /* side two */ byte = smbus_read_byte(device, 5); if (byte <= 1) continue; - + /* For now only handle the symmetrical case */ page_sizes |= (page_size << (index +2)); } @@ -898,10 +898,10 @@ static void spd_set_rps(void) /* we have just verified that we have to have this code. It appears that * the registered SDRAMs do indeed set the RPS wrong. sheesh. */ - /* at this point, page_sizes holds the RPS for all ram. - * we have verified that for registered DRAM the values are + /* at this point, page_sizes holds the RPS for all ram. + * we have verified that for registered DRAM the values are * 1/2 the size they should be. So we test for registered - * and then double the sizes if needed. + * and then double the sizes if needed. */ dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); @@ -909,9 +909,9 @@ static void spd_set_rps(void) /* registered */ /* BIOS makes weird page size for registered! */ - /* what we have found is you need to set the EVEN banks to - * twice the size. Fortunately there is a very easy way to - * do this. First, read the WORD value of register 0x74. + /* what we have found is you need to set the EVEN banks to + * twice the size. Fortunately there is a very easy way to + * do this. First, read the WORD value of register 0x74. */ page_sizes += 0x1111; } @@ -938,8 +938,8 @@ static void spd_set_pgpol(void) bank_sizes = 0; bank = 0; device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; - bank += 2, device += SMBUS_MEM_DEVICE_INC) { + for(; device <= SMBUS_MEM_DEVICE_END; + bank += 2, device += SMBUS_MEM_DEVICE_INC) { int byte; /* logical banks */ @@ -947,7 +947,7 @@ static void spd_set_pgpol(void) if (byte < 0) continue; if (byte < 4) continue; bank_sizes |= (1 << bank); - + /* side 2 */ /* Number of physical banks */ byte = smbus_read_byte(device, 5); @@ -974,14 +974,14 @@ static void spd_set_nbxcfg(void) /* Say all dimms have no ECC support */ reg = 0xff; index = 0; - + device = SMBUS_MEM_DEVICE_START; for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) { int byte; byte = smbus_read_byte(device, 11); if (byte < 0) continue; -#if !USE_ECC +#if !USE_ECC byte = 0; /* Disable ECC */ #endif /* 0 == None, 1 == Parity, 2 == ECC */ @@ -1015,7 +1015,7 @@ static void spd_set_nbxcfg(void) /* try this. * We should be setting bit 2 in register 76 and we're not * technically we should see if CL=2 for the ram, - * but registered is so screwed up that it's kind of a lost + * but registered is so screwed up that it's kind of a lost * cause. */ byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); @@ -1098,7 +1098,7 @@ static void dimms_read(unsigned long offset) int i; for(i = 0; i < 8; i++) { unsigned long dummy; - unsigned long addr; + unsigned long addr; unsigned long next_base; next_base = dimm_base(i +1); @@ -1108,8 +1108,8 @@ static void dimms_read(unsigned long offset) } addr += offset; #if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr); + print_debug("Reading "); + print_debug_hex32(addr); print_debug("\n"); #endif #if HAVE_POINTER_SUPPORT @@ -1120,8 +1120,8 @@ static void dimms_read(unsigned long offset) #endif #endif #if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr ^ 0xddf8); + print_debug("Reading "); + print_debug_hex32(addr ^ 0xddf8); print_debug("\n"); #endif #if HAVE_POINTER_SUPPORT @@ -1132,9 +1132,9 @@ static void dimms_read(unsigned long offset) #endif #endif #if HAVE_STRING_SUPPORT - print_debug("Read "); - print_debug_hex32(addr); - print_debug_hex32(addr ^ 0xddf8); + print_debug("Read "); + print_debug_hex32(addr); + print_debug_hex32(addr ^ 0xddf8); print_debug("\n"); #endif } @@ -1212,9 +1212,9 @@ void sdram_enable(void) #if HAVE_STRING_SUPPORT print_debug("Ram Enable 2\n"); #endif - + /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ - + sdram_set_command_cbr(); sdram_assert_command(); sdram_assert_command(); @@ -1224,11 +1224,11 @@ void sdram_enable(void) sdram_assert_command(); sdram_assert_command(); sdram_assert_command(); - + #if HAVE_STRING_SUPPORT print_debug("Ram Enable 3\n"); #endif - + /* mode register set */ sdram_set_mode_register(); /* MAx[14:0] lines, @@ -1245,7 +1245,7 @@ void sdram_enable(void) /* normal operation */ sdram_set_command_none(); - + #if HAVE_STRING_SUPPORT print_debug("Ram Enable 5\n"); #endif @@ -1270,7 +1270,7 @@ void sdram_initialize(void) print_debug("Ram3\n"); #endif /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for use while on others + * Some chipsets do the work for use while on others * we need to it by hand. */ sdram_enable(); diff --git a/util/romcc/tests/raminit_test2.c b/util/romcc/tests/raminit_test2.c index 2294b34e786f..d20ae6d4314a 100644 --- a/util/romcc/tests/raminit_test2.c +++ b/util/romcc/tests/raminit_test2.c @@ -136,7 +136,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -355,7 +355,7 @@ int smbus_read_byte(unsigned device, unsigned address) /* CAS latency 2 */ #if (CAS_LATENCY == 2) #define CAS_NB 0x17 - /* + /* * 7 == 0111 * 1 == 0001 */ @@ -367,7 +367,7 @@ int smbus_read_byte(unsigned device, unsigned address) #endif /* CAS latency 3 */ -#if (CAS_LATENCY == 3) +#if (CAS_LATENCY == 3) #define CAS_NB 0x13 /* * 3 == 0011 @@ -381,11 +381,11 @@ int smbus_read_byte(unsigned device, unsigned address) #endif #ifndef CAS_NB -#error "Nothing defined" +#error "Nothing defined" #endif /* Default values for config registers */ - + static void set_nbxcfg(void) { /* NBXCFG 0x50 - 0x53 */ @@ -417,7 +417,7 @@ static void set_nbxcfg(void) * ECC Diagnostic Mode Enable == 0 Not Enabled * MDA present == 0 Not Present * USWC Write Post During During I/O Bridge Access Enable == 1 Enabled - * In Order Queue Depth (IQD) (RO) == ?? + * In Order Queue Depth (IQD) (RO) == ?? */ pcibios_write_config_dword(I440GX_BUS, I440GX_DEVFN, 0x50, 0xff00000c); } @@ -486,7 +486,7 @@ static void set_mbsc(void) * MD[63:0]# Buffer Strength Control 1 == 3x * MECC[7:0] Buffer Strength Control 2 == 3x * MECC[7:0] Buffer Strength Control 1 == 3x - * CSB7# Buffer Strength == 3x + * CSB7# Buffer Strength == 3x * CSA7# Buffer Strength == 3x * CSB6# Buffer Strength == 3x * CSA6# Buffer Strength == 3x @@ -575,13 +575,13 @@ static void set_pgpol(void) static void set_mbfs(void) { /* MBFS - Memory Buffer Frequencey Select Register */ - /* 0xffff7f - * [23:20] f == 1111 - * [19:16] f == 1111 - * [15:12] f == 1111 - * [11: 8] f == 1111 - * [ 7: 4] 7 == 0111 - * [ 3: 0] f == 1111 + /* 0xffff7f + * [23:20] f == 1111 + * [19:16] f == 1111 + * [15:12] f == 1111 + * [11: 8] f == 1111 + * [ 7: 4] 7 == 0111 + * [ 3: 0] f == 1111 * MAA[14:0], WEA#, SRASA#, SCASA# == 100Mhz Buffers Enabled * MAB[14,13,10,12:11,9:0], WEB#, SRASB#, SCASB# == 100Mhz Buffers Enabled * MD[63:0] Control 2 == 100 Mhz Buffer Enable @@ -622,12 +622,12 @@ static void set_drtc(void) static void set_pmcr(void) { - /* PMCR -- BIOS sets 0x90 into it. + /* PMCR -- BIOS sets 0x90 into it. * 0x10 is REQUIRED. * we have never used it. So why did this ever work? */ pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x7a, 0x90); - + } void sdram_set_registers(void) { @@ -651,7 +651,7 @@ void sdram_set_registers(void) int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -670,7 +670,7 @@ static void spd_set_drb(void) unsigned end_of_memory; unsigned device; unsigned drb_reg; - + end_of_memory = 0; /* in multiples of 8MiB */ device = SMBUS_MEM_DEVICE_START; drb_reg = 0x60; @@ -704,13 +704,13 @@ static void spd_set_drb(void) #else side1_bits += log2((byte2 << 8) | byte); #endif - + /* now I have the ram size in bits as a power of two (less 1) */ /* Make it mulitples of 8MB */ side1_bits -= 25; - + /* side two */ - + /* number of physical banks */ byte = smbus_read_byte(device, 5); if (byte > 1) { @@ -783,8 +783,8 @@ static void spd_set_dramc(void) } dramc = 0x8; if ((byte & 0x12) != 0) { - /* this is a registered part. - * observation: for register parts, BIOS zeros (!) + /* this is a registered part. + * observation: for register parts, BIOS zeros (!) * registers CA-CC. This has an undocumented meaning. */ /* But it does make sense the oppisite of registered @@ -835,7 +835,7 @@ static void spd_enable_refresh(void) } byte &= 0x7f; /* Default refresh rate be conservative */ - refresh_rate = 5; + refresh_rate = 5; /* see if the ram refresh is a supported one */ if (byte < 6) { #if HAVE_STATIC_ARRAY_SUPPORT @@ -856,7 +856,7 @@ static void spd_set_sdramc(void) static void spd_set_rps(void) { /* - * Effects: Uses serial presence detect to set the row size + * Effects: Uses serial presence detect to set the row size * on a given DIMM * FIXME: Check for illegal/unsupported ram configurations and abort */ @@ -881,16 +881,16 @@ static void spd_set_rps(void) page_size = byte & 0xf; /* make it in multiples of 2Kb */ page_size -= 11; - + if (page_size <= 0) continue; - + /* FIXME: do something with page sizes greather than 8KB!! */ page_sizes |= (page_size << index); - + /* side two */ byte = smbus_read_byte(device, 5); if (byte <= 1) continue; - + /* For now only handle the symmetrical case */ page_sizes |= (page_size << (index +2)); } @@ -898,10 +898,10 @@ static void spd_set_rps(void) /* we have just verified that we have to have this code. It appears that * the registered SDRAMs do indeed set the RPS wrong. sheesh. */ - /* at this point, page_sizes holds the RPS for all ram. - * we have verified that for registered DRAM the values are + /* at this point, page_sizes holds the RPS for all ram. + * we have verified that for registered DRAM the values are * 1/2 the size they should be. So we test for registered - * and then double the sizes if needed. + * and then double the sizes if needed. */ dramc = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57); @@ -909,9 +909,9 @@ static void spd_set_rps(void) /* registered */ /* BIOS makes weird page size for registered! */ - /* what we have found is you need to set the EVEN banks to - * twice the size. Fortunately there is a very easy way to - * do this. First, read the WORD value of register 0x74. + /* what we have found is you need to set the EVEN banks to + * twice the size. Fortunately there is a very easy way to + * do this. First, read the WORD value of register 0x74. */ page_sizes += 0x1111; } @@ -938,8 +938,8 @@ static void spd_set_pgpol(void) bank_sizes = 0; bank = 0; device = SMBUS_MEM_DEVICE_START; - for(; device <= SMBUS_MEM_DEVICE_END; - bank += 2, device += SMBUS_MEM_DEVICE_INC) { + for(; device <= SMBUS_MEM_DEVICE_END; + bank += 2, device += SMBUS_MEM_DEVICE_INC) { int byte; /* logical banks */ @@ -947,7 +947,7 @@ static void spd_set_pgpol(void) if (byte < 0) continue; if (byte < 4) continue; bank_sizes |= (1 << bank); - + /* side 2 */ /* Number of physical banks */ byte = smbus_read_byte(device, 5); @@ -974,14 +974,14 @@ static void spd_set_nbxcfg(void) /* Say all dimms have no ECC support */ reg = 0xff; index = 0; - + device = SMBUS_MEM_DEVICE_START; for(; device <= SMBUS_MEM_DEVICE_END; index += 2, device += SMBUS_MEM_DEVICE_INC) { int byte; byte = smbus_read_byte(device, 11); if (byte < 0) continue; -#if !USE_ECC +#if !USE_ECC byte = 0; /* Disable ECC */ #endif /* 0 == None, 1 == Parity, 2 == ECC */ @@ -1015,7 +1015,7 @@ static void spd_set_nbxcfg(void) /* try this. * We should be setting bit 2 in register 76 and we're not * technically we should see if CL=2 for the ram, - * but registered is so screwed up that it's kind of a lost + * but registered is so screwed up that it's kind of a lost * cause. */ byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x76); @@ -1098,7 +1098,7 @@ static void dimms_read(unsigned long offset) int i; for(i = 0; i < 8; i++) { unsigned long dummy; - unsigned long addr; + unsigned long addr; unsigned long next_base; next_base = dimm_base(i +1); @@ -1108,8 +1108,8 @@ static void dimms_read(unsigned long offset) } addr += offset; #if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr); + print_debug("Reading "); + print_debug_hex32(addr); print_debug("\n"); #endif #if HAVE_POINTER_SUPPORT @@ -1120,8 +1120,8 @@ static void dimms_read(unsigned long offset) #endif #endif #if HAVE_STRING_SUPPORT - print_debug("Reading "); - print_debug_hex32(addr ^ 0xddf8); + print_debug("Reading "); + print_debug_hex32(addr ^ 0xddf8); print_debug("\n"); #endif #if HAVE_POINTER_SUPPORT @@ -1132,9 +1132,9 @@ static void dimms_read(unsigned long offset) #endif #endif #if HAVE_STRING_SUPPORT - print_debug("Read "); - print_debug_hex32(addr); - print_debug_hex32(addr ^ 0xddf8); + print_debug("Read "); + print_debug_hex32(addr); + print_debug_hex32(addr ^ 0xddf8); print_debug("\n"); #endif } @@ -1212,9 +1212,9 @@ void sdram_enable(void) #if HAVE_STRING_SUPPORT print_debug("Ram Enable 2\n"); #endif - + /* Now we need 8 AUTO REFRESH / CBR cycles to be performed */ - + sdram_set_command_cbr(); sdram_assert_command(); sdram_assert_command(); @@ -1224,11 +1224,11 @@ void sdram_enable(void) sdram_assert_command(); sdram_assert_command(); sdram_assert_command(); - + #if HAVE_STRING_SUPPORT print_debug("Ram Enable 3\n"); #endif - + /* mode register set */ sdram_set_mode_register(); /* MAx[14:0] lines, @@ -1245,7 +1245,7 @@ void sdram_enable(void) /* normal operation */ sdram_set_command_none(); - + #if HAVE_STRING_SUPPORT print_debug("Ram Enable 5\n"); #endif @@ -1270,7 +1270,7 @@ void sdram_initialize(void) print_debug("Ram3\n"); #endif /* Now that everything is setup enable the SDRAM. - * Some chipsets do the work for use while on others + * Some chipsets do the work for use while on others * we need to it by hand. */ sdram_enable(); diff --git a/util/romcc/tests/raminit_test6.c b/util/romcc/tests/raminit_test6.c index a0c3f055be09..e99e355e33d8 100644 --- a/util/romcc/tests/raminit_test6.c +++ b/util/romcc/tests/raminit_test6.c @@ -1,30 +1,30 @@ typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef signed char int8_t; typedef unsigned short uint16_t; typedef signed short int16_t; typedef unsigned int uint32_t; typedef signed int int32_t; - + typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef signed char int_least8_t; typedef unsigned short uint_least16_t; typedef signed short int_least16_t; typedef unsigned int uint_least32_t; typedef signed int int_least32_t; - + typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef signed char int_fast8_t; typedef unsigned int uint_fast16_t; typedef signed int int_fast16_t; typedef unsigned int uint_fast32_t; typedef signed int int_fast32_t; - + typedef int intptr_t; typedef unsigned int uintptr_t; - + typedef long int intmax_t; typedef unsigned long int uintmax_t; - + static inline unsigned long apic_read(unsigned long reg) { return *((volatile unsigned long *)(0xfee00000 +reg)); @@ -37,7 +37,7 @@ static inline void apic_wait_icr_idle(void) { do { } while ( apic_read( 0x300 ) & 0x01000 ); } - + static void outb(unsigned char value, unsigned short port) { __builtin_outb(value, port); @@ -65,7 +65,7 @@ static unsigned char inl(unsigned short port) static inline void outsb(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " + "cld ; rep ; outsb " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -73,7 +73,7 @@ static inline void outsb(uint16_t port, const void *addr, unsigned long count) static inline void outsw(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " + "cld ; rep ; outsw " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -81,7 +81,7 @@ static inline void outsw(uint16_t port, const void *addr, unsigned long count) static inline void outsl(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " + "cld ; rep ; outsl " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -89,7 +89,7 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count) static inline void insb(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insb " + "cld ; rep ; insb " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -97,7 +97,7 @@ static inline void insb(uint16_t port, void *addr, unsigned long count) static inline void insw(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insw " + "cld ; rep ; insw " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -105,7 +105,7 @@ static inline void insw(uint16_t port, void *addr, unsigned long count) static inline void insl(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insl " + "cld ; rep ; insl " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -180,7 +180,7 @@ static uldiv_t uldiv(unsigned long numer, unsigned long denom) } int log2(int value) { - + return __builtin_bsr(value); } typedef unsigned device_t; @@ -237,11 +237,11 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev) } return (0xffffffffU) ; } - - - - - + + + + + static int uart_can_tx_byte(void) { return inb(1016 + 0x05 ) & 0x20; @@ -253,29 +253,29 @@ static void uart_wait_to_tx_byte(void) } static void uart_wait_until_sent(void) { - while(!(inb(1016 + 0x05 ) & 0x40)) + while(!(inb(1016 + 0x05 ) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); outb(data, 1016 + 0x00 ); - + uart_wait_until_sent(); } static void uart_init(void) { - + outb(0x0, 1016 + 0x01 ); - + outb(0x01, 1016 + 0x02 ); - + outb(0x80 | 3 , 1016 + 0x03 ); outb((115200/ 115200 ) & 0xFF, 1016 + 0x00 ); outb(((115200/ 115200 ) >> 8) & 0xFF, 1016 + 0x01 ); outb(3 , 1016 + 0x03 ); } - + static void __console_tx_byte(unsigned char byte) { uart_tx_byte(byte); @@ -380,12 +380,12 @@ static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8 , value) static void print_spew(const char *str) { __console_tx_string(8 , str); } static void console_init(void) { - static const char console_test[] = + static const char console_test[] = "\r\n\r\nLinuxBIOS-" - "1.1.4" - ".0Fallback" + "1.1.4" + ".0Fallback" " " - "Thu Oct 9 20:29:48 MDT 2003" + "Thu Oct 9 20:29:48 MDT 2003" " starting...\r\n"; print_info(console_test); } @@ -400,9 +400,9 @@ static void write_phys(unsigned long addr, unsigned long value) { asm volatile( "movnti %1, (%0)" - : - : "r" (addr), "r" (value) - : + : + : "r" (addr), "r" (value) + : ); } static unsigned long read_phys(unsigned long addr) @@ -414,28 +414,28 @@ static unsigned long read_phys(unsigned long addr) static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; - + print_debug("DRAM fill: "); print_debug_hex32(start); print_debug("-"); print_debug_hex32(stop); print_debug("\r\n"); for(addr = start; addr < stop ; addr += 4) { - + if (!(addr & 0xffff)) { print_debug_hex32(addr); print_debug("\r"); } write_phys(addr, addr); }; - + print_debug_hex32(addr); print_debug("\r\nDRAM filled\r\n"); } static void ram_verify(unsigned long start, unsigned long stop) { unsigned long addr; - + print_debug("DRAM verify: "); print_debug_hex32(start); print_debug_char('-'); @@ -443,31 +443,31 @@ static void ram_verify(unsigned long start, unsigned long stop) print_debug("\r\n"); for(addr = start; addr < stop ; addr += 4) { unsigned long value; - + if (!(addr & 0xffff)) { print_debug_hex32(addr); print_debug("\r"); } value = read_phys(addr); if (value != addr) { - + print_err_hex32(addr); print_err_char(':'); print_err_hex32(value); print_err("\r\n"); } } - + print_debug_hex32(addr); print_debug("\r\nDRAM verified\r\n"); } void ram_check(unsigned long start, unsigned long stop) { int result; - + print_debug("Testing DRAM : "); print_debug_hex32(start); - print_debug("-"); + print_debug("-"); print_debug_hex32(stop); print_debug("\r\n"); ram_fill(start, stop); @@ -476,7 +476,7 @@ void ram_check(unsigned long start, unsigned long stop) } static int enumerate_ht_chain(unsigned link) { - + unsigned next_unitid, last_unitid; int reset_needed = 0; next_unitid = 1; @@ -485,7 +485,7 @@ static int enumerate_ht_chain(unsigned link) uint8_t hdr_type, pos; last_unitid = next_unitid; id = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x00 ); - + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0x0000)) { @@ -531,7 +531,7 @@ static void enable_smbus(void) pci_write_config32(dev, 0x58, 0x0f00 | 1); enable = pci_read_config8(dev, 0x41); pci_write_config8(dev, 0x41, enable | (1 << 7)); - + outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); } static inline void smbus_delay(void) @@ -550,7 +550,7 @@ static int smbus_wait_until_ready(void) break; } if(loops == ((100*1000*10) / 2)) { - outw(inw(0x0f00 + 0xe0 ), + outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); } } while(--loops); @@ -563,7 +563,7 @@ static int smbus_wait_until_done(void) do { unsigned short val; smbus_delay(); - + val = inw(0x0f00 + 0xe0 ); if (((val & 0x8) == 0) | ((val & 0x437) != 0)) { break; @@ -579,29 +579,29 @@ static int smbus_read_byte(unsigned device, unsigned address) if (smbus_wait_until_ready() < 0) { return -2; } - - - + + + outw(inw(0x0f00 + 0xe2 ) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x0f00 + 0xe2 ); - + outw(((device & 0x7f) << 1) | 1, 0x0f00 + 0xe4 ); - + outb(address & 0xFF, 0x0f00 + 0xe8 ); - + outw((inw(0x0f00 + 0xe2 ) & ~7) | (0x2), 0x0f00 + 0xe2 ); - - + + outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); - + outw(0, 0x0f00 + 0xe6 ); - + outw((inw(0x0f00 + 0xe2 ) | (1 << 3)), 0x0f00 + 0xe2 ); - + if (smbus_wait_until_done() < 0) { return -3; } global_status_register = inw(0x0f00 + 0xe0 ); - + byte = inw(0x0f00 + 0xe6 ) & 0xff; if (global_status_register != (1 << 4)) { return -1; @@ -636,31 +636,31 @@ static tsc_t rdtsc(void) { tsc_t res; asm ("rdtsc" - : "=a" (res.lo), "=d"(res.hi) - : - : + : "=a" (res.lo), "=d"(res.hi) + : + : ); return res; } void init_timer(void) { - + apic_write(0x320 , (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - + apic_write(0x3E0 , 0xB ); - + apic_write(0x380 , 0xffffffff); } void udelay(unsigned usecs) { uint32_t start, value, ticks; - + ticks = usecs * 200; start = apic_read(0x390 ); do { value = apic_read(0x390 ); } while((start - value) < ticks); - + } void mdelay(unsigned msecs) { @@ -732,8 +732,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; + for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; + dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { uint32_t id; id = pci_read_config32(dev, 0x00 ); @@ -751,7 +751,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\r\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -769,8 +769,8 @@ static void dump_pci_device(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; + for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; + dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { uint32_t id; id = pci_read_config32(dev, 0x00 ); @@ -791,8 +791,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -817,8 +817,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -842,13 +842,13 @@ static void dump_spd_registers(const struct mem_controller *ctrl) } } } - + static unsigned int cpuid(unsigned int op) { unsigned int ret; unsigned dummy2,dummy3,dummy4; - asm volatile ( - "cpuid" + asm volatile ( + "cpuid" : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) : "a" (op) ); @@ -865,13 +865,13 @@ static int is_cpu_pre_c0(void) static void memreset_setup(void) { if (is_cpu_pre_c0()) { - + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 28); - + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 29); } else { - + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 29); } } @@ -879,15 +879,15 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 28); udelay(90); } } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) { - - uint32_t ret=0x00010101; + + uint32_t ret=0x00010101; static const unsigned int rows_2p[2][2] = { { 0x00050101, 0x00010404 }, { 0x00010404, 0x00050101 } @@ -905,33 +905,33 @@ static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } - + static void coherent_ht_mainboard(unsigned cpus) { } - + void cpu_ldtstop(unsigned cpus) { uint32_t tmp; device_t dev; unsigned cnt; for(cnt=0; cnt<cpus; cnt++) { - + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0x81,0x23); - + pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd4,0x00000701); - + pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd8,0x00000000); - + tmp=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90); pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90, tmp | (1<<24) ); } } - - - - - + + + + + static void setup_resource_map(const unsigned int *register_values, int max) { int i; @@ -952,8 +952,8 @@ static void setup_resource_map(const unsigned int *register_values, int max) static void setup_default_resource_map(void) { static const unsigned int register_values[] = { - - + + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, @@ -962,7 +962,7 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, @@ -971,7 +971,7 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x84 ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x8C ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0x00000048, 0x00000000, @@ -980,7 +980,7 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xAC ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB4 ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xBC ) & 0xFF)) , 0x00000048, 0x00ffff00, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0x000000f0, 0x00000000, @@ -989,17 +989,17 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA8 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB0 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB8 ) & 0xFF)) , 0x000000f0, 0x00fc0003, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC4 ) & 0xFF)) , 0xFE000FC8, 0x01fff000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xCC ) & 0xFF)) , 0xFE000FC8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD4 ) & 0xFF)) , 0xFE000FC8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xDC ) & 0xFF)) , 0xFE000FC8, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC0 ) & 0xFF)) , 0xFE000FCC, 0x00000003, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD0 ) & 0xFF)) , 0xFE000FCC, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE0 ) & 0xFF)) , 0x0000FC88, 0xff000003, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE4 ) & 0xFF)) , 0x0000FC88, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE8 ) & 0xFF)) , 0x0000FC88, 0x00000000, @@ -1012,8 +1012,8 @@ static void setup_default_resource_map(void) static void sdram_set_registers(const struct mem_controller *ctrl) { static const unsigned int register_values[] = { - - + + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, @@ -1022,7 +1022,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, @@ -1031,7 +1031,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x001f01fe, 0x00000000, @@ -1040,7 +1040,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x001f01fe, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0xC01f01ff, 0x00000000, @@ -1049,33 +1049,33 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0xC01f01ff, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0xffff8888, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0xe8088008, 0x02522001 , - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x8c ) & 0xFF)) , 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| + + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xf0000000, + (4 << 25)|(0 << 24)| + (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| + (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| + (2 << 14)|(0 << 13)|(0 << 12)| + (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| (0 << 3) |(0 << 1) |(0 << 0), - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xc180f0f0, (0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)| (0 << 20)|(0 << 19)|(3 << 16)|(0 << 8)|(0 << 0), - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0xfc00ffff, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0xffe0e0e0, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000003e, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xffffff00, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xffff8000, 0x00000f70, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xffffff80, 0x00000002, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0x0000000f, 0x00068300, @@ -1107,14 +1107,14 @@ static int is_dual_channel(const struct mem_controller *ctrl) } static int is_opteron(const struct mem_controller *ctrl) { - + uint32_t nbcap; nbcap = pci_read_config32(ctrl->f3, 0xE8 ); return !!(nbcap & 0x0001 ); } static int is_registered(const struct mem_controller *ctrl) { - + uint32_t dcl; dcl = pci_read_config32(ctrl->f2, 0x90 ); return !(dcl & (1<<18) ); @@ -1125,45 +1125,45 @@ struct dimm_size { }; static struct dimm_size spd_get_dimm_size(unsigned device) { - + struct dimm_size sz; int value, low; sz.side1 = 0; sz.side2 = 0; - - value = spd_read_byte(device, 3); + + value = spd_read_byte(device, 3); if (value < 0) goto out; sz.side1 += value & 0xf; - value = spd_read_byte(device, 4); + value = spd_read_byte(device, 4); if (value < 0) goto out; sz.side1 += value & 0xf; - value = spd_read_byte(device, 17); + value = spd_read_byte(device, 17); if (value < 0) goto out; sz.side1 += log2(value & 0xff); - - value = spd_read_byte(device, 7); + + value = spd_read_byte(device, 7); if (value < 0) goto out; value &= 0xff; value <<= 8; - - low = spd_read_byte(device, 6); + + low = spd_read_byte(device, 6); if (low < 0) goto out; value = value | (low & 0xff); sz.side1 += log2(value); - - value = spd_read_byte(device, 5); + + value = spd_read_byte(device, 5); if (value <= 1) goto out; - + sz.side2 = sz.side1; - value = spd_read_byte(device, 3); + value = spd_read_byte(device, 3); if (value < 0) goto out; - if ((value & 0xf0) == 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - value = spd_read_byte(device, 4); + if ((value & 0xf0) == 0) goto out; + sz.side2 -= (value & 0x0f); + sz.side2 += ((value >> 4) & 0x0f); + value = spd_read_byte(device, 4); if (value < 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); + sz.side2 -= (value & 0x0f); + sz.side2 += ((value >> 4) & 0x0f); out: return sz; } @@ -1176,32 +1176,32 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz } map = pci_read_config32(ctrl->f2, 0x80 ); map &= ~(0xf << (index + 4)); - - + + base0 = base1 = 0; - + if (sz.side1 >= (25 +3)) { map |= (sz.side1 - (25 + 3)) << (index *4); base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1; } - + if (sz.side2 >= (25 + 3)) { base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1; } - + if (is_dual_channel(ctrl)) { base0 = (base0 << 1) | (base0 & 1); base1 = (base1 << 1) | (base1 & 1); } - + base0 &= ~0x001ffffe; base1 &= ~0x001ffffe; - + pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), base0); pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), base1); pci_write_config32(ctrl->f2, 0x80 , map); - - + + if (base0) { dch = pci_read_config32(ctrl->f2, 0x94 ); dch |= (1 << 26) << index; @@ -1211,7 +1211,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz static void spd_set_ram_size(const struct mem_controller *ctrl) { int i; - + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { struct dimm_size sz; sz = spd_get_dimm_size(ctrl->channel0[i]); @@ -1221,7 +1221,7 @@ static void spd_set_ram_size(const struct mem_controller *ctrl) static void route_dram_accesses(const struct mem_controller *ctrl, unsigned long base_k, unsigned long limit_k) { - + unsigned node_id; unsigned limit; unsigned base; @@ -1246,25 +1246,25 @@ static void route_dram_accesses(const struct mem_controller *ctrl, } static void set_top_mem(unsigned tom_k) { - + if (!tom_k) { set_bios_reset(); print_debug("No memory - reset"); - + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0x04 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0x41, 0xf1); - + outb(0x0e, 0x0cf9); } - + print_debug("RAM: 0x"); print_debug_hex32(tom_k); print_debug(" KB\r\n"); - + msr_t msr; msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(0xC001001D , msr); - + if (tom_k >= 0x003f0000) { tom_k = 0x3f0000; } @@ -1274,15 +1274,15 @@ static void set_top_mem(unsigned tom_k) } static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) { - - static const uint32_t csbase_low[] = { + + static const uint32_t csbase_low[] = { (1 << (13 - 4)), (1 << (14 - 4)), - (1 << (14 - 4)), + (1 << (14 - 4)), (1 << (15 - 4)), (1 << (15 - 4)), (1 << (16 - 4)), - (1 << (16 - 4)), + (1 << (16 - 4)), }; uint32_t csbase_inc; int chip_selects, index; @@ -1290,16 +1290,16 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) int dual_channel; unsigned common_size; uint32_t csbase, csmask; - + chip_selects = 0; common_size = 0; for(index = 0; index < 8; index++) { unsigned size; uint32_t value; - + value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - + + if (!(value & 1)) { continue; } @@ -1308,36 +1308,36 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) if (common_size == 0) { common_size = size; } - + if (common_size != size) { return 0; } } - + bits = log2(chip_selects); if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { return 0; - + } - + if ((bits == 3) && (common_size == (1 << (32 - 3)))) { print_debug("8 4GB chip selects cannot be interleaved\r\n"); return 0; } - + if (is_dual_channel(ctrl)) { csbase_inc = csbase_low[log2(common_size) - 1] << 1; } else { csbase_inc = csbase_low[log2(common_size)]; } - + csbase = 0 | 1; csmask = (((common_size << bits) - 1) << 21); csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc); for(index = 0; index < 8; index++) { uint32_t value; value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - + if (!(value & 1)) { continue; } @@ -1345,19 +1345,19 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) pci_write_config32(ctrl->f2, 0x60 + (index << 2), csmask); csbase += csbase_inc; } - + print_debug("Interleaved\r\n"); - + return common_size << (15 + bits); } static unsigned long order_chip_selects(const struct mem_controller *ctrl) { unsigned long tom; - - + + tom = 0; for(;;) { - + unsigned index, canidate; uint32_t csbase, csmask; unsigned size; @@ -1366,46 +1366,46 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) for(index = 0; index < 8; index++) { uint32_t value; value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - + if (!(value & 1)) { continue; } - - + + if (value <= csbase) { continue; } - - + + if (tom & (1 << (index + 24))) { continue; } - + csbase = value; canidate = index; } - + if (csbase == 0) { break; } - + size = csbase >> 21; - + tom |= (1 << (canidate + 24)); - + csbase = (tom << 21) | 1; - + tom += size; - + csmask = ((size -1) << 21); - csmask |= 0xfe00; - + csmask |= 0xfe00; + pci_write_config32(ctrl->f2, 0x40 + (canidate << 2), csbase); - + pci_write_config32(ctrl->f2, 0x60 + (canidate << 2), csmask); - + } - + return (tom & ~0xff000000) << 15; } static void order_dimms(const struct mem_controller *ctrl) @@ -1416,14 +1416,14 @@ static void order_dimms(const struct mem_controller *ctrl) if (!tom_k) { tom_k = order_chip_selects(ctrl); } - + base_k = 0; for(node_id = 0; node_id < ctrl->node_id; node_id++) { uint32_t limit, base; unsigned index; index = node_id << 3; base = pci_read_config32(ctrl->f1, 0x40 + index); - + if ((base & 3) == 3) { limit = pci_read_config32(ctrl->f1, 0x44 + index); base_k = ((limit + 0x00010000) & 0xffff0000) >> 2; @@ -1435,8 +1435,8 @@ static void order_dimms(const struct mem_controller *ctrl) } static void disable_dimm(const struct mem_controller *ctrl, unsigned index) { - print_debug("disabling dimm"); - print_debug_hex8(index); + print_debug("disabling dimm"); + print_debug_hex8(index); print_debug("\r\n"); pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), 0); pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), 0); @@ -1456,11 +1456,11 @@ static void spd_handle_unbuffered_dimms(const struct mem_controller *ctrl) disable_dimm(ctrl, i); continue; } - + if (value & (1 << 1)) { registered = 1; - } - + } + else { unbuffered = 1; } @@ -1482,29 +1482,29 @@ static void spd_enable_2channels(const struct mem_controller *ctrl) { int i; uint32_t nbcap; - - + + static const unsigned addresses[] = { - 2, - 3, - 4, - 5, - 6, - 7, - 9, - 11, - 13, - 17, - 18, - 21, - 23, - 26, - 27, - 28, - 29, - 30, - 41, - 42, + 2, + 3, + 4, + 5, + 6, + 7, + 9, + 11, + 13, + 17, + 18, + 21, + 23, + 26, + 27, + 28, + 29, + 30, + 41, + 42, }; nbcap = pci_read_config32(ctrl->f3, 0xE8 ); if (!(nbcap & 0x0001 )) { @@ -1543,7 +1543,7 @@ static void spd_enable_2channels(const struct mem_controller *ctrl) } struct mem_param { uint8_t cycle_time; - uint8_t divisor; + uint8_t divisor; uint8_t tRC; uint8_t tRFC; uint32_t dch_memclk; @@ -1616,35 +1616,35 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) } static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) { - + const struct mem_param *param; unsigned min_cycle_time, min_latency; int i; uint32_t value; static const int latency_indicies[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { - [0 ] = 0x50, - [1 ] = 0x60, - [2 ] = 0x75, - [3 ] = 0xa0, + [0 ] = 0x50, + [1 ] = 0x60, + [2 ] = 0x75, + [3 ] = 0xa0, }; value = pci_read_config32(ctrl->f3, 0xE8 ); min_cycle_time = min_cycle_times[(value >> 5 ) & 3 ]; min_latency = 2; - + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int new_cycle_time, new_latency; int index; int latencies; int latency; - + new_cycle_time = 0xa0; new_latency = 5; latencies = spd_read_byte(ctrl->channel0[i], 18); if (latencies <= 0) continue; - + latency = log2(latencies) -2; - + for(index = 0; index < 3; index++, latency++) { int value; if ((latency < 2) || (latency > 4) || @@ -1655,7 +1655,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (value < 0) { continue; } - + if ((value >= min_cycle_time) && (value < new_cycle_time)) { new_cycle_time = value; new_latency = latency; @@ -1664,17 +1664,17 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (new_latency > 4){ continue; } - + if (new_cycle_time > min_cycle_time) { min_cycle_time = new_cycle_time; } - + if (new_latency > min_latency) { min_latency = new_latency; } } - - + + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int latencies; int latency; @@ -1685,9 +1685,9 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (latencies <= 0) { goto dimm_err; } - + latency = log2(latencies) -2; - + for(index = 0; index < 3; index++, latency++) { if (!(latencies & (1 << latency))) { continue; @@ -1695,36 +1695,36 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (latency == min_latency) break; } - + if ((latency != min_latency) || (index >= 3)) { goto dimm_err; } - - + + value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - - + + if (value <= min_cycle_time) { continue; } - + dimm_err: disable_dimm(ctrl, i); } - + param = get_mem_param(min_cycle_time); - + value = pci_read_config32(ctrl->f2, 0x94 ); value &= ~(0x7 << 20 ); value |= param->dch_memclk; pci_write_config32(ctrl->f2, 0x94 , value); static const unsigned latencies[] = { 1 , 5 , 2 }; - + value = pci_read_config32(ctrl->f2, 0x88 ); value &= ~(0x7 << 0 ); value |= latencies[min_latency - 2] << 0 ; pci_write_config32(ctrl->f2, 0x88 , value); - + return param; } static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i) @@ -1969,7 +1969,7 @@ static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param * { uint32_t dth; unsigned clocks; - clocks = 1; + clocks = 1; dth = pci_read_config32(ctrl->f2, 0x8c ); dth &= ~(0x1 << 0 ); dth |= ((clocks - 1 ) << 0 ); @@ -1988,11 +1988,11 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * if (is_opteron(ctrl)) { if (latency == 1 ) { if (divisor == ((6 << 0) + 0)) { - + clocks = 3; } else if (divisor > ((6 << 0)+0)) { - + clocks = 2; } } @@ -2001,11 +2001,11 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * } else if (latency == 2 ) { if (divisor == ((6 << 0)+0)) { - + clocks = 4; } else if (divisor > ((6 << 0)+0)) { - + clocks = 3; } } @@ -2037,7 +2037,7 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * if ((clocks < 1 ) || (clocks > 6 )) { die("Unknown Trwt"); } - + dth = pci_read_config32(ctrl->f2, 0x8c ); dth &= ~(0x7 << 4 ); dth |= ((clocks - 1 ) << 4 ); @@ -2046,7 +2046,7 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * } static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param) { - + uint32_t dth; unsigned clocks; if (is_registered(ctrl)) { @@ -2070,19 +2070,19 @@ static void set_read_preamble(const struct mem_controller *ctrl, const struct me rdpreamble = 0; if (is_registered(ctrl)) { if (divisor == ((10 << 1)+0)) { - + rdpreamble = ((9 << 1)+ 0); } else if (divisor == ((7 << 1)+1)) { - + rdpreamble = ((8 << 1)+0); } else if (divisor == ((6 << 1)+0)) { - + rdpreamble = ((7 << 1)+1); } else if (divisor == ((5 << 1)+0)) { - + rdpreamble = ((7 << 1)+0); } } @@ -2096,42 +2096,42 @@ static void set_read_preamble(const struct mem_controller *ctrl, const struct me } } if (divisor == ((10 << 1)+0)) { - + if (slots <= 2) { - + rdpreamble = ((9 << 1)+0); } else { - + rdpreamble = ((14 << 1)+0); } } else if (divisor == ((7 << 1)+1)) { - + if (slots <= 2) { - + rdpreamble = ((7 << 1)+0); } else { - + rdpreamble = ((11 << 1)+0); } } else if (divisor == ((6 << 1)+0)) { - + if (slots <= 2) { - + rdpreamble = ((7 << 1)+0); } else { - + rdpreamble = ((9 << 1)+0); } } else if (divisor == ((5 << 1)+0)) { - + if (slots <= 2) { - + rdpreamble = ((5 << 1)+0); } else { - + rdpreamble = ((7 << 1)+0); } } @@ -2154,11 +2154,11 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc async_lat = 0; if (is_registered(ctrl)) { if (dimms == 4) { - + async_lat = 9; - } + } else { - + async_lat = 8; } } @@ -2167,11 +2167,11 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc die("Too many unbuffered dimms"); } else if (dimms == 3) { - + async_lat = 7; } else { - + async_lat = 6; } } @@ -2181,7 +2181,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { uint32_t dch; - + dch = pci_read_config32(ctrl->f2, 0x94 ); dch &= ~(0x7 << 16 ); dch |= 3 << 16 ; @@ -2193,39 +2193,39 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, const struct int dimms; int i; int rc; - + init_Tref(ctrl, param); for(i = 0; (i < 4) && ctrl->channel0[i]; i++) { int rc; - + if (update_dimm_Trc (ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trfc(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trcd(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trrd(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Tras(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trp (ctrl, param, i) < 0) goto dimm_err; - + if (update_dimm_Tref(ctrl, param, i) < 0) goto dimm_err; - + if (update_dimm_x4 (ctrl, param, i) < 0) goto dimm_err; if (update_dimm_ecc(ctrl, param, i) < 0) goto dimm_err; continue; dimm_err: disable_dimm(ctrl, i); - + } - + set_Twr(ctrl, param); - + set_Twtr(ctrl, param); set_Trwt(ctrl, param); set_Twcl(ctrl, param); - + set_read_preamble(ctrl, param); set_max_async_latency(ctrl, param); set_idle_cycle_limit(ctrl, param); } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { const struct mem_param *param; spd_enable_2channels(ctrl); @@ -2238,18 +2238,18 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; - + for(i = 0; i < controllers; i++) { uint32_t dch; dch = pci_read_config32(ctrl[i].f2, 0x94 ); dch |= (1 << 25) ; pci_write_config32(ctrl[i].f2, 0x94 , dch); } - + memreset(controllers, ctrl); for(i = 0; i < controllers; i++) { uint32_t dcl; - + dcl = pci_read_config32(ctrl[i].f2, 0x90 ); if (dcl & (1<<17) ) { uint32_t mnc; @@ -2289,7 +2289,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) if (dcl & (1<<17) ) { print_debug("Clearing memory: "); if (!is_cpu_pre_c0()) { - + dcl &= ~((1<<11) | (1<<10) ); pci_write_config32(ctrl[i].f2, 0x90 , dcl); do { @@ -2299,10 +2299,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) uint32_t base, last_scrub_k, scrub_k; uint32_t cnt,zstart,zend; msr_t msr,msr_201; - + pci_write_config32(ctrl[i].f3, 0x58 , (0 << 16) | (0 << 8) | (0 << 0)); - + msr_201 = rdmsr(0x201); zstart = pci_read_config32(ctrl[0].f1, 0x40 + (i*8)); zend = pci_read_config32(ctrl[0].f1, 0x44 + (i*8)); @@ -2313,50 +2313,50 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("-"); print_debug_hex32(zend); print_debug("\r\n"); - - + + msr = rdmsr(0x2ff ); msr.lo &= ~(1<<10); wrmsr(0x2ff , msr); - + msr = rdmsr(0xc0010015); msr.lo |= (1<<17); wrmsr(0xc0010015,msr); for(;zstart<zend;zstart+=4) { - + if(zstart == 0x0fc) continue; - - + + __asm__ volatile( "movl %%cr0, %0\n\t" "orl $0x40000000, %0\n\t" "movl %0, %%cr0\n\t" :"=r" (cnt) ); - - + + msr.lo = 1 + ((zstart&0x0ff)<<24); msr.hi = (zstart&0x0ff00)>>8; wrmsr(0x200,msr); - + msr.hi = 0x000000ff; msr.lo = 0xfc000800; wrmsr(0x201,msr); - + __asm__ volatile( "movl %%cr0, %0\n\t" "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) + "movl %0, %%cr0\n\t" + :"=r" (cnt) ); - + msr.lo = (zstart&0xff) << 24; msr.hi = (zstart&0xff00) >> 8; wrmsr(0xc0000100,msr); - print_debug_char((zstart > 0x0ff)?'+':'-'); - - + print_debug_char((zstart > 0x0ff)?'+':'-'); + + __asm__ volatile( "1: \n\t" "movl %0, %%fs:(%1)\n\t" @@ -2365,67 +2365,67 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) "jnz 1b\n\t" : : "a" (0), "D" (0), "c" (0x01000000) - ); + ); } - - + + __asm__ volatile( "movl %%cr0, %0\n\t" "orl $0x40000000, %0\n\t" "movl %0, %%cr0\n\t" - :"=r" (cnt) + :"=r" (cnt) ); - - + + msr = rdmsr(0x2ff ); msr.lo |= 0x0400; wrmsr(0x2ff , msr); - + msr.lo = 6; msr.hi = 0; wrmsr(0x200,msr); wrmsr(0x201,msr_201); - + msr.lo = 0; msr.hi = 0; wrmsr(0xc0000100,msr); - + __asm__ volatile( "movl %%cr0, %0\n\t" "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) + "movl %0, %%cr0\n\t" + :"=r" (cnt) ); - - + + msr = rdmsr(0xc0010015); msr.lo &= ~(1<<17); wrmsr(0xc0010015,msr); - + base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3)); base &= 0xffff0000; - + pci_write_config32(ctrl[i].f3, 0x5C , base << 8); pci_write_config32(ctrl[i].f3, 0x60 , base >> 24); - - pci_write_config32(ctrl[i].f3, 0x58 , + + pci_write_config32(ctrl[i].f3, 0x58 , (22 << 16) | (22 << 8) | (22 << 0)); print_debug("done\r\n"); } } } - - - - - + + + + + typedef uint8_t u8; typedef uint32_t u32; typedef int8_t bool; static void disable_probes(void) { - - + + u32 val; print_debug("Disabling read/write/fill probes for UP... "); val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68); @@ -2433,8 +2433,8 @@ static void disable_probes(void) pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68, val); print_debug("done.\r\n"); } - -static void wait_ap_stop(u8 node) + +static void wait_ap_stop(u8 node) { unsigned long reg; unsigned long i; @@ -2444,7 +2444,7 @@ static void wait_ap_stop(u8 node) if((regx & (1<<4))==1) break; } reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x6c); - reg &= ~(1<<4); + reg &= ~(1<<4); pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, reg); } static void notify_bsp_ap_is_stopped(void) @@ -2453,31 +2453,31 @@ static void notify_bsp_ap_is_stopped(void) unsigned long apic_id; apic_id = *((volatile unsigned long *)(0xfee00000 + 0x020 )); apic_id >>= 24; - + if(apic_id != 0) { - + reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C); reg |= 1<<4; pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C, reg); } - + } - + static void enable_routing(u8 node) { u32 val; - - + + print_debug("Enabling routing table for node "); print_debug_hex32(node); val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c); val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)); pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, val); - + if(node!=0) { wait_ap_stop(node); } - + print_debug(" done.\r\n"); } static void rename_temp_node(u8 node) @@ -2486,21 +2486,21 @@ static void rename_temp_node(u8 node) print_debug("Renaming current temp node to "); print_debug_hex32(node); val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60); - val &= (~7); - val |= node; + val &= (~7); + val |= node; pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60, val); print_debug(" done.\r\n"); } static bool check_connection(u8 src, u8 dest, u8 link) { - + u32 val; - - + + val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ src ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x98+link); if ( (val&0x17) != 0x03) return 0; - + val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ dest ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0); if(val != 0x11001022) return 0; @@ -2513,37 +2513,37 @@ static void optimize_connection(u8 node1, u8 link1, u8 node2, u8 link2) uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask; uint8_t width_cap1, width_cap2, width_cap, width, ln_width1, ln_width2; uint8_t freq; - - + + freq_cap1 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x0a ); freq_cap2 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x0a ); - - + + freq = log2(freq_cap1 & freq_cap2 & 0xff); - + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x09 , freq); pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x09 , freq); - + width_cap1 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 ); width_cap2 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 ); - + ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - + ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - - + + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 + 1, width); - + width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 + 1, width); } @@ -2571,8 +2571,8 @@ static void setup_remote_row(u8 source, u8 dest, u8 cpus) } static void setup_remote_node(u8 node, u8 cpus) { - static const uint8_t pci_reg[] = { - 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, + static const uint8_t pci_reg[] = { + 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, @@ -2585,7 +2585,7 @@ static void setup_remote_node(u8 node, u8 cpus) print_debug("setup_remote_node\r\n"); for(row=0; row<cpus; row++) setup_remote_row(node, row, cpus); - + for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { uint32_t value; uint8_t reg; @@ -2606,24 +2606,24 @@ static u8 setup_smp(void) u8 cpus=2; print_debug("Enabling SMP settings\r\n"); setup_row(0,0,cpus); - + setup_temp_row(0,1,cpus); - + if (!check_connection(0, 7, 0x20 )) { print_debug("No connection to Node 1.\r\n"); - fill_row( 0 ,7,0x00010101 ) ; - setup_uniprocessor(); + fill_row( 0 ,7,0x00010101 ) ; + setup_uniprocessor(); return 1; } - + optimize_connection(0, 0x20 , 7, 0x20 ); - setup_node(0, cpus); - setup_remote_node(1, cpus); - rename_temp_node(1); - enable_routing(1); - - fill_row( 0 ,7,0x00010101 ) ; - + setup_node(0, cpus); + setup_remote_node(1, cpus); + rename_temp_node(1); + enable_routing(1); + + fill_row( 0 ,7,0x00010101 ) ; + print_debug_hex32(cpus); print_debug(" nodes initialized.\r\n"); return cpus; @@ -2636,29 +2636,29 @@ static unsigned detect_mp_capabilities(unsigned cpus) print_debug_hex32(cpus); print_debug("\r\n"); if (cpus>2) - mask=0x06; + mask=0x06; else - mask=0x02; + mask=0x02; for (node=0; node<cpus; node++) { if ((pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0xe8) & mask)!=mask) mp_cap= (0) ; } if (mp_cap) return cpus; - + print_debug("One of the CPUs is not MP capable. Going back to UP\r\n"); for (node=cpus; node>0; node--) for (row=cpus; row>0; row--) fill_row(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node-1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , row-1, 0x00010101 ); - + return setup_uniprocessor(); } static void coherent_ht_finalize(unsigned cpus) { int node; bool rev_a0; - - + + print_debug("coherent_ht_finalize\r\n"); rev_a0= is_cpu_rev_a0(); for (node=0; node<cpus; node++) { @@ -2686,36 +2686,36 @@ static int setup_coherent_ht_domain(void) cpus=setup_smp(); cpus=detect_mp_capabilities(cpus); coherent_ht_finalize(cpus); - + coherent_ht_mainboard(cpus); return reset_needed; } void sdram_no_memory(void) { print_err("No memory!!\r\n"); - while(1) { - hlt(); + while(1) { + hlt(); } } - + void sdram_initialize(int controllers, const struct mem_controller *ctrl) { int i; - + for(i = 0; i < controllers; i++) { print_debug("Ram1."); print_debug_hex8(i); print_debug("\r\n"); sdram_set_registers(ctrl + i); } - + for(i = 0; i < controllers; i++) { print_debug("Ram2."); print_debug_hex8(i); print_debug("\r\n"); sdram_set_spd_registers(ctrl + i); } - + print_debug("Ram3\r\n"); sdram_enable(controllers, ctrl); print_debug("Ram4\r\n"); @@ -2733,17 +2733,17 @@ static void stop_this_cpu(void) { unsigned apicid; apicid = apic_read(0x020 ) >> 24; - + apic_write(0x310 , (( apicid )<<24) ); apic_write(0x300 , 0x08000 | 0x04000 | 0x00500 ); - + apic_wait_icr_idle(); - + apic_write(0x310 , (( apicid )<<24) ); apic_write(0x300 , 0x08000 | 0x00500 ); - + apic_wait_icr_idle(); - + for(;;) { hlt(); } @@ -2756,7 +2756,7 @@ static void pc87360_enable_serial(void) } static void main(void) { - + static const struct mem_controller cpu[] = { { .node_id = 0, @@ -2792,9 +2792,9 @@ static void main(void) setup_coherent_ht_domain(); enumerate_ht_chain(0); distinguish_cpu_resets(0); - + enable_smbus(); memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - + } diff --git a/util/romcc/tests/raminit_test7.c b/util/romcc/tests/raminit_test7.c index be62d3057350..184e912fffff 100644 --- a/util/romcc/tests/raminit_test7.c +++ b/util/romcc/tests/raminit_test7.c @@ -1,30 +1,30 @@ typedef unsigned char uint8_t; -typedef signed char int8_t; +typedef signed char int8_t; typedef unsigned short uint16_t; typedef signed short int16_t; typedef unsigned int uint32_t; typedef signed int int32_t; - + typedef unsigned char uint_least8_t; -typedef signed char int_least8_t; +typedef signed char int_least8_t; typedef unsigned short uint_least16_t; typedef signed short int_least16_t; typedef unsigned int uint_least32_t; typedef signed int int_least32_t; - + typedef unsigned char uint_fast8_t; -typedef signed char int_fast8_t; +typedef signed char int_fast8_t; typedef unsigned int uint_fast16_t; typedef signed int int_fast16_t; typedef unsigned int uint_fast32_t; typedef signed int int_fast32_t; - + typedef int intptr_t; typedef unsigned int uintptr_t; - + typedef long int intmax_t; typedef unsigned long int uintmax_t; - + static inline unsigned long apic_read(unsigned long reg) { return *((volatile unsigned long *)(0xfee00000 +reg)); @@ -37,7 +37,7 @@ static inline void apic_wait_icr_idle(void) { do { } while ( apic_read( 0x300 ) & 0x01000 ); } - + static void outb(unsigned char value, unsigned short port) { __builtin_outb(value, port); @@ -65,7 +65,7 @@ static unsigned char inl(unsigned short port) static inline void outsb(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsb " + "cld ; rep ; outsb " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -73,7 +73,7 @@ static inline void outsb(uint16_t port, const void *addr, unsigned long count) static inline void outsw(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsw " + "cld ; rep ; outsw " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -81,7 +81,7 @@ static inline void outsw(uint16_t port, const void *addr, unsigned long count) static inline void outsl(uint16_t port, const void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; outsl " + "cld ; rep ; outsl " : "=S" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -89,7 +89,7 @@ static inline void outsl(uint16_t port, const void *addr, unsigned long count) static inline void insb(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insb " + "cld ; rep ; insb " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -97,7 +97,7 @@ static inline void insb(uint16_t port, void *addr, unsigned long count) static inline void insw(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insw " + "cld ; rep ; insw " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -105,7 +105,7 @@ static inline void insw(uint16_t port, void *addr, unsigned long count) static inline void insl(uint16_t port, void *addr, unsigned long count) { __asm__ __volatile__ ( - "cld ; rep ; insl " + "cld ; rep ; insl " : "=D" (addr), "=c" (count) : "d"(port), "0"(addr), "1" (count) ); @@ -180,7 +180,7 @@ static uldiv_t uldiv(unsigned long numer, unsigned long denom) } int log2(int value) { - + return __builtin_bsr(value); } typedef unsigned device_t; @@ -237,11 +237,11 @@ static device_t pci_locate_device(unsigned pci_id, device_t dev) } return (0xffffffffU) ; } - - - - - + + + + + static int uart_can_tx_byte(void) { return inb(1016 + 0x05 ) & 0x20; @@ -253,29 +253,29 @@ static void uart_wait_to_tx_byte(void) } static void uart_wait_until_sent(void) { - while(!(inb(1016 + 0x05 ) & 0x40)) + while(!(inb(1016 + 0x05 ) & 0x40)) ; } static void uart_tx_byte(unsigned char data) { uart_wait_to_tx_byte(); outb(data, 1016 + 0x00 ); - + uart_wait_until_sent(); } static void uart_init(void) { - + outb(0x0, 1016 + 0x01 ); - + outb(0x01, 1016 + 0x02 ); - + outb(0x80 | 3 , 1016 + 0x03 ); outb((115200/ 115200 ) & 0xFF, 1016 + 0x00 ); outb(((115200/ 115200 ) >> 8) & 0xFF, 1016 + 0x01 ); outb(3 , 1016 + 0x03 ); } - + static void __console_tx_byte(unsigned char byte) { uart_tx_byte(byte); @@ -385,12 +385,12 @@ static void print_spew_hex32(unsigned int value) { __console_tx_hex32(8 , value) static void print_spew(const char *str) { __console_tx_string(8 , str); } static void console_init(void) { - static const char console_test[] = + static const char console_test[] = "\r\n\r\nLinuxBIOS-" - "1.1.4" - ".0Fallback" + "1.1.4" + ".0Fallback" " " - "Thu Oct 9 20:29:48 MDT 2003" + "Thu Oct 9 20:29:48 MDT 2003" " starting...\r\n"; print_info(console_test); } @@ -405,9 +405,9 @@ static void write_phys(unsigned long addr, unsigned long value) { asm volatile( "movnti %1, (%0)" - : - : "r" (addr), "r" (value) - : + : + : "r" (addr), "r" (value) + : ); } static unsigned long read_phys(unsigned long addr) @@ -419,28 +419,28 @@ static unsigned long read_phys(unsigned long addr) static void ram_fill(unsigned long start, unsigned long stop) { unsigned long addr; - + print_debug("DRAM fill: "); print_debug_hex32(start); print_debug("-"); print_debug_hex32(stop); print_debug("\r\n"); for(addr = start; addr < stop ; addr += 4) { - + if (!(addr & 0xffff)) { print_debug_hex32(addr); print_debug("\r"); } write_phys(addr, addr); }; - + print_debug_hex32(addr); print_debug("\r\nDRAM filled\r\n"); } static void ram_verify(unsigned long start, unsigned long stop) { unsigned long addr; - + print_debug("DRAM verify: "); print_debug_hex32(start); print_debug_char('-'); @@ -448,31 +448,31 @@ static void ram_verify(unsigned long start, unsigned long stop) print_debug("\r\n"); for(addr = start; addr < stop ; addr += 4) { unsigned long value; - + if (!(addr & 0xffff)) { print_debug_hex32(addr); print_debug("\r"); } value = read_phys(addr); if (value != addr) { - + print_err_hex32(addr); print_err_char(':'); print_err_hex32(value); print_err("\r\n"); } } - + print_debug_hex32(addr); print_debug("\r\nDRAM verified\r\n"); } void ram_check(unsigned long start, unsigned long stop) { int result; - + print_debug("Testing DRAM : "); print_debug_hex32(start); - print_debug("-"); + print_debug("-"); print_debug_hex32(stop); print_debug("\r\n"); ram_fill(start, stop); @@ -481,7 +481,7 @@ void ram_check(unsigned long start, unsigned long stop) } static int enumerate_ht_chain(unsigned link) { - + unsigned next_unitid, last_unitid; int reset_needed = 0; next_unitid = 1; @@ -490,7 +490,7 @@ static int enumerate_ht_chain(unsigned link) uint8_t hdr_type, pos; last_unitid = next_unitid; id = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x00 ); - + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0xffff) || (((id >> 16) & 0xffff) == 0x0000)) { @@ -536,7 +536,7 @@ static void enable_smbus(void) pci_write_config32(dev, 0x58, 0x0f00 | 1); enable = pci_read_config8(dev, 0x41); pci_write_config8(dev, 0x41, enable | (1 << 7)); - + outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); } static inline void smbus_delay(void) @@ -555,7 +555,7 @@ static int smbus_wait_until_ready(void) break; } if(loops == ((100*1000*10) / 2)) { - outw(inw(0x0f00 + 0xe0 ), + outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); } } while(--loops); @@ -568,7 +568,7 @@ static int smbus_wait_until_done(void) do { unsigned short val; smbus_delay(); - + val = inw(0x0f00 + 0xe0 ); if (((val & 0x8) == 0) | ((val & 0x437) != 0)) { break; @@ -584,29 +584,29 @@ static int smbus_read_byte(unsigned device, unsigned address) if (smbus_wait_until_ready() < 0) { return -2; } - - - + + + outw(inw(0x0f00 + 0xe2 ) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)), 0x0f00 + 0xe2 ); - + outw(((device & 0x7f) << 1) | 1, 0x0f00 + 0xe4 ); - + outb(address & 0xFF, 0x0f00 + 0xe8 ); - + outw((inw(0x0f00 + 0xe2 ) & ~7) | (0x2), 0x0f00 + 0xe2 ); - - + + outw(inw(0x0f00 + 0xe0 ), 0x0f00 + 0xe0 ); - + outw(0, 0x0f00 + 0xe6 ); - + outw((inw(0x0f00 + 0xe2 ) | (1 << 3)), 0x0f00 + 0xe2 ); - + if (smbus_wait_until_done() < 0) { return -3; } global_status_register = inw(0x0f00 + 0xe0 ); - + byte = inw(0x0f00 + 0xe6 ) & 0xff; if (global_status_register != (1 << 4)) { return -1; @@ -641,31 +641,31 @@ static tsc_t rdtsc(void) { tsc_t res; asm ("rdtsc" - : "=a" (res.lo), "=d"(res.hi) - : - : + : "=a" (res.lo), "=d"(res.hi) + : + : ); return res; } void init_timer(void) { - + apic_write(0x320 , (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); - + apic_write(0x3E0 , 0xB ); - + apic_write(0x380 , 0xffffffff); } void udelay(unsigned usecs) { uint32_t start, value, ticks; - + ticks = usecs * 200; start = apic_read(0x390 ); do { value = apic_read(0x390 ); } while((start - value) < ticks); - + } void mdelay(unsigned msecs) { @@ -737,8 +737,8 @@ static void print_debug_pci_dev(unsigned dev) static void print_pci_devices(void) { device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; + for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; + dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { uint32_t id; id = pci_read_config32(dev, 0x00 ); @@ -756,7 +756,7 @@ static void dump_pci_device(unsigned dev) int i; print_debug_pci_dev(dev); print_debug("\r\n"); - + for(i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { @@ -774,8 +774,8 @@ static void dump_pci_device(unsigned dev) static void dump_pci_devices(void) { device_t dev; - for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; - dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; + for(dev = ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ; + dev <= ( ((( 0 ) & 0xFF) << 16) | ((( 0x1f ) & 0x1f) << 11) | ((( 0x7 ) & 0x7) << 8)) ; dev += ( ((( 0 ) & 0xFF) << 16) | ((( 0 ) & 0x1f) << 11) | ((( 1 ) & 0x7) << 8)) ) { uint32_t id; id = pci_read_config32(dev, 0x00 ); @@ -796,8 +796,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel0[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".0: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -822,8 +822,8 @@ static void dump_spd_registers(const struct mem_controller *ctrl) device = ctrl->channel1[i]; if (device) { int j; - print_debug("dimm: "); - print_debug_hex8(i); + print_debug("dimm: "); + print_debug_hex8(i); print_debug(".1: "); print_debug_hex8(device); for(j = 0; j < 256; j++) { @@ -847,13 +847,13 @@ static void dump_spd_registers(const struct mem_controller *ctrl) } } } - + static unsigned int cpuid(unsigned int op) { unsigned int ret; unsigned dummy2,dummy3,dummy4; - asm volatile ( - "cpuid" + asm volatile ( + "cpuid" : "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4) : "a" (op) ); @@ -870,13 +870,13 @@ static int is_cpu_pre_c0(void) static void memreset_setup(void) { if (is_cpu_pre_c0()) { - + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 28); - + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), 0x0f00 + 0xc0 + 29); } else { - + outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 29); } } @@ -884,15 +884,15 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - + outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), 0x0f00 + 0xc0 + 28); udelay(90); } } static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes) { - - uint32_t ret=0x00010101; + + uint32_t ret=0x00010101; static const unsigned int rows_2p[2][2] = { { 0x00050101, 0x00010404 }, { 0x00010404, 0x00050101 } @@ -910,33 +910,33 @@ static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } - + static void coherent_ht_mainboard(unsigned cpus) { } - + void cpu_ldtstop(unsigned cpus) { uint32_t tmp; device_t dev; unsigned cnt; for(cnt=0; cnt<cpus; cnt++) { - + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0x81,0x23); - + pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd4,0x00000701); - + pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) ,0xd8,0x00000000); - + tmp=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90); pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24 ) & 0x1f) << 11) | ((( 2 ) & 0x7) << 8)) ,0x90, tmp | (1<<24) ); } } - - - - - + + + + + static void setup_resource_map(const unsigned int *register_values, int max) { int i; @@ -957,8 +957,8 @@ static void setup_resource_map(const unsigned int *register_values, int max) static void setup_default_resource_map(void) { static const unsigned int register_values[] = { - - + + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, @@ -967,7 +967,7 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, @@ -976,7 +976,7 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x84 ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x8C ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0x00000048, 0x00000000, @@ -985,7 +985,7 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xAC ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB4 ) & 0xFF)) , 0x00000048, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xBC ) & 0xFF)) , 0x00000048, 0x00ffff00, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0x000000f0, 0x00000000, @@ -994,17 +994,17 @@ static void setup_default_resource_map(void) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xA8 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB0 ) & 0xFF)) , 0x000000f0, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xB8 ) & 0xFF)) , 0x000000f0, 0x00fc0003, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC4 ) & 0xFF)) , 0xFE000FC8, 0x01fff000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xCC ) & 0xFF)) , 0xFE000FC8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD4 ) & 0xFF)) , 0xFE000FC8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xDC ) & 0xFF)) , 0xFE000FC8, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC0 ) & 0xFF)) , 0xFE000FCC, 0x00000003, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xC8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD0 ) & 0xFF)) , 0xFE000FCC, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xD8 ) & 0xFF)) , 0xFE000FCC, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE0 ) & 0xFF)) , 0x0000FC88, 0xff000003, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE4 ) & 0xFF)) , 0x0000FC88, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0xE8 ) & 0xFF)) , 0x0000FC88, 0x00000000, @@ -1017,8 +1017,8 @@ static void setup_default_resource_map(void) static void sdram_set_registers(const struct mem_controller *ctrl) { static const unsigned int register_values[] = { - - + + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x0000f8f8, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x4C ) & 0xFF)) , 0x0000f8f8, 0x00000001, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x0000f8f8, 0x00000002, @@ -1027,7 +1027,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x6C ) & 0xFF)) , 0x0000f8f8, 0x00000005, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0x0000f8f8, 0x00000006, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0x0000f8f8, 0x00000007, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x50 ) & 0xFF)) , 0x0000f8fc, 0x00000000, @@ -1036,7 +1036,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x70 ) & 0xFF)) , 0x0000f8fc, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 1 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0x0000f8fc, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x40 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x44 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x48 ) & 0xFF)) , 0x001f01fe, 0x00000000, @@ -1045,7 +1045,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x54 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0x001f01fe, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x001f01fe, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x64 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x68 ) & 0xFF)) , 0xC01f01ff, 0x00000000, @@ -1054,33 +1054,33 @@ static void sdram_set_registers(const struct mem_controller *ctrl) ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x74 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x78 ) & 0xFF)) , 0xC01f01ff, 0x00000000, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x7C ) & 0xFF)) , 0xC01f01ff, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x80 ) & 0xFF)) , 0xffff8888, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x88 ) & 0xFF)) , 0xe8088008, 0x02522001 , - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x8c ) & 0xFF)) , 0xff8fe08e, (0 << 20)|(0 << 8)|(0 << 4)|(0 << 0), - - ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xf0000000, - (4 << 25)|(0 << 24)| - (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| - (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| - (2 << 14)|(0 << 13)|(0 << 12)| - (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| + + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xf0000000, + (4 << 25)|(0 << 24)| + (0 << 23)|(0 << 22)|(0 << 21)|(0 << 20)| + (1 << 19)|(0 << 18)|(1 << 17)|(0 << 16)| + (2 << 14)|(0 << 13)|(0 << 12)| + (0 << 11)|(0 << 10)|(0 << 9)|(0 << 8)| (0 << 3) |(0 << 1) |(0 << 0), - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xc180f0f0, (0 << 29)|(0 << 28)|(0 << 27)|(0 << 26)|(0 << 25)| (0 << 20)|(0 << 19)|(3 << 16)|(0 << 8)|(0 << 0), - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 2 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0xfc00ffff, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x58 ) & 0xFF)) , 0xffe0e0e0, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x5C ) & 0xFF)) , 0x0000003e, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x60 ) & 0xFF)) , 0xffffff00, 0x00000000, - + ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x94 ) & 0xFF)) , 0xffff8000, 0x00000f70, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x90 ) & 0xFF)) , 0xffffff80, 0x00000002, ( ((( 0 ) & 0xFF) << 16) | ((( 0x18 ) & 0x1f) << 11) | ((( 3 ) & 0x07) << 8) | (( 0x98 ) & 0xFF)) , 0x0000000f, 0x00068300, @@ -1112,14 +1112,14 @@ static int is_dual_channel(const struct mem_controller *ctrl) } static int is_opteron(const struct mem_controller *ctrl) { - + uint32_t nbcap; nbcap = pci_read_config32(ctrl->f3, 0xE8 ); return !!(nbcap & 0x0001 ); } static int is_registered(const struct mem_controller *ctrl) { - + uint32_t dcl; dcl = pci_read_config32(ctrl->f2, 0x90 ); return !(dcl & (1<<18) ); @@ -1130,45 +1130,45 @@ struct dimm_size { }; static struct dimm_size spd_get_dimm_size(unsigned device) { - + struct dimm_size sz; int value, low; sz.side1 = 0; sz.side2 = 0; - - value = spd_read_byte(device, 3); + + value = spd_read_byte(device, 3); if (value < 0) goto out; sz.side1 += value & 0xf; - value = spd_read_byte(device, 4); + value = spd_read_byte(device, 4); if (value < 0) goto out; sz.side1 += value & 0xf; - value = spd_read_byte(device, 17); + value = spd_read_byte(device, 17); if (value < 0) goto out; sz.side1 += log2(value & 0xff); - - value = spd_read_byte(device, 7); + + value = spd_read_byte(device, 7); if (value < 0) goto out; value &= 0xff; value <<= 8; - - low = spd_read_byte(device, 6); + + low = spd_read_byte(device, 6); if (low < 0) goto out; value = value | (low & 0xff); sz.side1 += log2(value); - - value = spd_read_byte(device, 5); + + value = spd_read_byte(device, 5); if (value <= 1) goto out; - + sz.side2 = sz.side1; - value = spd_read_byte(device, 3); + value = spd_read_byte(device, 3); if (value < 0) goto out; - if ((value & 0xf0) == 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); - value = spd_read_byte(device, 4); + if ((value & 0xf0) == 0) goto out; + sz.side2 -= (value & 0x0f); + sz.side2 += ((value >> 4) & 0x0f); + value = spd_read_byte(device, 4); if (value < 0) goto out; - sz.side2 -= (value & 0x0f); - sz.side2 += ((value >> 4) & 0x0f); + sz.side2 -= (value & 0x0f); + sz.side2 += ((value >> 4) & 0x0f); out: return sz; } @@ -1181,32 +1181,32 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz } map = pci_read_config32(ctrl->f2, 0x80 ); map &= ~(0xf << (index + 4)); - - + + base0 = base1 = 0; - + if (sz.side1 >= (25 +3)) { map |= (sz.side1 - (25 + 3)) << (index *4); base0 = (1 << ((sz.side1 - (25 + 3)) + 21)) | 1; } - + if (sz.side2 >= (25 + 3)) { base1 = (1 << ((sz.side2 - (25 + 3)) + 21)) | 1; } - + if (is_dual_channel(ctrl)) { base0 = (base0 << 1) | (base0 & 1); base1 = (base1 << 1) | (base1 & 1); } - + base0 &= ~0x001ffffe; base1 &= ~0x001ffffe; - + pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), base0); pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), base1); pci_write_config32(ctrl->f2, 0x80 , map); - - + + if (base0) { dch = pci_read_config32(ctrl->f2, 0x94 ); dch |= (1 << 26) << index; @@ -1216,7 +1216,7 @@ static void set_dimm_size(const struct mem_controller *ctrl, struct dimm_size sz static void spd_set_ram_size(const struct mem_controller *ctrl) { int i; - + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { struct dimm_size sz; sz = spd_get_dimm_size(ctrl->channel0[i]); @@ -1226,7 +1226,7 @@ static void spd_set_ram_size(const struct mem_controller *ctrl) static void route_dram_accesses(const struct mem_controller *ctrl, unsigned long base_k, unsigned long limit_k) { - + unsigned node_id; unsigned limit; unsigned base; @@ -1251,25 +1251,25 @@ static void route_dram_accesses(const struct mem_controller *ctrl, } static void set_top_mem(unsigned tom_k) { - + if (!tom_k) { set_bios_reset(); print_debug("No memory - reset"); - + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 0x04 ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0x41, 0xf1); - + outb(0x0e, 0x0cf9); } - + print_debug("RAM: 0x"); print_debug_hex32(tom_k); print_debug(" KB\r\n"); - + msr_t msr; msr.lo = (tom_k & 0x003fffff) << 10; msr.hi = (tom_k & 0xffc00000) >> 22; wrmsr(0xC001001D , msr); - + if (tom_k >= 0x003f0000) { tom_k = 0x3f0000; } @@ -1279,15 +1279,15 @@ static void set_top_mem(unsigned tom_k) } static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) { - - static const uint32_t csbase_low[] = { + + static const uint32_t csbase_low[] = { (1 << (13 - 4)), (1 << (14 - 4)), - (1 << (14 - 4)), + (1 << (14 - 4)), (1 << (15 - 4)), (1 << (15 - 4)), (1 << (16 - 4)), - (1 << (16 - 4)), + (1 << (16 - 4)), }; uint32_t csbase_inc; int chip_selects, index; @@ -1295,16 +1295,16 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) int dual_channel; unsigned common_size; uint32_t csbase, csmask; - + chip_selects = 0; common_size = 0; for(index = 0; index < 8; index++) { unsigned size; uint32_t value; - + value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - - + + if (!(value & 1)) { continue; } @@ -1313,36 +1313,36 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) if (common_size == 0) { common_size = size; } - + if (common_size != size) { return 0; } } - + bits = log2(chip_selects); if (((1 << bits) != chip_selects) || (bits < 1) || (bits > 3)) { return 0; - + } - + if ((bits == 3) && (common_size == (1 << (32 - 3)))) { print_debug("8 4GB chip selects cannot be interleaved\r\n"); return 0; } - + if (is_dual_channel(ctrl)) { csbase_inc = csbase_low[log2(common_size) - 1] << 1; } else { csbase_inc = csbase_low[log2(common_size)]; } - + csbase = 0 | 1; csmask = (((common_size << bits) - 1) << 21); csmask |= 0xfe00 & ~((csbase_inc << bits) - csbase_inc); for(index = 0; index < 8; index++) { uint32_t value; value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - + if (!(value & 1)) { continue; } @@ -1350,19 +1350,19 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl) pci_write_config32(ctrl->f2, 0x60 + (index << 2), csmask); csbase += csbase_inc; } - + print_debug("Interleaved\r\n"); - + return common_size << (15 + bits); } static unsigned long order_chip_selects(const struct mem_controller *ctrl) { unsigned long tom; - - + + tom = 0; for(;;) { - + unsigned index, canidate; uint32_t csbase, csmask; unsigned size; @@ -1371,46 +1371,46 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) for(index = 0; index < 8; index++) { uint32_t value; value = pci_read_config32(ctrl->f2, 0x40 + (index << 2)); - + if (!(value & 1)) { continue; } - - + + if (value <= csbase) { continue; } - - + + if (tom & (1 << (index + 24))) { continue; } - + csbase = value; canidate = index; } - + if (csbase == 0) { break; } - + size = csbase >> 21; - + tom |= (1 << (canidate + 24)); - + csbase = (tom << 21) | 1; - + tom += size; - + csmask = ((size -1) << 21); - csmask |= 0xfe00; - + csmask |= 0xfe00; + pci_write_config32(ctrl->f2, 0x40 + (canidate << 2), csbase); - + pci_write_config32(ctrl->f2, 0x60 + (canidate << 2), csmask); - + } - + return (tom & ~0xff000000) << 15; } static void order_dimms(const struct mem_controller *ctrl) @@ -1421,14 +1421,14 @@ static void order_dimms(const struct mem_controller *ctrl) if (!tom_k) { tom_k = order_chip_selects(ctrl); } - + base_k = 0; for(node_id = 0; node_id < ctrl->node_id; node_id++) { uint32_t limit, base; unsigned index; index = node_id << 3; base = pci_read_config32(ctrl->f1, 0x40 + index); - + if ((base & 3) == 3) { limit = pci_read_config32(ctrl->f1, 0x44 + index); base_k = ((limit + 0x00010000) & 0xffff0000) >> 2; @@ -1440,8 +1440,8 @@ static void order_dimms(const struct mem_controller *ctrl) } static void disable_dimm(const struct mem_controller *ctrl, unsigned index) { - print_debug("disabling dimm"); - print_debug_hex8(index); + print_debug("disabling dimm"); + print_debug_hex8(index); print_debug("\r\n"); pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+0)<<2), 0); pci_write_config32(ctrl->f2, 0x40 + (((index << 1)+1)<<2), 0); @@ -1461,11 +1461,11 @@ static void spd_handle_unbuffered_dimms(const struct mem_controller *ctrl) disable_dimm(ctrl, i); continue; } - + if (value & (1 << 1)) { registered = 1; - } - + } + else { unbuffered = 1; } @@ -1487,29 +1487,29 @@ static void spd_enable_2channels(const struct mem_controller *ctrl) { int i; uint32_t nbcap; - - + + static const unsigned addresses[] = { - 2, - 3, - 4, - 5, - 6, - 7, - 9, - 11, - 13, - 17, - 18, - 21, - 23, - 26, - 27, - 28, - 29, - 30, - 41, - 42, + 2, + 3, + 4, + 5, + 6, + 7, + 9, + 11, + 13, + 17, + 18, + 21, + 23, + 26, + 27, + 28, + 29, + 30, + 41, + 42, }; nbcap = pci_read_config32(ctrl->f3, 0xE8 ); if (!(nbcap & 0x0001 )) { @@ -1548,7 +1548,7 @@ static void spd_enable_2channels(const struct mem_controller *ctrl) } struct mem_param { uint8_t cycle_time; - uint8_t divisor; + uint8_t divisor; uint8_t tRC; uint8_t tRFC; uint32_t dch_memclk; @@ -1621,35 +1621,35 @@ static const struct mem_param *get_mem_param(unsigned min_cycle_time) } static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) { - + const struct mem_param *param; unsigned min_cycle_time, min_latency; int i; uint32_t value; static const int latency_indicies[] = { 26, 23, 9 }; static const unsigned char min_cycle_times[] = { - [0 ] = 0x50, - [1 ] = 0x60, - [2 ] = 0x75, - [3 ] = 0xa0, + [0 ] = 0x50, + [1 ] = 0x60, + [2 ] = 0x75, + [3 ] = 0xa0, }; value = pci_read_config32(ctrl->f3, 0xE8 ); min_cycle_time = min_cycle_times[(value >> 5 ) & 3 ]; min_latency = 2; - + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int new_cycle_time, new_latency; int index; int latencies; int latency; - + new_cycle_time = 0xa0; new_latency = 5; latencies = spd_read_byte(ctrl->channel0[i], 18); if (latencies <= 0) continue; - + latency = log2(latencies) -2; - + for(index = 0; index < 3; index++, latency++) { int value; if ((latency < 2) || (latency > 4) || @@ -1660,7 +1660,7 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (value < 0) { continue; } - + if ((value >= min_cycle_time) && (value < new_cycle_time)) { new_cycle_time = value; new_latency = latency; @@ -1669,17 +1669,17 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (new_latency > 4){ continue; } - + if (new_cycle_time > min_cycle_time) { min_cycle_time = new_cycle_time; } - + if (new_latency > min_latency) { min_latency = new_latency; } } - - + + for(i = 0; (i < 4) && (ctrl->channel0[i]); i++) { int latencies; int latency; @@ -1690,9 +1690,9 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (latencies <= 0) { goto dimm_err; } - + latency = log2(latencies) -2; - + for(index = 0; index < 3; index++, latency++) { if (!(latencies & (1 << latency))) { continue; @@ -1700,36 +1700,36 @@ static const struct mem_param *spd_set_memclk(const struct mem_controller *ctrl) if (latency == min_latency) break; } - + if ((latency != min_latency) || (index >= 3)) { goto dimm_err; } - - + + value = spd_read_byte(ctrl->channel0[i], latency_indicies[index]); - - + + if (value <= min_cycle_time) { continue; } - + dimm_err: disable_dimm(ctrl, i); } - + param = get_mem_param(min_cycle_time); - + value = pci_read_config32(ctrl->f2, 0x94 ); value &= ~(0x7 << 20 ); value |= param->dch_memclk; pci_write_config32(ctrl->f2, 0x94 , value); static const unsigned latencies[] = { 1 , 5 , 2 }; - + value = pci_read_config32(ctrl->f2, 0x88 ); value &= ~(0x7 << 0 ); value |= latencies[min_latency - 2] << 0 ; pci_write_config32(ctrl->f2, 0x88 , value); - + return param; } static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_param *param, int i) @@ -1974,7 +1974,7 @@ static void set_Twtr(const struct mem_controller *ctrl, const struct mem_param * { uint32_t dth; unsigned clocks; - clocks = 1; + clocks = 1; dth = pci_read_config32(ctrl->f2, 0x8c ); dth &= ~(0x1 << 0 ); dth |= ((clocks - 1 ) << 0 ); @@ -1993,11 +1993,11 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * if (is_opteron(ctrl)) { if (latency == 1 ) { if (divisor == ((6 << 0) + 0)) { - + clocks = 3; } else if (divisor > ((6 << 0)+0)) { - + clocks = 2; } } @@ -2006,11 +2006,11 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * } else if (latency == 2 ) { if (divisor == ((6 << 0)+0)) { - + clocks = 4; } else if (divisor > ((6 << 0)+0)) { - + clocks = 3; } } @@ -2042,7 +2042,7 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * if ((clocks < 1 ) || (clocks > 6 )) { die("Unknown Trwt"); } - + dth = pci_read_config32(ctrl->f2, 0x8c ); dth &= ~(0x7 << 4 ); dth |= ((clocks - 1 ) << 4 ); @@ -2051,7 +2051,7 @@ static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param * } static void set_Twcl(const struct mem_controller *ctrl, const struct mem_param *param) { - + uint32_t dth; unsigned clocks; if (is_registered(ctrl)) { @@ -2075,19 +2075,19 @@ static void set_read_preamble(const struct mem_controller *ctrl, const struct me rdpreamble = 0; if (is_registered(ctrl)) { if (divisor == ((10 << 1)+0)) { - + rdpreamble = ((9 << 1)+ 0); } else if (divisor == ((7 << 1)+1)) { - + rdpreamble = ((8 << 1)+0); } else if (divisor == ((6 << 1)+0)) { - + rdpreamble = ((7 << 1)+1); } else if (divisor == ((5 << 1)+0)) { - + rdpreamble = ((7 << 1)+0); } } @@ -2101,42 +2101,42 @@ static void set_read_preamble(const struct mem_controller *ctrl, const struct me } } if (divisor == ((10 << 1)+0)) { - + if (slots <= 2) { - + rdpreamble = ((9 << 1)+0); } else { - + rdpreamble = ((14 << 1)+0); } } else if (divisor == ((7 << 1)+1)) { - + if (slots <= 2) { - + rdpreamble = ((7 << 1)+0); } else { - + rdpreamble = ((11 << 1)+0); } } else if (divisor == ((6 << 1)+0)) { - + if (slots <= 2) { - + rdpreamble = ((7 << 1)+0); } else { - + rdpreamble = ((9 << 1)+0); } } else if (divisor == ((5 << 1)+0)) { - + if (slots <= 2) { - + rdpreamble = ((5 << 1)+0); } else { - + rdpreamble = ((7 << 1)+0); } } @@ -2159,11 +2159,11 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc async_lat = 0; if (is_registered(ctrl)) { if (dimms == 4) { - + async_lat = 9; - } + } else { - + async_lat = 8; } } @@ -2172,11 +2172,11 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc die("Too many unbuffered dimms"); } else if (dimms == 3) { - + async_lat = 7; } else { - + async_lat = 6; } } @@ -2186,7 +2186,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param) { uint32_t dch; - + dch = pci_read_config32(ctrl->f2, 0x94 ); dch &= ~(0x7 << 16 ); dch |= 3 << 16 ; @@ -2198,39 +2198,39 @@ static void spd_set_dram_timing(const struct mem_controller *ctrl, const struct int dimms; int i; int rc; - + init_Tref(ctrl, param); for(i = 0; (i < 4) && ctrl->channel0[i]; i++) { int rc; - + if (update_dimm_Trc (ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trfc(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trcd(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trrd(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Tras(ctrl, param, i) < 0) goto dimm_err; if (update_dimm_Trp (ctrl, param, i) < 0) goto dimm_err; - + if (update_dimm_Tref(ctrl, param, i) < 0) goto dimm_err; - + if (update_dimm_x4 (ctrl, param, i) < 0) goto dimm_err; if (update_dimm_ecc(ctrl, param, i) < 0) goto dimm_err; continue; dimm_err: disable_dimm(ctrl, i); - + } - + set_Twr(ctrl, param); - + set_Twtr(ctrl, param); set_Trwt(ctrl, param); set_Twcl(ctrl, param); - + set_read_preamble(ctrl, param); set_max_async_latency(ctrl, param); set_idle_cycle_limit(ctrl, param); } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { const struct mem_param *param; spd_enable_2channels(ctrl); @@ -2243,18 +2243,18 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) static void sdram_enable(int controllers, const struct mem_controller *ctrl) { int i; - + for(i = 0; i < controllers; i++) { uint32_t dch; dch = pci_read_config32(ctrl[i].f2, 0x94 ); dch |= (1 << 25) ; pci_write_config32(ctrl[i].f2, 0x94 , dch); } - + memreset(controllers, ctrl); for(i = 0; i < controllers; i++) { uint32_t dcl; - + dcl = pci_read_config32(ctrl[i].f2, 0x90 ); if (dcl & (1<<17) ) { uint32_t mnc; @@ -2294,7 +2294,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) if (dcl & (1<<17) ) { print_debug("Clearing memory: "); if (!is_cpu_pre_c0()) { - + dcl &= ~((1<<11) | (1<<10) ); pci_write_config32(ctrl[i].f2, 0x90 , dcl); do { @@ -2304,10 +2304,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) uint32_t base, last_scrub_k, scrub_k; uint32_t cnt,zstart,zend; msr_t msr,msr_201; - + pci_write_config32(ctrl[i].f3, 0x58 , (0 << 16) | (0 << 8) | (0 << 0)); - + msr_201 = rdmsr(0x201); zstart = pci_read_config32(ctrl[0].f1, 0x40 + (i*8)); zend = pci_read_config32(ctrl[0].f1, 0x44 + (i*8)); @@ -2318,50 +2318,50 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) print_debug("-"); print_debug_hex32(zend); print_debug("\r\n"); - - + + msr = rdmsr(0x2ff ); msr.lo &= ~(1<<10); wrmsr(0x2ff , msr); - + msr = rdmsr(0xc0010015); msr.lo |= (1<<17); wrmsr(0xc0010015,msr); for(;zstart<zend;zstart+=4) { - + if(zstart == 0x0fc) continue; - - + + __asm__ volatile( "movl %%cr0, %0\n\t" "orl $0x40000000, %0\n\t" "movl %0, %%cr0\n\t" :"=r" (cnt) ); - - + + msr.lo = 1 + ((zstart&0x0ff)<<24); msr.hi = (zstart&0x0ff00)>>8; wrmsr(0x200,msr); - + msr.hi = 0x000000ff; msr.lo = 0xfc000800; wrmsr(0x201,msr); - + __asm__ volatile( "movl %%cr0, %0\n\t" "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) + "movl %0, %%cr0\n\t" + :"=r" (cnt) ); - + msr.lo = (zstart&0xff) << 24; msr.hi = (zstart&0xff00) >> 8; wrmsr(0xc0000100,msr); - print_debug_char((zstart > 0x0ff)?'+':'-'); - - + print_debug_char((zstart > 0x0ff)?'+':'-'); + + __asm__ volatile( "1: \n\t" "movl %0, %%fs:(%1)\n\t" @@ -2370,67 +2370,67 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) "jnz 1b\n\t" : : "a" (0), "D" (0), "c" (0x01000000) - ); + ); } - - + + __asm__ volatile( "movl %%cr0, %0\n\t" "orl $0x40000000, %0\n\t" "movl %0, %%cr0\n\t" - :"=r" (cnt) + :"=r" (cnt) ); - - + + msr = rdmsr(0x2ff ); msr.lo |= 0x0400; wrmsr(0x2ff , msr); - + msr.lo = 6; msr.hi = 0; wrmsr(0x200,msr); wrmsr(0x201,msr_201); - + msr.lo = 0; msr.hi = 0; wrmsr(0xc0000100,msr); - + __asm__ volatile( "movl %%cr0, %0\n\t" "andl $0x9fffffff, %0\n\t" - "movl %0, %%cr0\n\t" - :"=r" (cnt) + "movl %0, %%cr0\n\t" + :"=r" (cnt) ); - - + + msr = rdmsr(0xc0010015); msr.lo &= ~(1<<17); wrmsr(0xc0010015,msr); - + base = pci_read_config32(ctrl[i].f1, 0x40 + (ctrl[i].node_id << 3)); base &= 0xffff0000; - + pci_write_config32(ctrl[i].f3, 0x5C , base << 8); pci_write_config32(ctrl[i].f3, 0x60 , base >> 24); - - pci_write_config32(ctrl[i].f3, 0x58 , + + pci_write_config32(ctrl[i].f3, 0x58 , (22 << 16) | (22 << 8) | (22 << 0)); print_debug("done\r\n"); } } } - - - - - + + + + + typedef uint8_t u8; typedef uint32_t u32; typedef int8_t bool; static void disable_probes(void) { - - + + u32 val; print_debug("Disabling read/write/fill probes for UP... "); val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68); @@ -2438,8 +2438,8 @@ static void disable_probes(void) pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x68, val); print_debug("done.\r\n"); } - -static void wait_ap_stop(u8 node) + +static void wait_ap_stop(u8 node) { unsigned long reg; unsigned long i; @@ -2449,7 +2449,7 @@ static void wait_ap_stop(u8 node) if((regx & (1<<4))==1) break; } reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0x6c); - reg &= ~(1<<4); + reg &= ~(1<<4); pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, reg); } static void notify_bsp_ap_is_stopped(void) @@ -2458,31 +2458,31 @@ static void notify_bsp_ap_is_stopped(void) unsigned long apic_id; apic_id = *((volatile unsigned long *)(0xfee00000 + 0x020 )); apic_id >>= 24; - + if(apic_id != 0) { - + reg = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C); reg |= 1<<4; pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ apic_id ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6C, reg); } - + } - + static void enable_routing(u8 node) { u32 val; - - + + print_debug("Enabling routing table for node "); print_debug_hex32(node); val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c); val &= ~((1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0)); pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x6c, val); - + if(node!=0) { wait_ap_stop(node); } - + print_debug(" done.\r\n"); } static void rename_temp_node(u8 node) @@ -2491,21 +2491,21 @@ static void rename_temp_node(u8 node) print_debug("Renaming current temp node to "); print_debug_hex32(node); val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60); - val &= (~7); - val |= node; + val &= (~7); + val |= node; pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x60, val); print_debug(" done.\r\n"); } static bool check_connection(u8 src, u8 dest, u8 link) { - + u32 val; - - + + val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ src ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x98+link); if ( (val&0x17) != 0x03) return 0; - + val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ dest ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) ,0); if(val != 0x11001022) return 0; @@ -2518,37 +2518,37 @@ static void optimize_connection(u8 node1, u8 link1, u8 node2, u8 link2) uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask; uint8_t width_cap1, width_cap2, width_cap, width, ln_width1, ln_width2; uint8_t freq; - - + + freq_cap1 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x0a ); freq_cap2 = pci_read_config16(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x0a ); - - + + freq = log2(freq_cap1 & freq_cap2 & 0xff); - + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 0x09 , freq); pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 0x09 , freq); - + width_cap1 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 ); width_cap2 = pci_read_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 ); - + ln_width1 = link_width_to_pow2[width_cap1 & 7]; ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7]; if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width = pow2_to_link_width[ln_width1]; - + ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7]; ln_width2 = link_width_to_pow2[width_cap2 & 7]; if (ln_width1 > ln_width2) { ln_width1 = ln_width2; } width |= pow2_to_link_width[ln_width1] << 4; - - + + pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link1 + 6 + 1, width); - + width = ((width & 0x70) >> 4) | ((width & 0x7) << 4); pci_write_config8(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node2 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , 0x80 + link2 + 6 + 1, width); } @@ -2576,8 +2576,8 @@ static void setup_remote_row(u8 source, u8 dest, u8 cpus) } static void setup_remote_node(u8 node, u8 cpus) { - static const uint8_t pci_reg[] = { - 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, + static const uint8_t pci_reg[] = { + 0x44, 0x4c, 0x54, 0x5c, 0x64, 0x6c, 0x74, 0x7c, 0x40, 0x48, 0x50, 0x58, 0x60, 0x68, 0x70, 0x78, 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, @@ -2590,7 +2590,7 @@ static void setup_remote_node(u8 node, u8 cpus) print_debug("setup_remote_node\r\n"); for(row=0; row<cpus; row++) setup_remote_row(node, row, cpus); - + for(i = 0; i < sizeof(pci_reg)/sizeof(pci_reg[0]); i++) { uint32_t value; uint8_t reg; @@ -2611,24 +2611,24 @@ static u8 setup_smp(void) u8 cpus=2; print_debug("Enabling SMP settings\r\n"); setup_row(0,0,cpus); - + setup_temp_row(0,1,cpus); - + if (!check_connection(0, 7, 0x20 )) { print_debug("No connection to Node 1.\r\n"); - fill_row( 0 ,7,0x00010101 ) ; - setup_uniprocessor(); + fill_row( 0 ,7,0x00010101 ) ; + setup_uniprocessor(); return 1; } - + optimize_connection(0, 0x20 , 7, 0x20 ); - setup_node(0, cpus); - setup_remote_node(1, cpus); - rename_temp_node(1); - enable_routing(1); - - fill_row( 0 ,7,0x00010101 ) ; - + setup_node(0, cpus); + setup_remote_node(1, cpus); + rename_temp_node(1); + enable_routing(1); + + fill_row( 0 ,7,0x00010101 ) ; + print_debug_hex32(cpus); print_debug(" nodes initialized.\r\n"); return cpus; @@ -2641,29 +2641,29 @@ static unsigned detect_mp_capabilities(unsigned cpus) print_debug_hex32(cpus); print_debug("\r\n"); if (cpus>2) - mask=0x06; + mask=0x06; else - mask=0x02; + mask=0x02; for (node=0; node<cpus; node++) { if ((pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node ) & 0x1f) << 11) | ((( 3 ) & 0x7) << 8)) , 0xe8) & mask)!=mask) mp_cap= (0) ; } if (mp_cap) return cpus; - + print_debug("One of the CPUs is not MP capable. Going back to UP\r\n"); for (node=cpus; node>0; node--) for (row=cpus; row>0; row--) fill_row(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node-1 ) & 0x1f) << 11) | ((( 0 ) & 0x7) << 8)) , row-1, 0x00010101 ); - + return setup_uniprocessor(); } static void coherent_ht_finalize(unsigned cpus) { int node; bool rev_a0; - - + + print_debug("coherent_ht_finalize\r\n"); rev_a0= is_cpu_rev_a0(); for (node=0; node<cpus; node++) { @@ -2691,36 +2691,36 @@ static int setup_coherent_ht_domain(void) cpus=setup_smp(); cpus=detect_mp_capabilities(cpus); coherent_ht_finalize(cpus); - + coherent_ht_mainboard(cpus); return reset_needed; } void sdram_no_memory(void) { print_err("No memory!!\r\n"); - while(1) { - hlt(); + while(1) { + hlt(); } } - + void sdram_initialize(int controllers, const struct mem_controller *ctrl) { int i; - + for(i = 0; i < controllers; i++) { print_debug("Ram1."); print_debug_hex8(i); print_debug("\r\n"); sdram_set_registers(ctrl + i); } - + for(i = 0; i < controllers; i++) { print_debug("Ram2."); print_debug_hex8(i); print_debug("\r\n"); sdram_set_spd_registers(ctrl + i); } - + print_debug("Ram3\r\n"); sdram_enable(controllers, ctrl); print_debug("Ram4\r\n"); @@ -2738,17 +2738,17 @@ static void stop_this_cpu(void) { unsigned apicid; apicid = apic_read(0x020 ) >> 24; - + apic_write(0x310 , (( apicid )<<24) ); apic_write(0x300 , 0x08000 | 0x04000 | 0x00500 ); - + apic_wait_icr_idle(); - + apic_write(0x310 , (( apicid )<<24) ); apic_write(0x300 , 0x08000 | 0x00500 ); - + apic_wait_icr_idle(); - + for(;;) { hlt(); } @@ -2761,7 +2761,7 @@ static void pc87360_enable_serial(void) } static void main(void) { - + static const struct mem_controller cpu[] = { { .node_id = 0, @@ -2797,9 +2797,9 @@ static void main(void) setup_coherent_ht_domain(); enumerate_ht_chain(0); distinguish_cpu_resets(0); - + enable_smbus(); memreset_setup(); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); - + } diff --git a/util/romcc/tests/simple_test.c b/util/romcc/tests/simple_test.c index 4065c51a2fb0..9791d9e352f4 100644 --- a/util/romcc/tests/simple_test.c +++ b/util/romcc/tests/simple_test.c @@ -78,7 +78,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -170,7 +170,7 @@ static void and(void) i = 1; j = 2; k = i && j; - + } static void and_test(void) { @@ -236,9 +236,9 @@ static void fun(void) static void func(void) { int bar, baz; - int i; - - baz = add(1, 2); + int i; + + baz = add(1, 2); baz = add(1, 2); bar = 1; baz = 2; diff --git a/util/romcc/tests/simple_test1.c b/util/romcc/tests/simple_test1.c index 4065c51a2fb0..9791d9e352f4 100644 --- a/util/romcc/tests/simple_test1.c +++ b/util/romcc/tests/simple_test1.c @@ -78,7 +78,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -170,7 +170,7 @@ static void and(void) i = 1; j = 2; k = i && j; - + } static void and_test(void) { @@ -236,9 +236,9 @@ static void fun(void) static void func(void) { int bar, baz; - int i; - - baz = add(1, 2); + int i; + + baz = add(1, 2); baz = add(1, 2); bar = 1; baz = 2; diff --git a/util/romcc/tests/simple_test10.c b/util/romcc/tests/simple_test10.c index 3e7f510d676b..af9bf076a12d 100644 --- a/util/romcc/tests/simple_test10.c +++ b/util/romcc/tests/simple_test10.c @@ -11,7 +11,7 @@ static void spd_set_drb(void) */ unsigned end_of_memory; unsigned char device; - + end_of_memory = 0; /* in multiples of 8MiB */ device = SMBUS_MEM_DEVICE_START; while (device <= SMBUS_MEM_DEVICE_END) { diff --git a/util/romcc/tests/simple_test19.c b/util/romcc/tests/simple_test19.c index 0bdcf422ef35..cb1f4940d791 100644 --- a/util/romcc/tests/simple_test19.c +++ b/util/romcc/tests/simple_test19.c @@ -1,4 +1,4 @@ -static void hlt(void) +static void hlt(void) { __builtin_hlt(); } diff --git a/util/romcc/tests/simple_test2.c b/util/romcc/tests/simple_test2.c index aef936a8ff3b..b576d3064d25 100644 --- a/util/romcc/tests/simple_test2.c +++ b/util/romcc/tests/simple_test2.c @@ -18,7 +18,7 @@ static void spd_set_drb(void) */ unsigned end_of_memory; unsigned device; - + end_of_memory = 0; /* in multiples of 8MiB */ device = SMBUS_MEM_DEVICE_START; while (device <= SMBUS_MEM_DEVICE_END) { diff --git a/util/romcc/tests/simple_test20.c b/util/romcc/tests/simple_test20.c index 1998853af183..f32aeac8af28 100644 --- a/util/romcc/tests/simple_test20.c +++ b/util/romcc/tests/simple_test20.c @@ -86,7 +86,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } diff --git a/util/romcc/tests/simple_test22.c b/util/romcc/tests/simple_test22.c index 81d2ed008d01..a67f5fd36cda 100644 --- a/util/romcc/tests/simple_test22.c +++ b/util/romcc/tests/simple_test22.c @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 diff --git a/util/romcc/tests/simple_test27.c b/util/romcc/tests/simple_test27.c index f278f62e8a4d..ac5236806145 100644 --- a/util/romcc/tests/simple_test27.c +++ b/util/romcc/tests/simple_test27.c @@ -66,7 +66,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -96,7 +96,7 @@ void uart_init(void) void __console_tx_char(unsigned char byte) { uart_tx_byte(byte); - + } void __console_tx_string(char *str) diff --git a/util/romcc/tests/simple_test3.c b/util/romcc/tests/simple_test3.c index 008d0ab52834..864760c4183f 100644 --- a/util/romcc/tests/simple_test3.c +++ b/util/romcc/tests/simple_test3.c @@ -7,7 +7,7 @@ static void spd_set_drb(void) */ unsigned end_of_memory; unsigned device; - + end_of_memory = 0; /* in multiples of 8MiB */ device = 0x50; while (device <= 0x53) { @@ -23,7 +23,7 @@ static void spd_set_drb(void) /* Make it mulitples of 8MB */ side1_bits -= 25; } - + /* Compute the end address for the DRB register */ /* Only process dimms < 2GB (2^8 * 8MB) */ if (1) { diff --git a/util/romcc/tests/simple_test30.c b/util/romcc/tests/simple_test30.c index 6582a91c1acc..ede20917d97f 100644 --- a/util/romcc/tests/simple_test30.c +++ b/util/romcc/tests/simple_test30.c @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 @@ -301,37 +301,37 @@ static void _exit(int status) static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; @@ -484,14 +484,14 @@ static void setup_coherent_ht_domain(void) (((FN) & 0x07) << 8) | \ ((WHERE) & 0xFF)) - /* Routing Table Node i - * F0:0x40 i = 0, + /* Routing Table Node i + * F0:0x40 i = 0, * F0:0x44 i = 1, - * F0:0x48 i = 2, + * F0:0x48 i = 2, * F0:0x4c i = 3, - * F0:0x50 i = 4, + * F0:0x50 i = 4, * F0:0x54 i = 5, - * F0:0x58 i = 6, + * F0:0x58 i = 6, * F0:0x5c i = 7 * [ 0: 3] Request Route * [0] Route to this node @@ -518,7 +518,7 @@ static void setup_coherent_ht_domain(void) PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101, PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101, - /* Hypetransport Transaction Control Register + /* Hypetransport Transaction Control Register * F0:0x68 * [ 0: 0] Disable read byte probe * 0 = Probes issues @@ -560,7 +560,7 @@ static void setup_coherent_ht_domain(void) * [12:12] Change ISOC to Ordered * 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization * 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering. - * [14:13] Buffer Release Priority select + * [14:13] Buffer Release Priority select * 00 = 64 * 01 = 16 * 10 = 8 @@ -667,7 +667,7 @@ static void setup_coherent_ht_domain(void) * [13:13] HT Stop Tristate Enable * 0 = Driven during an LDTSTOP_L * 1 = Tristated during and LDTSTOP_L - * [14:14] Extended CTL Time + * [14:14] Extended CTL Time * 0 = CTL is asserted for 16 bit times during link initialization * 1 = CTL is asserted for 50us during link initialization * [18:16] Max Link Width In (Read-Only?) @@ -933,7 +933,7 @@ static void setup_coherent_ht_domain(void) * 1 = base/limit registers i are read-only * [ 7: 4] Reserved * [31: 8] Memory-Mapped I/O Base Address i (39-16) - * This field defines the upper address bits of a 40bit address + * This field defines the upper address bits of a 40bit address * that defines the start of memory-mapped I/O region i */ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003, @@ -994,7 +994,7 @@ static void setup_coherent_ht_domain(void) * [ 3: 2] Reserved * [ 4: 4] VGA Enable * 0 = VGA matches Disabled - * 1 = matches all address < 64K and where A[9:0] is in the + * 1 = matches all address < 64K and where A[9:0] is in the * range 3B0-3BB or 3C0-3DF independen of the base & limit registers * [ 5: 5] ISA Enable * 0 = ISA matches Disabled @@ -1002,7 +1002,7 @@ static void setup_coherent_ht_domain(void) * from matching agains this base/limit pair * [11: 6] Reserved * [24:12] PCI I/O Base i - * This field defines the start of PCI I/O region n + * This field defines the start of PCI I/O region n * [31:25] Reserved */ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003, diff --git a/util/romcc/tests/simple_test32.c b/util/romcc/tests/simple_test32.c index bd6947a2ba74..28dbb8972e88 100644 --- a/util/romcc/tests/simple_test32.c +++ b/util/romcc/tests/simple_test32.c @@ -3,7 +3,7 @@ void main(void) unsigned long addr, start, stop; start = 0x00100000; stop = 0x00180000; - + for(addr = start; addr < stop ;) { unsigned char ch; @@ -12,7 +12,7 @@ void main(void) while(__builtin_inb(0x3f)) ; __builtin_outb(ch, 0x3f8); - + while(__builtin_inb(0x3f)) ; } diff --git a/util/romcc/tests/simple_test36.c b/util/romcc/tests/simple_test36.c index 9044bda7b97c..53aaf91aedf6 100644 --- a/util/romcc/tests/simple_test36.c +++ b/util/romcc/tests/simple_test36.c @@ -34,7 +34,7 @@ static void order_dimms(void) __builtin_outl(0xc260, 0xCF8); __builtin_outl(csmask, 0xCFC); } - + tom &= ~0xff000000; __builtin_outl(tom, 0x1234); diff --git a/util/romcc/tests/simple_test37.c b/util/romcc/tests/simple_test37.c index 85c622b17d59..d6ddc2ec98b9 100644 --- a/util/romcc/tests/simple_test37.c +++ b/util/romcc/tests/simple_test37.c @@ -4,7 +4,7 @@ static void main(void) csbase = 0x40; csmask = 0xfe00; - + __builtin_outl(csbase, 0x40); __builtin_outl(csmask, 0x60); } diff --git a/util/romcc/tests/simple_test38.c b/util/romcc/tests/simple_test38.c index db001a26a868..9239664fdfd0 100644 --- a/util/romcc/tests/simple_test38.c +++ b/util/romcc/tests/simple_test38.c @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 @@ -301,37 +301,37 @@ static void _exit(int status) static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; @@ -401,15 +401,15 @@ static void goto_test(void) { int i; print_debug("goto_test\n"); - + i = 0; goto bottom; { top: - print_debug("i = "); - print_debug_hex8(i); + print_debug("i = "); + print_debug_hex8(i); print_debug("\n"); - + i = i + 1; } bottom: diff --git a/util/romcc/tests/simple_test39.c b/util/romcc/tests/simple_test39.c index a7b999bf7bf5..1c67cab5907e 100644 --- a/util/romcc/tests/simple_test39.c +++ b/util/romcc/tests/simple_test39.c @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 @@ -301,37 +301,37 @@ static void _exit(int status) static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; @@ -401,15 +401,15 @@ static void goto_test(void) { int i; print_debug("goto_test\n"); - + i = 0; goto bottom; { top: - print_debug("i = "); - print_debug_hex8(i); + print_debug("i = "); + print_debug_hex8(i); print_debug("\n"); - + i = i + 1; } bottom: @@ -424,7 +424,7 @@ struct socket_desc { short across; }; -static void main(void) +static void main(void) { static const struct socket_desc cpu_socketsA[] = { { .up = 2, .down = -1, .across = 1 }, /* Node 0 */ diff --git a/util/romcc/tests/simple_test4.c b/util/romcc/tests/simple_test4.c index 4f72dcad677b..2ac6a4d5f44d 100644 --- a/util/romcc/tests/simple_test4.c +++ b/util/romcc/tests/simple_test4.c @@ -86,7 +86,7 @@ static void pcibios_write_config_dword( int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -149,7 +149,7 @@ void uart_wait_to_tx_byte(void) void uart_wait_until_sent(void) { - while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) + while(!(inb(CONFIG_TTYS0_BASE + UART_LSR) & 0x40)) ; } @@ -274,7 +274,7 @@ void print_spew(char *str) { __console_tx_string(str); } #define PM_BUS 0 #define PM_DEVFN (PIIX4_DEVFN+3) -#if HAVE_CONSTANT_PROPOGATION +#if HAVE_CONSTANT_PROPOGATION #define SMBUS_IO_BASE 0x1000 #define SMBHSTSTAT 0 #define SMBHSTCTL 2 @@ -428,7 +428,7 @@ static void spd_set_drb(void) unsigned end_of_memory; unsigned char device; unsigned char drb_reg; - + end_of_memory = 0; /* in multiples of 8MiB */ device = SMBUS_MEM_DEVICE_START; #if !CALCULATE_DRB_REG @@ -464,13 +464,13 @@ static void spd_set_drb(void) #else side1_bits += log2((((byte2 << 8) | byte)); #endif - + /* now I have the ram size in bits as a power of two (less 1) */ /* Make it mulitples of 8MB */ side1_bits -= 25; /* side two */ - + /* number of physical banks */ byte = smbus_read_byte(device, 5); if (byte > 1) { @@ -487,7 +487,7 @@ static void spd_set_drb(void) #if CALCULATE_DRB_REG drb_reg = ((device - SMBUS_MEM_DEVICE_START) << 1) + 0x60; #endif - + #if HAVE_STRING_SUPPORT print_debug("end_of_memory: "); print_debug_hex32(end_of_memory); print_debug("\n"); #endif diff --git a/util/romcc/tests/simple_test43.c b/util/romcc/tests/simple_test43.c index 4fb2735d8330..464f26f9184a 100644 --- a/util/romcc/tests/simple_test43.c +++ b/util/romcc/tests/simple_test43.c @@ -24,13 +24,13 @@ static void spd_set_memclk(void) if (!loops) { goto end; } - + loops = 1000000; while(--loops) ; - end: + end: ; - + } loops = 1000000; while(--loops) diff --git a/util/romcc/tests/simple_test45.c b/util/romcc/tests/simple_test45.c index beb041708c33..5e8d742fa850 100644 --- a/util/romcc/tests/simple_test45.c +++ b/util/romcc/tests/simple_test45.c @@ -10,8 +10,8 @@ static void spd_set_memclk(void) device = 0x50; new_cycle_time = 0xa0; new_latency = 5; - - + + latency = 0; for(index = 0; index < 3; index++, latency++) { unsigned long loops; @@ -23,10 +23,10 @@ static void spd_set_memclk(void) if (!loops) { continue; } - + __builtin_outb(device, 0xe4); __builtin_outb(index, 0xe8); - + loops = 1000000; while(--loops) ; diff --git a/util/romcc/tests/simple_test46.c b/util/romcc/tests/simple_test46.c index bd84246b027c..0b831254a112 100644 --- a/util/romcc/tests/simple_test46.c +++ b/util/romcc/tests/simple_test46.c @@ -22,16 +22,16 @@ static void spd_set_memclk(void) if (loops < 0) { continue; } - + __builtin_outb(device, 0x10e4); __builtin_outb(address, 0x10e8); - + loops = 1000000; if ((loops?0:-1) < 0) { continue; } } - + if (new_cycle_time > min_cycle_time) { min_cycle_time = new_cycle_time; } diff --git a/util/romcc/tests/simple_test47.c b/util/romcc/tests/simple_test47.c index 28d72eaa9abc..d1c54aeced2e 100644 --- a/util/romcc/tests/simple_test47.c +++ b/util/romcc/tests/simple_test47.c @@ -16,18 +16,18 @@ static void spd_set_memclk(void) for(index = 0; index < 3; index++, latency++) { unsigned long loops; unsigned address = index; - + loops = 1000000; do { } while(--loops); if (loops) { continue; } - + __builtin_outb(device, 0x10e4); - + __builtin_outb(address & 0xFF, 0x10e8); - + loops = 1000000; while(--loops) ; diff --git a/util/romcc/tests/simple_test48.c b/util/romcc/tests/simple_test48.c index 779ecfdc9695..cf9ee8ab0f17 100644 --- a/util/romcc/tests/simple_test48.c +++ b/util/romcc/tests/simple_test48.c @@ -9,5 +9,5 @@ static void main(void) __builtin_outb(j, 0xef90); next: __builtin_outb(i, 0x5678); - + } diff --git a/util/romcc/tests/simple_test49.c b/util/romcc/tests/simple_test49.c index a5a12c1cd84b..b18b4cb4b919 100644 --- a/util/romcc/tests/simple_test49.c +++ b/util/romcc/tests/simple_test49.c @@ -11,5 +11,5 @@ static void main(void) } } __builtin_outb(i, 0x5678); - + } diff --git a/util/romcc/tests/simple_test5.c b/util/romcc/tests/simple_test5.c index efc1e9489a8a..725d7453df79 100644 --- a/util/romcc/tests/simple_test5.c +++ b/util/romcc/tests/simple_test5.c @@ -85,7 +85,7 @@ static void pcibios_write_config_dword( int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -102,7 +102,7 @@ int log2(int value) #define PM_BUS 0 #define PM_DEVFN (PIIX4_DEVFN+3) -#if HAVE_CONSTANT_PROPOGATION +#if HAVE_CONSTANT_PROPOGATION #define SMBUS_IO_BASE 0x1000 #define SMBHSTSTAT 0 #define SMBHSTCTL 2 @@ -290,7 +290,7 @@ static void spd_enable_refresh(void) } byte &= 0x7f; /* Default refresh rate be conservative */ - refresh_rate = 5; + refresh_rate = 5; /* see if the ram refresh is a supported one */ if (byte < 6) { #if HAVE_STATIC_ARRAY_SUPPORT diff --git a/util/romcc/tests/simple_test50.c b/util/romcc/tests/simple_test50.c index 51c7c505c970..f8d29b716fe3 100644 --- a/util/romcc/tests/simple_test50.c +++ b/util/romcc/tests/simple_test50.c @@ -3,17 +3,17 @@ typedef __builtin_ldiv_t ldiv_t; typedef __builtin_udiv_t udiv_t; typedef __builtin_uldiv_t uldiv_t; -static div_t div(int numer, int denom) -{ - return __builtin_div(numer, denom); +static div_t div(int numer, int denom) +{ + return __builtin_div(numer, denom); } -static ldiv_t ldiv(long numer, long denom) -{ - return __builtin_ldiv(numer, denom); +static ldiv_t ldiv(long numer, long denom) +{ + return __builtin_ldiv(numer, denom); } static udiv_t udiv(unsigned numer, unsigned denom) -{ - return __builtin_udiv(numer, denom); +{ + return __builtin_udiv(numer, denom); } static uldiv_t uldiv(unsigned long numer, unsigned long denom) { diff --git a/util/romcc/tests/simple_test54.c b/util/romcc/tests/simple_test54.c index ec3208f4aa66..37dce795c5d3 100644 --- a/util/romcc/tests/simple_test54.c +++ b/util/romcc/tests/simple_test54.c @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 @@ -301,37 +301,37 @@ static void _exit(int status) static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; @@ -407,7 +407,7 @@ static void print_debug(const char *str) { console_tx_string(str); } int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -503,8 +503,8 @@ static unsigned spd_to_dimm(unsigned device) static void disable_dimm(unsigned index) { - print_debug("disabling dimm"); - print_debug_hex8(index); + print_debug("disabling dimm"); + print_debug_hex8(index); print_debug("\r\n"); #if 0 pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0); @@ -587,8 +587,8 @@ static const struct mem_param *spd_set_memclk(void) min_latency = 2; #if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); + print_debug("min_cycle_time: "); + print_debug_hex8(min_cycle_time); print_debug(" min_latency: "); print_debug_hex8(min_latency); print_debug("\r\n"); @@ -648,8 +648,8 @@ static const struct mem_param *spd_set_memclk(void) #if 1 print_debug("device: "); print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); + print_debug(" new_cycle_time: "); + print_debug_hex8(new_cycle_time); print_debug(" new_latency: "); print_debug_hex8(new_latency); print_debug("\r\n"); @@ -661,8 +661,8 @@ static const struct mem_param *spd_set_memclk(void) #if 1 print_debug("device: "); print_debug_hex8(device); - print_debug(" new_cycle_time: "); - print_debug_hex8(new_cycle_time); + print_debug(" new_cycle_time: "); + print_debug_hex8(new_cycle_time); print_debug(" new_latency: "); print_debug_hex8(new_latency); print_debug("\r\n"); @@ -682,8 +682,8 @@ static const struct mem_param *spd_set_memclk(void) #if 1 print_debug("device: "); print_debug_hex8(device); - print_debug(" min_cycle_time: "); - print_debug_hex8(min_cycle_time); + print_debug(" min_cycle_time: "); + print_debug_hex8(min_cycle_time); print_debug(" min_latency: "); print_debug_hex8(min_latency); print_debug("\r\n"); @@ -721,11 +721,11 @@ static const struct mem_param *spd_set_memclk(void) if ((latency != min_latency) || (index >= 3)) { goto dimm_err; } - + /* Read the min_cycle_time for this latency */ value = smbus_read_byte(device, latency_indicies[index]); - - /* All is good if the selected clock speed + + /* All is good if the selected clock speed * is what I need or slower. */ if (value <= min_cycle_time) { @@ -736,8 +736,8 @@ static const struct mem_param *spd_set_memclk(void) disable_dimm(spd_to_dimm(device)); } #if 1 - print_debug("min_cycle_time: "); - print_debug_hex8(min_cycle_time); + print_debug("min_cycle_time: "); + print_debug_hex8(min_cycle_time); print_debug(" min_latency: "); print_debug_hex8(min_latency); print_debug("\r\n"); @@ -759,7 +759,7 @@ static const struct mem_param *spd_set_memclk(void) value |= latencies[min_latency - 2]; pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value); #endif - + return param; } diff --git a/util/romcc/tests/simple_test56.c b/util/romcc/tests/simple_test56.c index 831ee9a4ca2c..570b4eeec3de 100644 --- a/util/romcc/tests/simple_test56.c +++ b/util/romcc/tests/simple_test56.c @@ -31,7 +31,7 @@ static void spd_enable_refresh(void) } byte &= 0x7f; /* Default refresh rate be conservative */ - refresh_rate = 5; + refresh_rate = 5; /* see if the ram refresh is a supported one */ if (byte < 6) { refresh_rate = refresh_rates[byte]; diff --git a/util/romcc/tests/simple_test59.c b/util/romcc/tests/simple_test59.c index 4b0ee36133f1..a54c0435d398 100644 --- a/util/romcc/tests/simple_test59.c +++ b/util/romcc/tests/simple_test59.c @@ -34,7 +34,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsigned long arg2) @@ -45,7 +45,7 @@ static struct syscall_result syscall2(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2)); return syscall_return(res); - + } @@ -58,7 +58,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -70,7 +70,7 @@ static struct syscall_result syscall4(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4)); return syscall_return(res); - + } static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -80,10 +80,10 @@ static struct syscall_result syscall5(unsigned long nr, unsigned long arg1, unsi asm volatile( "int $0x80" : "=a" (res) - : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), + : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3), "S" (arg4), "D" (arg5)); return syscall_return(res); - + } #define NR_exit 1 @@ -301,37 +301,37 @@ static void _exit(int status) static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; diff --git a/util/romcc/tests/simple_test6.c b/util/romcc/tests/simple_test6.c index aba7f1f5493b..147614e84b15 100644 --- a/util/romcc/tests/simple_test6.c +++ b/util/romcc/tests/simple_test6.c @@ -81,7 +81,7 @@ static void pcibios_write_config_dword( int log2(int value) { /* __builtin_bsr is a exactly equivalent to the x86 machine - * instruction with the exception that it returns -1 + * instruction with the exception that it returns -1 * when the value presented to it is zero. * Otherwise __builtin_bsr returns the zero based index of * the highest bit set. @@ -98,7 +98,7 @@ int log2(int value) #define PM_BUS 0 #define PM_DEVFN (PIIX4_DEVFN+3) -#if HAVE_CONSTANT_PROPOGATION +#if HAVE_CONSTANT_PROPOGATION #define SMBUS_IO_BASE 0x1000 #define SMBHSTSTAT 0 #define SMBHSTCTL 2 diff --git a/util/romcc/tests/simple_test61.c b/util/romcc/tests/simple_test61.c index 583a9db36b71..2b235ccd5eac 100644 --- a/util/romcc/tests/simple_test61.c +++ b/util/romcc/tests/simple_test61.c @@ -16,7 +16,7 @@ static void spd_set_nbxcfg(void) /* set the device I'm talking too */ __builtin_outb(device, 0x1004); - + /* poll for transaction completion */ byte = __builtin_inb(0x10); while(byte == 0) { diff --git a/util/romcc/tests/simple_test65.c b/util/romcc/tests/simple_test65.c index 642882c2a2cd..9921e2e9cce3 100644 --- a/util/romcc/tests/simple_test65.c +++ b/util/romcc/tests/simple_test65.c @@ -6,5 +6,5 @@ static void main(void) { enum tag foo; foo = Y; - + } diff --git a/util/romcc/tests/simple_test66.c b/util/romcc/tests/simple_test66.c index 5857855700a1..afc0255345ed 100644 --- a/util/romcc/tests/simple_test66.c +++ b/util/romcc/tests/simple_test66.c @@ -1,8 +1,8 @@ typedef unsigned char uint8_t; static unsigned int generate_row(uint8_t row, uint8_t maxnodes) { - - unsigned int ret=0x00010101; + + unsigned int ret=0x00010101; static const unsigned int rows_2p[2][2] = { { 0x00050101, 0x00010404 }, { 0x00010404, 0x00050101 } diff --git a/util/romcc/tests/simple_test67.c b/util/romcc/tests/simple_test67.c index 3bfdc5a0725a..70d7170292c5 100644 --- a/util/romcc/tests/simple_test67.c +++ b/util/romcc/tests/simple_test67.c @@ -11,7 +11,7 @@ static void main(void) if (!(dcl & (1 << 8))) { if (dimms == 4) { async_lat = 9; - } + } else { async_lat = 8; } diff --git a/util/romcc/tests/simple_test7.c b/util/romcc/tests/simple_test7.c index 571f2cdb71a3..a2065463a31b 100644 --- a/util/romcc/tests/simple_test7.c +++ b/util/romcc/tests/simple_test7.c @@ -1,4 +1,4 @@ -void main(void) +void main(void) { int i; i = 0; @@ -8,5 +8,5 @@ void main(void) j = i++; __builtin_outb(j, 0xdc); } while(i <= 9); - + } diff --git a/util/romcc/tests/simple_test72.c b/util/romcc/tests/simple_test72.c index 2011fea7fa2a..10f6ee9f4dd8 100644 --- a/util/romcc/tests/simple_test72.c +++ b/util/romcc/tests/simple_test72.c @@ -1,37 +1,37 @@ static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; @@ -45,7 +45,7 @@ static void print_debug_char(int c) : : "a" (4), "b" (1), "c" (addr_of_char(c)), "d" (1) ); - + } static void print_debug_nibble(unsigned nibble) { @@ -122,7 +122,7 @@ static void spd_set_memclk(void) int index; int latencies; int latency; - + /* First find the supported CAS latencies * Byte 18 for DDR SDRAM is interpreted: * bit 0 == CAS Latency = 1.0 @@ -138,12 +138,12 @@ static void spd_set_memclk(void) new_latency = 5; latencies = smbus_read_byte(device, 18); - + /* Compute the lowest cas latency supported */ latency = __builtin_bsr(latencies) -2; /* Loop through and find a fast clock with a low latency */ - for(index = 0; index < 1; index++, latency++) + for(index = 0; index < 1; index++, latency++) { int value; @@ -152,7 +152,7 @@ static void spd_set_memclk(void) continue; } value = smbus_read_byte(device, index); - + /* Only increase the latency if we decreas the clock */ if ((value >= min_cycle_time) && (value < new_cycle_time)) { new_cycle_time = value; diff --git a/util/romcc/tests/simple_test73.c b/util/romcc/tests/simple_test73.c index f9e00cd4f8f6..da69cf5e7d59 100644 --- a/util/romcc/tests/simple_test73.c +++ b/util/romcc/tests/simple_test73.c @@ -1,37 +1,37 @@ static const char *addr_of_char(unsigned char ch) { static const char byte[] = { - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, - 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, - 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, - 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, - 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, - 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, - 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, - 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, - 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, - 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, - 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, - 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, - 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, - 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, - 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, + 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, - 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, }; return byte + ch; diff --git a/util/romcc/tests/simple_test74.c b/util/romcc/tests/simple_test74.c index 177e00f29e25..fff1a16e3fe2 100644 --- a/util/romcc/tests/simple_test74.c +++ b/util/romcc/tests/simple_test74.c @@ -24,7 +24,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } @@ -37,7 +37,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } #define NR_exit 1 diff --git a/util/romcc/tests/simple_test75.c b/util/romcc/tests/simple_test75.c index 1ad87bd2a0d7..ae28a3ce1a30 100644 --- a/util/romcc/tests/simple_test75.c +++ b/util/romcc/tests/simple_test75.c @@ -1,7 +1,7 @@ static void goto_test(void) { int i; - + i = 0; goto bottom; { diff --git a/util/romcc/tests/simple_test76.c b/util/romcc/tests/simple_test76.c index 4f682d37d41c..74b1cf1657fc 100644 --- a/util/romcc/tests/simple_test76.c +++ b/util/romcc/tests/simple_test76.c @@ -23,7 +23,7 @@ static struct syscall_result syscall1(unsigned long nr, unsigned long arg1) : "=a" (res) : "a" (nr), "b" (arg1)); return syscall_return(res); - + } static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsigned long arg2, @@ -35,7 +35,7 @@ static struct syscall_result syscall3(unsigned long nr, unsigned long arg1, unsi : "=a" (res) : "a" (nr), "b" (arg1), "c" (arg2), "d" (arg3)); return syscall_return(res); - + } #define NR_exit 1 diff --git a/util/romcc/tests/simple_test81.c b/util/romcc/tests/simple_test81.c index e942679d677c..1f647aae8d0c 100644 --- a/util/romcc/tests/simple_test81.c +++ b/util/romcc/tests/simple_test81.c @@ -4,5 +4,5 @@ static void main(void) i = __builtin_inb(0x1234); int j; j = __builtin_inb(0xabcd); - + } |