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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-10-16 11:55:48 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-19 19:56:06 +0000 |
| commit | 025e0ccc59e6e10d7dd9ba6aa96fec586dc47c9e (patch) | |
| tree | 88154e966f4c9788adcd8885e22cb9c79ae1ddfa /util | |
| parent | e7a1e7d3c49e980774985f3f6fae697dcb129420 (diff) | |
| download | coreboot-025e0ccc59e6e10d7dd9ba6aa96fec586dc47c9e.tar.gz coreboot-025e0ccc59e6e10d7dd9ba6aa96fec586dc47c9e.tar.bz2 coreboot-025e0ccc59e6e10d7dd9ba6aa96fec586dc47c9e.zip | |
intel/fsp: Update cannonlake FSP header
Update cannonlake FSP header file to revision 7.x.15.46. The following
item had been updated:
1. Remove/Hide restricted structure.
2. Add EBR as extention of RMT features.
3. Add cpu wakeup timer UPD.
4. Remove XHCI access lock UPD.
TEST=NONE
Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'util')
0 files changed, 0 insertions, 0 deletions