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| author | Angel Pons <th3fanbus@gmail.com> | 2022-10-07 00:25:33 +0200 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-10-08 21:04:43 +0000 |
| commit | f007ab7b43f920c4a7d44dcc43782705ca32e28a (patch) | |
| tree | b109e4bb57e5f7b745089d5c9d51a30f49c2cc57 /util | |
| parent | aa4cd73409db2564a8d50ce952b083a8148e88f0 (diff) | |
| download | coreboot-f007ab7b43f920c4a7d44dcc43782705ca32e28a.tar.gz coreboot-f007ab7b43f920c4a7d44dcc43782705ca32e28a.tar.bz2 coreboot-f007ab7b43f920c4a7d44dcc43782705ca32e28a.zip | |
util/inteltool: Add support for (non-ULT) Broadwell
Add support for traditional (non-ULT) Broadwell.
Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'util')
| -rw-r--r-- | util/inteltool/inteltool.c | 4 | ||||
| -rw-r--r-- | util/inteltool/inteltool.h | 2 | ||||
| -rw-r--r-- | util/inteltool/memory.c | 2 | ||||
| -rw-r--r-- | util/inteltool/pcie.c | 6 |
4 files changed, 14 insertions, 0 deletions
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 743cd1a10854..8f662373f9f1 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -107,6 +107,10 @@ static const struct { "4th generation (Haswell family) Core Processor ULT" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D, + "5th generation (Broadwell family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M, + "5th generation (Broadwell family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M, "6th generation (Skylake-H family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 44201b120c5f..091e5929b3ba 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -333,6 +333,8 @@ static inline uint32_t inl(unsigned port) #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */ #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */ #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D 0x1610 /* Broadwell (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M 0x1614 /* Broadwell (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2 0x190f /* Skylake (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U 0x1904 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y 0x190c /* Skylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 36d11978f439..a536d39e01c5 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -206,6 +206,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index d392c2810eab..fb29d3201ec2 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -250,6 +250,8 @@ int print_epbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: @@ -369,6 +371,8 @@ int print_dmibar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32; dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */ @@ -496,6 +500,8 @@ int print_pciexbar(struct pci_dev *nb) case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3: case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_Y: |