diff options
| -rw-r--r-- | Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md | 2 | ||||
| -rw-r--r-- | Documentation/soc/intel/fsp/index.md | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index adee88acb295..2cb945ae140e 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -31,7 +31,7 @@ Look at the [flashing tutorial] and the board-specific section. These issues apply to all boards. Have a look at the board-specific issues, too. - TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726) -- MRC caching does not work with cold boot +- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0]) ## ToDo diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index aac7b35a50c6..769b98b4fcd8 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well. * Workaround: none * Issue on public tracker: [Issue 22] +* MRC forces memory re-training on cold boot on boards with Intel SPS + * Releases 3.7.1, 3.7.6 + * Workaround: Flash Intel ME instead of SPS + * Issue on public tracker: [Issue 41] + ### BraswellFsp * Internal UART can't be disabled using PcdEnableHsuart* * Release MR2 @@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well. [Issue 15]: https://github.com/IntelFsp/FSP/issues/15 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35 +[Issue 41]: https://github.com/IntelFsp/FSP/issues/41 |