diff options
| -rw-r--r-- | src/mainboard/pcengines/apu2/OemCustomize.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6e6b5a273a74..95af6ef92d56 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -3,6 +3,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/state_machine.h> +#include "gpio_ftns.h" + static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -78,3 +80,17 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CpbMode = CpbModeAuto; } + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* + * Bank interleaving does not work on this platform. + * Disable it so AGESA will return success. + */ + Post->MemConfig.EnableBankIntlv = FALSE; + /* 4GB variants have ECC */ + if (get_spd_offset()) + Post->MemConfig.EnableEccFeature = TRUE; + else + Post->MemConfig.EnableEccFeature = FALSE; +} |