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-rw-r--r--src/soc/amd/cezanne/cpu.c6
-rw-r--r--src/soc/amd/picasso/cpu.c6
-rw-r--r--src/soc/amd/stoneyridge/cpu.c6
3 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c
index c3d89bf5134f..440b5ba28b9b 100644
--- a/src/soc/amd/cezanne/cpu.c
+++ b/src/soc/amd/cezanne/cpu.c
@@ -51,9 +51,9 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus)
{
- /* Clear for take-off */
- /* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(cpu_bus, &mp_ops);
+ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
+ die_with_post_code(POST_HW_INIT_FAILURE,
+ "mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 9822326afe36..b80b0f7a2e65 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -55,9 +55,9 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus)
{
- /* Clear for take-off */
- /* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(cpu_bus, &mp_ops);
+ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
+ die_with_post_code(POST_HW_INIT_FAILURE,
+ "mp_init_with_smm failed. Halting.\n");
/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index 06550327d868..6be76bfde8d9 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -52,9 +52,9 @@ static const struct mp_ops mp_ops = {
void mp_init_cpus(struct bus *cpu_bus)
{
- /* Clear for take-off */
- /* TODO: Handle mp_init_with_smm failure? */
- mp_init_with_smm(cpu_bus, &mp_ops);
+ if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS)
+ die_with_post_code(POST_HW_INIT_FAILURE,
+ "mp_init_with_smm failed. Halting.\n");
/* The flash is now no longer cacheable. Reset to WP for performance. */
mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);