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-rw-r--r--src/soc/intel/alderlake/pcie_rp.c24
-rw-r--r--src/soc/intel/cannonlake/chip.c10
-rw-r--r--src/soc/intel/common/block/include/intelblocks/pcie_rp.h6
-rw-r--r--src/soc/intel/common/block/pcie/pcie_rp.c17
-rw-r--r--src/soc/intel/elkhartlake/chip.c2
-rw-r--r--src/soc/intel/jasperlake/chip.c2
-rw-r--r--src/soc/intel/skylake/chip.c10
-rw-r--r--src/soc/intel/tigerlake/pcie_rp.c14
8 files changed, 51 insertions, 34 deletions
diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c
index f38105af71f8..119304777790 100644
--- a/src/soc/intel/alderlake/pcie_rp.c
+++ b/src/soc/intel/alderlake/pcie_rp.c
@@ -9,14 +9,14 @@
#define CPU_CPIE_VW_IDX_BASE 24
static const struct pcie_rp_group pch_lp_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group pch_m_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 2 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 2, .lcap_port_base = 1 },
{ 0 }
};
@@ -35,14 +35,14 @@ const struct pcie_rp_group *get_pch_pcie_rp_table(void)
* RP3: PEG62 : 0:6:2 : x4 CPU Slot
*/
static const struct pcie_rp_group cpu_rp_groups[] = {
- { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 },
- { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1 },
- { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1 },
+ { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 },
+ { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 1, .lcap_port_base = 1 },
+ { .slot = SA_DEV_SLOT_CPU_6, .start = 2, .count = 1, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group cpu_m_rp_groups[] = {
- { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1 },
+ { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 },
{ 0 }
};
@@ -61,8 +61,14 @@ const struct pcie_rp_group *get_cpu_pcie_rp_table(void)
return cpu_rp_groups;
}
+/*
+ * TBT's LCAP registers are returning port index which starts from 2 (Usually for other PCIe
+ * root ports index starts from 1). Thus keeping lcap_port_base 2 for TBT, so that coreboot's
+ * PCIe remapping logic can return correct index (0-based)
+ */
+
static const struct pcie_rp_group tbt_rp_groups[] = {
- { .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS},
+ { .slot = SA_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 2 },
{ 0 }
};
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 27c49b174dc2..c223211ba41a 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -18,15 +18,15 @@
#include "chip.h"
static const struct pcie_rp_group pch_lp_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group pch_h_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 },
{ 0 }
};
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index b43987d13c8c..2f3b83ce4c55 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -62,11 +62,17 @@ struct pcie_rp_config {
* in case the root port numbers are not contiguous within the slot.
* `count` is the number of functions within the group starting with the `start`
* function number.
+ * `lcap_port_base` is the starting index of physical port as described in LCAP
+ * register in PCIe config space. coreboot always uses 0 based indexing while
+ * referring to the PCIe port but LCAP registers uses 1-based indexing in
+ * most of the cases. Remapping logic needs to correctly map LCAP port number
+ * (1-based or n-based) to coreboot indexing (0-based).
*/
struct pcie_rp_group {
unsigned int slot;
unsigned int start;
unsigned int count;
+ unsigned int lcap_port_base;
};
static inline unsigned int rp_start_fn(const struct pcie_rp_group *group)
diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c
index 221ee03a9423..145159f6eb66 100644
--- a/src/soc/intel/common/block/pcie/pcie_rp.c
+++ b/src/soc/intel/common/block/pcie/pcie_rp.c
@@ -31,20 +31,25 @@ static int pcie_rp_original_idx(
}
const uint32_t lcap = pci_s_read_config32(dev, clist + PCI_EXP_LNKCAP);
- /* Read 1-based absolute port number. This reflects the numbering
- scheme that Intel uses in their documentation and what we use
- as index (0-based, though) in our mapping. */
+
+ /* Read n-based absolute port number from LCAP register.
+ This reflects the numbering scheme that Intel uses in their
+ documentation and what we use as index (0-based, though) in
+ our mapping. */
const unsigned int port_num = (lcap & PCI_EXP_LNKCAP_PORT) >> 24;
- /* `port_num` is 1-based, `offset` is 0-based. */
- if (port_num <= offset || port_num > offset + group->count) {
+ /* Subtract lcap_port_base from port_num to get 0-based index */
+ const unsigned int port_idx = port_num - group->lcap_port_base;
+
+ /* Check if port_idx (0-based) is out of bounds */
+ if (port_idx < offset || port_idx >= offset + group->count) {
printk(BIOS_WARNING, "%s: Unexpected root-port number '%u'"
" at PCI: 00:%02x.%x, ignoring.\n",
__func__, port_num, group->slot, PCI_FUNC(PCI_DEV2DEVFN(dev)));
return -1;
}
- return port_num - 1;
+ return port_idx;
}
/* Scan actual PCI config space to reconstruct current mapping */
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index 3bed78bece38..c138a1fe456a 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -17,7 +17,7 @@
#include <soc/soc_chip.h>
static const struct pcie_rp_group pch_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 7 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 7, .lcap_port_base = 1 },
{ 0 }
};
diff --git a/src/soc/intel/jasperlake/chip.c b/src/soc/intel/jasperlake/chip.c
index a8e3c8812822..7f325c4f59b1 100644
--- a/src/soc/intel/jasperlake/chip.c
+++ b/src/soc/intel/jasperlake/chip.c
@@ -17,7 +17,7 @@
#include <soc/soc_chip.h>
static const struct pcie_rp_group pch_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
{ 0 }
};
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 5c1cc6113f83..7c77a8966cf7 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -34,18 +34,18 @@
#include "chip.h"
static const struct pcie_rp_group pch_lp_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group pch_h_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
/* Sunrise Point PCH-H actually only has 4 ports in the
third group. But that would require a runtime check
and probing 4 non-existent ports shouldn't hurt. */
- { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 },
{ 0 }
};
diff --git a/src/soc/intel/tigerlake/pcie_rp.c b/src/soc/intel/tigerlake/pcie_rp.c
index f45a9c4e9696..57a5cf29dcb0 100644
--- a/src/soc/intel/tigerlake/pcie_rp.c
+++ b/src/soc/intel/tigerlake/pcie_rp.c
@@ -7,21 +7,21 @@
#define CPU_CPIE_VW_IDX_BASE 24
static const struct pcie_rp_group pch_lp_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group pch_h_rp_groups[] = {
- { .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8 },
- { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8 },
+ { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 },
+ { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 },
{ 0 }
};
static const struct pcie_rp_group cpu_rp_groups[] = {
- { .slot = SA_DEV_SLOT_PEG, .start = 0, .count = 3 },
- { .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1 },
+ { .slot = SA_DEV_SLOT_PEG, .start = 0, .count = 3, .lcap_port_base = 1 },
+ { .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1, .lcap_port_base = 1 },
{ 0 }
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 13:25:18 +0000