diff options
198 files changed, 2347 insertions, 1151 deletions
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware -Subproject 17bef2248d4547242463e27cfe48ec96029626b +Subproject 48f1bc9f52491d51ca92a1d396ccbe6a9d09e78 diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md index 7c8ce9eb522b..784f3d688845 100644 --- a/Documentation/tutorial/part2.md +++ b/Documentation/tutorial/part2.md @@ -30,7 +30,7 @@ often. Copy the content of `.ssh/id_ed25519.pub` (notice the ".pub" suffix as you need to send the public key) into the textbox "New SSH Key" at -https://review.coreboot.org/settings/#SSHKeys and save it. +<https://review.coreboot.org/settings/#SSHKeys> and save it. ## Step 2b: Set up an HTTP Password diff --git a/MAINTAINERS b/MAINTAINERS index 2963ab403baf..8ed9b4b8f09b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -130,12 +130,6 @@ F: src/mainboard/acer/ -ADLINK MAINBOARDS -S: Orphan -F: src/mainboard/adlink/ - - - AMD non-server family 17h and 19h reference boards M: Felix Held <felix-coreboot@felixheld.de> M: Jason Glenesk <jason.glenesk@gmail.com> @@ -160,14 +154,7 @@ AMD reference boards outside of family 17h and 19h S: Odd Fixes L: amd_coreboot_org_changes@googlegroups.com F: src/mainboard/amd/gardenia/ -F: src/mainboard/amd/inagua/ -F: src/mainboard/amd/olivehill/ F: src/mainboard/amd/pademelon/ -F: src/mainboard/amd/parmer/ -F: src/mainboard/amd/persimmon/ -F: src/mainboard/amd/south_station/ -F: src/mainboard/amd/thatcher/ -F: src/mainboard/amd/union_station/ @@ -199,6 +186,11 @@ M: Angel Pons <th3fanbus@gmail.com> S: Maintained F: src/mainboard/asrock/g41c-gs/ +ASROCK Z97 EXTREME6 MAINBOARD +M: Angel Pons <th3fanbus@gmail.com> +S: Maintained +F: src/mainboard/asrock/z97_extreme6/ + ASUS A88XM-E MAINBOARD @@ -235,12 +227,6 @@ F: src/mainboard/asus/p8z77-series/ -BAP MAINBOARDS -S: Orphan -F: src/mainboard/bap/ - - - BIOSTAR MAINBOARDS S: Orphan F: src/mainboard/biostar/ @@ -283,11 +269,6 @@ S: Maintained F: src/mainboard/dell/e6400/ -ELMEX MAINBOARDS -S: Orphan -F: src/mainboard/elmex/ - - EMULATION MAINBOARDS S: Orphan @@ -339,12 +320,6 @@ F: src/mainboard/gigabyte/ga-h61m-series/ -GIZMOSPHERE MAINBOARDS -S: Orphan -F: src/mainboard/gizmosphere/ - - - GOOGLE REX MAINBOARDS M: Subrata Banik <subratabanik@google.com> M: Tarun Tuli <tstuli@gmail.com> @@ -432,15 +407,13 @@ M: Vanessa Eusebio <vanessa.f.eusebio@intel.com> S: Maintained F: src/mainboard/intel/harcuvar/ + + INVENTEC MAINBOARDS M: Annie Chen <Chen.AnnieET@inventec.com> S: Maintained F: src/mainboard/inventec/ -JETWAY MAINBOARDS -S: Orphan -F: src/mainboard/jetway/ - KONTRON BSL6 MAINBOARD @@ -488,12 +461,6 @@ F: src/mainboard/libretrend/lt1000/ -LIPPERT MAINBOARDS (acquired by Adlink) -S: Orphan -F: src/mainboard/lippert/ - - - MSI H81M-P33 MAINBOARD M: Angel Pons <th3fanbus@gmail.com> S: Maintained @@ -569,13 +536,14 @@ PRODRIVE ATLAS MAINBOARD M: Angel Pons <th3fanbus@gmail.com> M: Christian Walter <christian.walter@9elements.com> M: Lean Sheng Tan <sheng.tan@9elements.com> -S: Maintained +S: Supported F: src/mainboard/prodrive/atlas/ PRODRIVE HERMES MAINBOARD +M: Angel Pons <th3fanbus@gmail.com> M: Christian Walter <christian.walter@9elements.com> M: Patrick Rudolph <patrick.rudolph@9elements.com> -S: Maintained +S: Supported F: src/mainboard/prodrive/hermes/ @@ -613,12 +581,6 @@ F: src/mainboard/sapphire/ -SCALEWAY MAINBOARDS -S: Orphan -F: src/mainboard/scaleway/ - - - SIEMENS CHILI MAINBAORD M: Felix Singer <felixsinger@posteo.net> M: Nico Huber <nico.h@gmx.de> @@ -937,7 +899,7 @@ M: Nick Vaccaro <nvaccaro@chromium.org> S: Maintained F: src/soc/intel/tigerlake/ -INTEL Xeon Sacalable Processor Family +INTEL Xeon Scalable Processor Family M: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> M: Johnny Lin <Johnny_Lin@wiwynn.com> M: Tim Chu <Tim.Chu@quantatw.com> @@ -951,6 +913,7 @@ F: src/soc/intel/xeon_sp/ F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/ F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/ F: src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/ +F: src/vendorcode/intel/fsp/fsp2_0/graniterapids/ MEDIATEK SOCS M: Hung-Te Lin <hungte@chromium.org> diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index c7c44e22313d..5899b1f14930 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -9,14 +9,14 @@ config PAYLOAD_SPECIFIC_OPTIONS config UBOOT_STABLE_COMMIT_ID string - default "v2023.07" + default "v2024.04" choice prompt "U-Boot version" default UBOOT_STABLE config UBOOT_STABLE - bool "v2023.07" + bool "v2024.04" help Stable U-Boot version diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S index 1e0e4a0d3d6b..2bac700bda3b 100644 --- a/payloads/libpayload/arch/x86/head.S +++ b/payloads/libpayload/arch/x86/head.S @@ -63,9 +63,11 @@ _init: /* No interrupts, please. */ cli +#if CONFIG(LP_MULTIBOOT) /* Store EAX and EBX */ movl %eax, loader_eax movl %ebx, loader_ebx +#endif /* save pointer to coreboot tables */ movl 4(%esp), %eax diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c index 288f474dfc78..a7c6b0141b13 100644 --- a/payloads/libpayload/arch/x86/main.c +++ b/payloads/libpayload/arch/x86/main.c @@ -30,9 +30,6 @@ #include <libpayload.h> #include <arch/apic.h> -unsigned long loader_eax; /**< The value of EAX passed from the loader */ -unsigned long loader_ebx; /**< The value of EBX passed from the loader */ - int main_argc; /**< The argc value to pass to main() */ /** The argv value to pass to main() */ diff --git a/payloads/libpayload/arch/x86/multiboot.c b/payloads/libpayload/arch/x86/multiboot.c index 26dc4f8cd089..ed7886238e24 100644 --- a/payloads/libpayload/arch/x86/multiboot.c +++ b/payloads/libpayload/arch/x86/multiboot.c @@ -30,8 +30,8 @@ #include <libpayload.h> #include <multiboot_tables.h> -extern unsigned long loader_eax; -extern unsigned long loader_ebx; +unsigned long loader_eax; /* The value of EAX passed from the loader */ +unsigned long loader_ebx; /* The value of EBX passed from the loader */ static int mb_add_memrange(struct sysinfo_t *info, unsigned long long base, unsigned long long size, unsigned int type) diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c index a23b84c39f7d..3edf0d034249 100644 --- a/src/acpi/acpigen_pci.c +++ b/src/acpi/acpigen_pci.c @@ -55,308 +55,3 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, acpigen_pop_len(); /* Package */ } - -#define PCI_HOST_BRIDGE_OSC_UUID "33db4d5b-1ff7-401c-9657-7441c03dd766" -#define CXL_HOST_BRIDGE_OSC_UUID "68f2d50b-c469-4d8a-bd3d-941a103fd3fc" - -#define OSC_RET_FAILURE 0x02 -#define OSC_RET_UNRECOGNIZED_UUID 0x04 -#define OSC_RET_UNRECOGNIZED_REV 0x08 -#define OSC_RET_CAPABILITIES_MASKED 0x10 - -#define OSC_QUERY_SUPPORT_SET 0x01 - -#define ASL_UUID_UNHANDLED 0x00 -#define ASL_UUID_HANDLED 0x01 - -static void acpigen_OSC_handle_pcie_request(const struct device *domain); -static void acpigen_OSC_handle_cxl_request(const struct device *domain); - -/* - * acpigen_write_OSC_pci_domain - * - * Reference: - * 6.2.11 in https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Device_Configuration.html - * - * _OSC ASL Arguments: (4) - * Arg0 - A Buffer containing a UUID - * Arg1 - An Integer containing a Revision ID of the buffer format - * Arg2 - An Integer containing a count of entries in Arg3 - * Arg3 - A Buffer containing a list of DWORD capabilities - * - * _OSC ASL Return Value: - * A Buffer containing a list of capabilities - * - * Local Variables Assignment: - * Local0 - Temp assigned - * Local1 - Temp assigned - * Local2 - Not used - * Local3 - Not used - * Local4 - Not used - * Local5 - Not used - * Local6 - Record whether the UUID is handled - * Local7 - Backs up the input value of Arg3 - * - * Field Definitions: - * Name - Width Source Offset Description - * -------------------------------- - * QSUP - DWord Local7 0x00 Query support - * RETE - DWord Arg3 0x00 Returned errors - * SUPP - Dword Arg3 0x04 PCIe Features that OS supported - * CTRL - Dword Arg3 0x08 PCIe Features that firmware grant control to OS - * OTRL - Dword Local7 0x08 PCIe Features that OS requests for control - * SUPC - Dword Arg3 0x0C CXL Features that OS supported - * CTRC - Dword Arg3 0x10 CXL Features that firmware grant control to OS - * OTRC - Dword Local7 0x10 CXL Features that OS requests for control - */ -void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain) -{ - /* - * Method (_OSC, 4, NotSerialized) - * { - */ - acpigen_write_method("_OSC", 4); - - /* - * // - * // Check revision ID - * // - * If (Arg1 != 1) - * { - * RETE = OSC_RET_UNRECOGNIZED_REV - * Return (Arg3) - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(ARG1_OP); - acpigen_write_integer(0x1); - - acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_REV, "RETE"); - acpigen_write_return_op(ARG3_OP); - - acpigen_write_if_end(); - - /* - * // - * // Setup up local variables - * // - * Local7 = Arg3 - * CreateDwordField (Local7, 0x00, QSUP) - * CreateDWordField (Arg3, 0x00, RETE) - * RETE = 0x0 - * Local6 = ASL_UUID_UNHANDLED - */ - acpigen_write_store_ops(ARG3_OP, LOCAL7_OP); - acpigen_write_create_dword_field(LOCAL7_OP, 0x00, "QSUP"); - acpigen_write_create_dword_field(ARG3_OP, 0x00, "RETE"); - acpigen_write_store_int_to_namestr(0x0, "RETE"); - acpigen_write_store_int_to_op(ASL_UUID_UNHANDLED, LOCAL6_OP); - - /* - * // - * // Refer to CXL-3.1-Specification, 9.18.2 - * // A CXL Host Bridge also originates a PCIe hierarchy and will have a - * // _CID of EISAID("PNP0A08"). As such, a CXL Host Bridge device may expose - * // both CXL _OSC and PCIe _OSC. - * // - * - * If (Arg0 == ToUUID (PCI_HOST_BRIDGE_OSC_UUID)) - * { - * // - * // Handle PCIe _OSC request - * // Mark UUID handled - * // - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(ARG0_OP); - acpigen_write_uuid(PCI_HOST_BRIDGE_OSC_UUID); - - acpigen_OSC_handle_pcie_request(domain); - acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); - - acpigen_write_if_end(); - - if (is_cxl_domain) { - /* - * If (Arg0 == ToUUID (CXL_HOST_BRIDGE_OSC_UUID)) - * { - * // - * // Handle CXL _OSC request - * // Mark UUID handled - * // - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(ARG0_OP); - acpigen_write_uuid(CXL_HOST_BRIDGE_OSC_UUID); - - acpigen_OSC_handle_cxl_request(domain); - acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); - - acpigen_write_if_end(); - } - - /* - * // - * // Handle unrecognized UUID - * // - * If (Local6 == ASL_UUID_UNHANDLED) - * { - * RETE = OSC_RET_UNRECOGNIZED_UUID - * } - */ - acpigen_write_if_lequal_op_int(LOCAL6_OP, ASL_UUID_UNHANDLED); - acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_UUID, "RETE"); - acpigen_write_if_end(); - - /* - * // - * // All done, return - * // - * Return (Arg3) - */ - acpigen_write_return_op(ARG3_OP); - - /* - * } // Method (_OSC, 4, NotSerialized) - */ - acpigen_pop_len(); - -} - -void acpigen_OSC_handle_pcie_request(const struct device *domain) -{ - uint32_t osc_features = soc_get_granted_pci_features(domain); - - /* - * If (Arg2 < 2)) - * { - * RETE = OSC_RET_FAILURE - * Return (Arg3) - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LLESS_OP); - acpigen_emit_byte(ARG2_OP); - acpigen_write_integer(0x2); - - acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); - acpigen_write_return_op(ARG3_OP); - - acpigen_write_if_end(); - - /* - * CreateDWordField (Arg3, 0x04, SUPP) - * CreateDWordField (Arg3, 0x08, CTRL) - * CreateDWordField (Local7, 0x08, OTRL) - */ - acpigen_write_create_dword_field(ARG3_OP, 0x04, "SUPP"); - acpigen_write_create_dword_field(ARG3_OP, 0x08, "CTRL"); - acpigen_write_create_dword_field(LOCAL7_OP, 0x08, "OTRL"); - - /* - * // Grant PCIe feature controls to OS - * CTRL &= osc_features - */ - acpigen_write_to_integer_from_namestring("CTRL", LOCAL0_OP); - acpigen_write_store_int_to_op(osc_features, LOCAL1_OP); - acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); - acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRL"); - - /* - * If (CTRL != OTRL) - * { - * RETE = OSC_RET_CAPABILITIES_MASKED - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_namestring("CTRL"); - acpigen_emit_namestring("OTRL"); - acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); - acpigen_write_if_end(); -}; - -void acpigen_OSC_handle_cxl_request(const struct device *domain) -{ - uint32_t osc_features = soc_get_granted_cxl_features(domain); - - /* - * If (Arg2 < 4)) - * { - * RETE = OSC_RET_FAILURE - * Return (Arg3) - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LLESS_OP); - acpigen_emit_byte(ARG2_OP); - acpigen_write_integer(0x4); - - acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); - acpigen_write_return_op(ARG3_OP); - - acpigen_write_if_end(); - - /* - * CreateDWordField (Arg3, 0x0C, SUPC) - * CreateDWordField (Arg3, 0x10, CTRC) - * CreateDWordField (Local7, 0x10, OTRC) - */ - acpigen_write_create_dword_field(ARG3_OP, 0x0C, "SUPC"); - acpigen_write_create_dword_field(ARG3_OP, 0x10, "CTRC"); - acpigen_write_create_dword_field(LOCAL7_OP, 0x10, "OTRC"); - - /* - * // Grant CXL feature controls to OS - * CTRC &= osc_features - */ - acpigen_write_to_integer_from_namestring("CTRC", LOCAL0_OP); - acpigen_write_store_int_to_op(osc_features, LOCAL1_OP); - acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); - acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRC"); - - /* - * If (CTRC != OTRC) - * { - * RETE = OSC_RET_CAPABILITIES_MASKED - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_namestring("CTRC"); - acpigen_emit_namestring("OTRC"); - acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); - acpigen_write_if_end(); -}; - -__weak uint32_t soc_get_granted_pci_features(const struct device *domain) -{ - /* - * By default grant no features to OS, which equals to the case where _OSC - * is absent. - * - * Refer to PCI firmware specification, revision 3.1. - * If the _OSC control method is absent from the scope of a host bridge device, then - * the operating system must not enable or attempt to use any features defined in this - * section for the hierarchy originated by the host bridge. Doing so could contend with - * platform firmware operations or produce undesired results. - */ - return 0; -} - -__weak uint32_t soc_get_granted_cxl_features(const struct device *domain) -{ - /* - * By default grant no features to OS, which equals to the case where _OSC - * is absent. - */ - return 0; -} diff --git a/src/acpi/device.c b/src/acpi/device.c index 091a0865a1c5..7313639afa81 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -51,7 +51,7 @@ int acpi_device_write_dsd_gpio(struct acpi_gpio *gpio, int *curr_index) return ret; acpi_device_write_gpio(gpio); - ret = *curr_index++; + ret = (*curr_index)++; return ret; } diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk index 2986397e51c8..897dae525f2e 100644 --- a/src/arch/arm64/Makefile.mk +++ b/src/arch/arm64/Makefile.mk @@ -173,13 +173,14 @@ BL31_MAKEARGS += IS_ANYTHING_TO_BUILD=1 BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP='"$(shell sed -n 's/^.define COREBOOT_BUILD\>.*"\(.*\)".*/\1/p' $(obj)/build.h)"' BL31_CFLAGS := -fno-pic -fno-stack-protector -Wno-deprecated-declarations -Wno-unused-function -BL31_LDFLAGS := --emit-relocs +BL31_LDFLAGS := -Wl,--emit-relocs BL31 := $(obj)/bl31.elf $(BL31): $(obj)/build.h printf " MAKE $(subst $(obj)/,,$(@))\n" - +CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ + +unset AS AR CC CPP OC OD LD; \ + CROSS_COMPILE="$(CROSS_COMPILE_arm64)" \ CFLAGS="$(BL31_CFLAGS)" \ LDFLAGS="$(BL31_LDFLAGS)" \ $(MAKE) -C $(BL31_SOURCE) $(BL31_MAKEARGS) $(BL31_TARGET) DISABLE_PEDANTIC=1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index fc7dba8a8a0c..d34c8ae700c5 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -165,6 +165,7 @@ enum timestamp_id { TS_VB_EC_VBOOT_DONE = 1030, TS_VB_STORAGE_INIT_DONE = 1040, TS_VB_READ_KERNEL_DONE = 1050, + TS_VB_AUXFW_SYNC_DONE = 1060, TS_VB_VBOOT_DONE = 1100, TS_KERNEL_START = 1101, @@ -358,6 +359,7 @@ static const struct timestamp_id_to_name { TS_NAME_DEF(TS_VB_EC_VBOOT_DONE, 0, "finished EC verification"), TS_NAME_DEF(TS_VB_STORAGE_INIT_DONE, 0, "finished storage device initialization"), TS_NAME_DEF(TS_VB_READ_KERNEL_DONE, 0, "finished reading kernel from disk"), + TS_NAME_DEF(TS_VB_AUXFW_SYNC_DONE, 0, "finished AuxFW Sync"), TS_NAME_DEF(TS_VB_VBOOT_DONE, 0, "finished vboot kernel verification"), TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"), diff --git a/src/device/device_util.c b/src/device/device_util.c index 7dcf081820d6..d91df76cee9a 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -930,3 +930,8 @@ bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus) return is_pci(pci) && pci->upstream->segment_group == 0 && pci->upstream->secondary == bus; } + +bool is_pci_bridge(const struct device *pci) +{ + return is_pci(pci) && ((pci->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE); +} diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 1fa3f4c3b2ba..09a4e7ff9fd7 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -97,7 +97,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len) * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd) +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd) { int ret; u16 crc, spd_crc; @@ -122,7 +122,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd) dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR3; dimm->dimm_type = spd[3] & 0xf; - crc = spd_ddr3_calc_crc(spd, sizeof(spd_raw_data)); + crc = spd_ddr3_calc_crc(spd, sizeof(spd_ddr3_raw_data)); /* Compare with the CRC in the SPD */ spd_crc = (spd[127] << 8) + spd[126]; /* Verify the CRC is correct */ @@ -365,7 +365,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd) memcpy(dimm->part_number, &spd[128], 16); printram(" Part number : %s\n", dimm->part_number); - memcpy(dimm->serial, &spd[SPD_DIMM_SERIAL_NUM], SPD_DIMM_SERIAL_LEN); + memcpy(dimm->serial, &spd[SPD_DDR3_SERIAL_NUM], SPD_DDR3_SERIAL_LEN); return ret; } @@ -390,7 +390,7 @@ int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd) * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was * detected. */ -int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd, +int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile) { int ret; diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c index 37bd4e2770c9..6ccef7274f88 100644 --- a/src/device/dram/ddr4.c +++ b/src/device/dram/ddr4.c @@ -70,7 +70,7 @@ const spd_block spd_blocks[] = { {.type = BLOCK_3, 384, 128, 0} }; -static bool verify_block(const spd_block *block, spd_raw_data spd) +static bool verify_block(const spd_block *block, spd_ddr4_raw_data spd) { uint16_t crc, spd_crc; @@ -136,7 +136,7 @@ uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz) * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD * SPD_STATUS_CRC_ERROR -- checksum mismatch */ -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd) +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd) { u8 reg8; u8 bus_width, sdram_width; @@ -272,25 +272,7 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 sel dimm->dimm_num = slot; memcpy(dimm->module_part_number, info->part_number, SPD_DDR4_PART_LEN); dimm->mod_id = info->manufacturer_id; - - switch (info->dimm_type) { - case SPD_DDR4_DIMM_TYPE_SO_DIMM: - dimm->mod_type = DDR4_SPD_SODIMM; - break; - case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: - dimm->mod_type = DDR4_SPD_72B_SO_RDIMM; - break; - case SPD_DDR4_DIMM_TYPE_UDIMM: - dimm->mod_type = DDR4_SPD_UDIMM; - break; - case SPD_DDR4_DIMM_TYPE_RDIMM: - dimm->mod_type = DDR4_SPD_RDIMM; - break; - default: - dimm->mod_type = SPD_UNDEFINED; - break; - } - + dimm->mod_type = info->dimm_type; dimm->bus_width = info->bus_width; memcpy(dimm->serial, info->serial_number, MIN(sizeof(dimm->serial), sizeof(info->serial_number))); diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c index 4a1e8825430c..41ec7c52c76f 100644 --- a/src/device/dram/spd.c +++ b/src/device/dram/spd.c @@ -2,6 +2,8 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> +#include <device/dram/ddr5.h> #include <device/dram/spd.h> #include <spd.h> #include <stddef.h> @@ -108,22 +110,22 @@ static void convert_ddr3_module_type_to_spd_info(enum spd_dimm_type_ddr3 module_ } } -static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type, +static void convert_ddr4_module_type_to_spd_info(enum spd_dimm_type_ddr4 module_type, struct spd_info *info) { switch (module_type) { - case DDR4_SPD_RDIMM: - case DDR4_SPD_MINI_RDIMM: + case SPD_DDR4_DIMM_TYPE_RDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR4_SPD_UDIMM: - case DDR4_SPD_MINI_UDIMM: + case SPD_DDR4_DIMM_TYPE_UDIMM: + case SPD_DDR4_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR4_SPD_SODIMM: - case DDR4_SPD_72B_SO_UDIMM: + case SPD_DDR4_DIMM_TYPE_SO_DIMM: + case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; @@ -133,26 +135,26 @@ static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_ty } } -static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type, +static void convert_ddr5_module_type_to_spd_info(enum spd_dimm_type_ddr5 module_type, struct spd_info *info) { switch (module_type) { - case DDR5_SPD_RDIMM: - case DDR5_SPD_MINI_RDIMM: + case SPD_DDR5_DIMM_TYPE_RDIMM: + case SPD_DDR5_DIMM_TYPE_MINI_RDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED; break; - case DDR5_SPD_UDIMM: - case DDR5_SPD_MINI_UDIMM: + case SPD_DDR5_DIMM_TYPE_UDIMM: + case SPD_DDR5_DIMM_TYPE_MINI_UDIMM: info->form_factor = MEMORY_FORMFACTOR_DIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED; break; - case DDR5_SPD_SODIMM: - case DDR5_SPD_72B_SO_UDIMM: + case SPD_DDR5_DIMM_TYPE_SODIMM: + case SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM: info->form_factor = MEMORY_FORMFACTOR_SODIMM; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; - case DDR5_SPD_2DPC: + case SPD_DDR5_DIMM_TYPE_2DPC: info->form_factor = MEMORY_FORMFACTOR_PROPRIETARY_CARD; info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN; break; diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 754b04af419b..9ea1526e84e3 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -55,10 +55,12 @@ if PLATFORM_USES_FSP2_0 config PLATFORM_USES_FSP2_X86_32 bool + default n if PLATFORM_USES_FSP2_4 default y help - The FSP 2.0 runs in x86_32 protected mode. - Once there's a x86_64 FSP this needs to default to n. + Specify if the FSP binaries are 32-bits (yes) or 64-bits + (no). By default, 64-bit should be used starting with FSP + specification 2.4 config HAVE_INTEL_FSP_REPO bool diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f495822e19cc..a553436166eb 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -12,7 +12,6 @@ #define FSP_HDR_ATTRIB_FSPS 3 #define FSP_IMAGE_ID_LENGTH 8 -#if CONFIG(PLATFORM_USES_FSP2_X86_32) struct fsp_header { uint32_t signature; //FSPH uint32_t header_length; @@ -40,9 +39,6 @@ struct fsp_header { uint32_t fsp_multi_phase_mem_init_entry_offset; uint32_t res5; } __packed; -#else -#error You need to implement this struct for x86_64 FSP -#endif enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 31ae21336c6a..7e9676c666a4 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,7 +34,7 @@ void __weak platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index) /* Leave for the SoC/Mainboard to implement if necessary. */ } -static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); +static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(16); /* * Helper function to store the MRC cache version into CBMEM diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index a891ba010981..41fccd6a523f 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -12,6 +12,18 @@ #define BSP_CPU_SLOT 0 +struct efi_ap_procedure_caller_params { + efi_ap_procedure procedure; + void *argument; +}; + +static void efi_ap_procedure_caller(void *arg) +{ + struct efi_ap_procedure_caller_params *params = + (struct efi_ap_procedure_caller_params *)arg; + params->procedure(params->argument); +} + efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processors, efi_uintn_t *number_of_enabled_processors) { @@ -58,14 +70,19 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number, efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure, bool run_serial, efi_uintn_t timeout_usec, void *argument) { + struct efi_ap_procedure_caller_params params = { + .procedure = procedure, + .argument = argument + }; + if (!cpu_info()) return FSP_DEVICE_ERROR; if (procedure == NULL) return FSP_INVALID_PARAMETER; - if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial) != - CB_SUCCESS) { + if (mp_run_on_all_aps((void *)efi_ap_procedure_caller, ¶ms, + timeout_usec, !run_serial) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } @@ -76,6 +93,11 @@ efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure, efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure, efi_uintn_t timeout_usec, void *argument) { + struct efi_ap_procedure_caller_params params = { + .procedure = procedure, + .argument = argument + }; + if (!cpu_info()) return FSP_DEVICE_ERROR; @@ -99,8 +121,8 @@ efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure, * due to lack of acquiring a spin lock while accessing common data structure in * multiprocessor environment. */ - if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, false) != - CB_SUCCESS) { + if (mp_run_on_all_aps((void *)efi_ap_procedure_caller, + ¶ms, timeout_usec, false) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; } @@ -111,6 +133,11 @@ efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure, efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure, efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument) { + struct efi_ap_procedure_caller_params params = { + .procedure = procedure, + .argument = argument + }; + if (!cpu_info()) return FSP_DEVICE_ERROR; @@ -123,7 +150,7 @@ efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure, if (procedure == NULL) return FSP_INVALID_PARAMETER; - if (mp_run_on_aps((void *)procedure, argument, + if (mp_run_on_aps((void *)efi_ap_procedure_caller, ¶ms, processor_number, timeout_usec) != CB_SUCCESS) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); return FSP_NOT_STARTED; diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 52d714d50394..89b8a1b2a212 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -2,6 +2,7 @@ #include <arch/null_breakpoint.h> #include <bootsplash.h> +#include <bootstate.h> #include <cbfs.h> #include <cbmem.h> #include <commonlib/fsp.h> @@ -142,9 +143,6 @@ static void do_silicon_init(struct fsp_header *hdr) timestamp_add_now(TS_FSP_SILICON_INIT_END); post_code(POSTCODE_FSP_SILICON_EXIT); - if (CONFIG(BMP_LOGO)) - bmp_release_logo(); - fsp_debug_after_silicon_init(status); fsps_return_value_handler(FSP_SILICON_INIT_API, status); @@ -261,3 +259,11 @@ void fsp_silicon_init(void) } __weak void soc_load_logo(FSPS_UPD *supd) { } + +static void release_logo(void *arg_unused) +{ + if (CONFIG(BMP_LOGO)) + bmp_release_logo(); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, release_logo, NULL); diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 92c45a8aead8..190adc7349b9 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -11,6 +11,10 @@ #include <device/pci_def.h> #include "chip.h" +#define CSI2_DATA_STREAM_INTERFACE_GUID \ + GUID_INIT(0x8A395669, 0x11F7, 0x4EA9, \ + 0x9C, 0x7D, 0x20, 0xEE, 0x0A, 0xB5, 0xCA, 0x40) + #define SENSOR_NAME_UUID "822ace8f-2814-4174-a56b-5f029fe079ee" #define SENSOR_TYPE_UUID "26257549-9271-4ca4-bb43-c4899d5a4881" #define DEFAULT_ENDPOINT 0 @@ -285,6 +289,8 @@ static void camera_fill_ssdb_defaults(struct drivers_intel_mipi_camera_config *c if (config->disable_ssdb_defaults) return; + guidcpy(&config->ssdb.csi2_data_stream_interface, &CSI2_DATA_STREAM_INTERFACE_GUID); + if (!config->ssdb.bdf_value) config->ssdb.bdf_value = PCI_DEVFN(CIO2_PCI_DEV, CIO2_PCI_FN); diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index ecf371458b6d..9aba729b3226 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -5,6 +5,7 @@ #include <stdint.h> #include <acpi/acpi_pld.h> +#include <uuid.h> #define DEFAULT_LINK_FREQ 450000000 #define MAX_PWDB_ENTRIES 12 @@ -143,7 +144,7 @@ struct operation_seq { struct intel_ssdb { uint8_t version; /* Current version */ uint8_t sensor_card_sku; /* CRD Board type */ - uint8_t csi2_data_stream_interface[16]; /* CSI2 data stream GUID */ + guid_t csi2_data_stream_interface; /* CSI2 data stream GUID */ uint16_t bdf_value; /* Bus number of the host controller */ uint32_t dphy_link_en_fuses; /* Host controller's fuses diff --git a/src/drivers/intel/pmc_mux/conn/conn.c b/src/drivers/intel/pmc_mux/conn/conn.c index c2c719991be8..4b1b08c9aa8d 100644 --- a/src/drivers/intel/pmc_mux/conn/conn.c +++ b/src/drivers/intel/pmc_mux/conn/conn.c @@ -1,9 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi_pld.h> #include <acpi/acpigen.h> #include <boot/coreboot_tables.h> #include <cbmem.h> #include <console/console.h> +#include <drivers/usb/acpi/chip.h> #include <intelblocks/acpi.h> #include "chip.h" @@ -94,12 +96,31 @@ static const char *orientation_to_str(enum type_c_orientation ori) } } +static void get_pld_from_usb_ports(struct acpi_pld *pld, + struct device *usb2_port, struct device *usb3_port) +{ + struct drivers_usb_acpi_config *config = NULL; + + if (usb3_port) + config = usb3_port->chip_info; + else if (usb2_port) + config = usb2_port->chip_info; + + if (config) { + if (config->use_custom_pld) + *pld = config->custom_pld; + else + acpi_pld_fill_usb(pld, config->type, &config->group); + } +} + static void conn_fill_ssdt(const struct device *dev) { struct drivers_intel_pmc_mux_conn_config *config = dev->chip_info; struct acpi_dp *dsd; const char *scope; const char *name; + struct acpi_pld pld = {0}; /* Reference the existing scope and write CONx device */ scope = acpi_device_scope(dev); @@ -131,6 +152,10 @@ static void conn_fill_ssdt(const struct device *dev) acpi_dp_write(dsd); + /* Copy _PLD from USB ports */ + get_pld_from_usb_ports(&pld, config->usb2_port, config->usb3_port); + acpigen_write_pld(&pld); + acpigen_pop_len(); /* CONx Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/mipi/panel-IVO_T109NW41.c b/src/drivers/mipi/panel-IVO_T109NW41.c index 21e1029e1c05..97a69d3ea303 100644 --- a/src/drivers/mipi/panel-IVO_T109NW41.c +++ b/src/drivers/mipi/panel-IVO_T109NW41.c @@ -21,14 +21,13 @@ struct panel_serializable_data IVO_T109NW41 = { .init = { PANEL_DELAY(60), PANEL_DCS(0xB9, 0x83, 0x10, 0x21, 0x55, 0x00), - PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x27, 0xE7, 0x42, 0xF5, 0x39, + PANEL_DCS(0xB1, 0x2C, 0xED, 0xED, 0x0F, 0xCF, 0x42, 0xF5, 0x39, 0x36, 0x36, 0x36, 0x36, 0x32, 0x8B, 0x11, 0x65, 0x00, 0x88, 0xFA, 0xFF, 0xFF, 0x8F, 0xFF, 0x08, 0xD6, 0x33), PANEL_DCS(0xB2, 0x00, 0x47, 0xB0, 0x80, 0x00, 0x12, 0x71, 0x3C, 0xA3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01), PANEL_DCS(0xB4, 0x35, 0x35, 0x43, 0x43, 0x35, 0x35, 0x30, 0x7A, 0x30, 0x7A, 0x01, 0x9D), - PANEL_DCS(0xB6, 0x34, 0x34, 0x03), PANEL_DCS(0xE9, 0xCD), PANEL_DCS(0xBA, 0x84), PANEL_DCS(0xE9, 0x3F), @@ -40,6 +39,9 @@ struct panel_serializable_data IVO_T109NW41 = { PANEL_DCS(0xE9, 0xCC), PANEL_DCS(0xC7, 0x80), PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xE9, 0xD3), + PANEL_DCS(0xC7, 0x22), + PANEL_DCS(0xE9, 0x3F), PANEL_DCS(0xE9, 0xC6), PANEL_DCS(0xC8, 0x97), PANEL_DCS(0xE9, 0x3F), @@ -56,19 +58,25 @@ struct panel_serializable_data IVO_T109NW41 = { 0x00, 0x02, 0x00, 0x02, 0x00, 0x00), PANEL_DCS(0xD5, 0x25, 0x24, 0x25, 0x24, 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, - 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0xA8, 0xA8, 0xA8, 0xA8, - 0x29, 0x29, 0x29, 0x29, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, + 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x1E, 0x1E, 0x1E, 0x1E, + 0x1F, 0x1F, 0x1F, 0x1F, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18), PANEL_DCS(0xD8, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + PANEL_DCS(0xE0, 0x04, 0X04, 0X06, 0X0A, 0X0A, 0X05, 0X12, 0X14, + 0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C, 0X56, 0X61, 0X78, + 0X7A, 0X41, 0X50, 0X68, 0X73, 0X04, 0X04, 0X06, 0X0A, 0X0A, + 0X05, 0X12, 0X14, 0X17, 0X13, 0X2C, 0X33, 0X39, 0X4B, 0X4C, + 0X56, 0X61, 0X78, 0X7A, 0X41, 0X50, 0X68, 0X73), PANEL_DCS(0xE7, 0x07, 0x10, 0x10, 0x1A, 0x26, 0x9E, 0x00, 0x4F, 0xA0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0A, 0x02, 0x02, 0x00, 0x33, 0x02, 0x04, 0x18, 0x01), PANEL_DCS(0xBD, 0x01), PANEL_DCS(0xB1, 0x01, 0x7F, 0x11, 0xFD), PANEL_DCS(0xCB, 0x86), + PANEL_DCS(0xD3, 0x00, 0X00, 0X04, 0X00, 0X00), PANEL_DCS(0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xA0, 0x00, 0x00, 0x00, 0x00, @@ -94,6 +102,7 @@ struct panel_serializable_data IVO_T109NW41 = { PANEL_DCS(0xE9, 0x3F), PANEL_DCS(0xE1, 0x00), PANEL_DCS(0xBD, 0x00), + PANEL_DCS(0xD2, 0xFF, 0XFF, 0XFF, 0XFF, 0XFF, 0XFF), PANEL_DCS(0xE9, 0xC4), PANEL_DCS(0xBA, 0x96), PANEL_DCS(0xE9, 0x3F), diff --git a/src/drivers/ocp/include/vpd.h b/src/drivers/ocp/include/vpd.h index 8ed6a56cee3f..bf0bc9265e2d 100644 --- a/src/drivers/ocp/include/vpd.h +++ b/src/drivers/ocp/include/vpd.h @@ -3,6 +3,8 @@ #ifndef OCP_VPD_H #define OCP_VPD_H +#include <include/types.h> + /* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */ #define FRB2_TIMER "frb2_timer_enable" #define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */ diff --git a/src/drivers/wifi/generic/Makefile.mk b/src/drivers/wifi/generic/Makefile.mk index 2231115f7630..4ccc934edb1a 100644 --- a/src/drivers/wifi/generic/Makefile.mk +++ b/src/drivers/wifi/generic/Makefile.mk @@ -20,12 +20,12 @@ wifi_sar_defaults.hex-type := raw endif -CONFIG_MTCL_CBFS_FILEPATH := $(call strip_quotes,$(CONFIG_MTCL_CBFS_FILEPATH)) +CONFIG_WIFI_MTCL_CBFS_FILEPATH := $(call strip_quotes,$(CONFIG_WIFI_MTCL_CBFS_FILEPATH)) -ifneq ($(CONFIG_MTCL_CBFS_FILEPATH),) +ifneq ($(CONFIG_WIFI_MTCL_CBFS_FILEPATH),) cbfs-files-$(CONFIG_USE_MTCL) += wifi_mtcl.bin -wifi_mtcl.bin-file := $(CONFIG_MTCL_CBFS_FILEPATH) +wifi_mtcl.bin-file := $(CONFIG_WIFI_MTCL_CBFS_FILEPATH) wifi_mtcl.bin-type := raw endif diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h index 7a07423b7bda..69216ec4fa46 100644 --- a/src/include/acpi/acpigen_pci.h +++ b/src/include/acpi/acpigen_pci.h @@ -7,13 +7,6 @@ #include <device/pci_def.h> #include <device/pci_type.h> -#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01 -#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02 -#define PCIE_PME_CONTROL 0x04 -#define PCIE_AER_CONTROL 0x08 -#define PCIE_CAP_STRUCTURE_CONTROL 0x10 -#define PCIE_LTR_CONTROL 0x20 - void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); void acpigen_write_ADR_pci_device(const struct device *dev); @@ -23,8 +16,4 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, void pci_domain_fill_ssdt(const struct device *domain); -void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain); -uint32_t soc_get_granted_pci_features(const struct device *domain); -uint32_t soc_get_granted_cxl_features(const struct device *domain); - #endif /* ACPIGEN_PCI_H */ diff --git a/src/include/device/device.h b/src/include/device/device.h index ac7e86917eff..48e539f8dcc0 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -193,6 +193,7 @@ bool is_enabled_cpu(const struct device *cpu); bool is_pci(const struct device *pci); bool is_enabled_pci(const struct device *pci); bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus); +bool is_pci_bridge(const struct device *pci); /* Returns whether there is a hotplug port on the path to the given device. */ bool dev_path_hotplug(const struct device *); diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 6efe0494dfbf..c4fd253efd5b 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -27,12 +27,12 @@ * * @{ */ -#define SPD_DIMM_MOD_ID1 117 -#define SPD_DIMM_MOD_ID2 118 -#define SPD_DIMM_SERIAL_NUM 122 -#define SPD_DIMM_SERIAL_LEN 4 -#define SPD_DIMM_PART_NUM 128 -#define SPD_DIMM_PART_LEN 18 +#define SPD_DDR3_MOD_ID1 117 +#define SPD_DDR3_MOD_ID2 118 +#define SPD_DDR3_SERIAL_NUM 122 +#define SPD_DDR3_SERIAL_LEN 4 +#define SPD_DDR3_PART_NUM 128 +#define SPD_DDR3_PART_LEN 18 /** @} */ /* Byte 3 [3:0]: DDR3 Module type information */ @@ -145,7 +145,7 @@ struct dimm_attr_ddr3_st { /* ASCII part number - NULL terminated */ u8 part_number[17]; /* Serial number */ - u8 serial[SPD_DIMM_SERIAL_LEN]; + u8 serial[SPD_DDR3_SERIAL_LEN]; }; enum ddr3_xmp_profile { @@ -153,15 +153,15 @@ enum ddr3_xmp_profile { DDR3_XMP_PROFILE_2 = 1, }; -typedef u8 spd_raw_data[256]; +typedef u8 spd_ddr3_raw_data[SPD_SIZE_MAX_DDR3]; u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd_data); int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type); void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, - spd_raw_data spd, + spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile); enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 72102125206e..da7359a253a1 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -64,9 +64,9 @@ struct dimm_attr_ddr4_st { bool ecc_extension; }; -typedef u8 spd_raw_data[512]; +typedef u8 spd_ddr4_raw_data[SPD_SIZE_MAX_DDR4]; -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd); +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd); enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index ff1604a808a4..78d18b24f8ab 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -15,6 +15,22 @@ /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR5 1024 +enum spd_dimm_type_ddr5 { + SPD_DDR5_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR5_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR5_DIMM_TYPE_SODIMM = 0x03, + SPD_DDR5_DIMM_TYPE_LRDIMM = 0x04, + SPD_DDR5_DIMM_TYPE_MINI_RDIMM = 0x05, + SPD_DDR5_DIMM_TYPE_MINI_UDIMM = 0x06, + SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM = 0x08, + SPD_DDR5_DIMM_TYPE_72B_SO_RDIMM = 0x09, + SPD_DDR5_DIMM_TYPE_SOLDERED_DOWN = 0x0b, + SPD_DDR5_DIMM_TYPE_16B_SO_DIMM = 0x0c, + SPD_DDR5_DIMM_TYPE_32B_SO_RDIMM = 0x0d, + SPD_DDR5_DIMM_TYPE_1DPC = 0x0e, + SPD_DDR5_DIMM_TYPE_2DPC = 0x0f, +}; + /** * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d3ba149afbbd..d6f8dd307804 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4128,6 +4128,7 @@ #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 +#define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5 #define PCI_DID_INTEL_RPL_HX_GT1 0xa788 #define PCI_DID_INTEL_RPL_HX_GT2 0xa78b #define PCI_DID_INTEL_RPL_HX_GT3 0x4688 diff --git a/src/include/spd.h b/src/include/spd.h index 2fe9f968d436..ff7c73ebb5c2 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -154,6 +154,13 @@ enum spd_memory_type { SPD_MEMORY_TYPE_DDR4E_SDRAM = 0x0e, SPD_MEMORY_TYPE_LPDDR3_SDRAM = 0x0f, SPD_MEMORY_TYPE_LPDDR4_SDRAM = 0x10, + SPD_MEMORY_TYPE_LPDDR4X_SDRAM = 0x11, + SPD_MEMORY_TYPE_DDR5_SDRAM = 0x12, + SPD_MEMORY_TYPE_LPDDR5_SDRAM = 0x13, + SPD_MEMORY_TYPE_DDR5_NVDIMM_P = 0x14, + SPD_MEMORY_TYPE_LPDDR5X_SDRAM = 0x15, + /* This is not a JEDEC module type ID */ + SPD_MEMORY_TYPE_LPDDR3_INTEL = 0xf1, }; /* SPD_MODULE_VOLTAGE values. */ @@ -201,36 +208,6 @@ enum spd_memory_type { #define SPD_ECC_8BIT (1<<3) #define SPD_ECC_8BIT_LP5_DDR5 (1<<4) -/* Byte 3 [3:0]: DDR4 Module type information */ -enum ddr4_module_type { - DDR4_SPD_RDIMM = 0x01, - DDR4_SPD_UDIMM = 0x02, - DDR4_SPD_SODIMM = 0x03, - DDR4_SPD_LRDIMM = 0x04, - DDR4_SPD_MINI_RDIMM = 0x05, - DDR4_SPD_MINI_UDIMM = 0x06, - DDR4_SPD_72B_SO_RDIMM = 0x08, - DDR4_SPD_72B_SO_UDIMM = 0x09, - DDR4_SPD_16B_SO_DIMM = 0x0c, - DDR4_SPD_32B_SO_RDIMM = 0x0d, -}; - -enum ddr5_module_type { - DDR5_SPD_RDIMM = 0x01, - DDR5_SPD_UDIMM = 0x02, - DDR5_SPD_SODIMM = 0x03, - DDR5_SPD_LRDIMM = 0x04, - DDR5_SPD_MINI_RDIMM = 0x05, - DDR5_SPD_MINI_UDIMM = 0x06, - DDR5_SPD_72B_SO_UDIMM = 0x08, - DDR5_SPD_72B_SO_RDIMM = 0x09, - DDR5_SPD_SOLDERED_DOWN = 0x0b, - DDR5_SPD_16B_SO_DIMM = 0x0c, - DDR5_SPD_32B_SO_RDIMM = 0x0d, - DDR5_SPD_1DPC = 0x0e, - DDR5_SPD_2DPC = 0x0f, -}; - enum lpx_module_type { LPX_SPD_LPDIMM = 0x07, LPX_SPD_NONDIMM = 0x0e, diff --git a/src/mainboard/adlink/CM2-GF/board_info.txt b/src/mainboard/adlink/CM2-GF/board_info.txt deleted file mode 100644 index 4244bfc70c80..000000000000 --- a/src/mainboard/adlink/CM2-GF/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Category: half -Board name: CoreModule2-GF -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Clone of: lippert/frontrunner-af diff --git a/src/mainboard/adlink/Kconfig b/src/mainboard/adlink/Kconfig deleted file mode 100644 index 2ff99b3ef857..000000000000 --- a/src/mainboard/adlink/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if VENDOR_ADLINK - -comment "see under vendor LiPPERT" -# any further boards will then be ADLINK - -config MAINBOARD_VENDOR - default "ADLINK" - -endif # VENDOR_ADLINK diff --git a/src/mainboard/adlink/Kconfig.name b/src/mainboard/adlink/Kconfig.name deleted file mode 100644 index 2781c4fc888a..000000000000 --- a/src/mainboard/adlink/Kconfig.name +++ /dev/null @@ -1,4 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -config VENDOR_ADLINK - bool "ADLINK" diff --git a/src/mainboard/adlink/cExpress-GFR/board_info.txt b/src/mainboard/adlink/cExpress-GFR/board_info.txt deleted file mode 100644 index 7f883dbb2cb1..000000000000 --- a/src/mainboard/adlink/cExpress-GFR/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Category: half -Board name: cExpress-GFR -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Clone of: lippert/toucan-af diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig new file mode 100644 index 000000000000..d47e3a204797 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z97_EXTREME6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT + +config CBFS_SIZE + default 0x200000 + +config MAINBOARD_DIR + default "asrock/z97_extreme6" + +config MAINBOARD_PART_NUMBER + default "Z97 Extreme6" + +endif diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig.name b/src/mainboard/asrock/z97_extreme6/Kconfig.name new file mode 100644 index 000000000000..24435876406b --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z97_EXTREME6 + bool "Z97 Extreme6" diff --git a/src/mainboard/asrock/z97_extreme6/Makefile.mk b/src/mainboard/asrock/z97_extreme6/Makefile.mk new file mode 100644 index 000000000000..513c347cbdad --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z97_extreme6/acpi/ec.asl b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl new file mode 100644 index 000000000000..16990d45f428 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z97_extreme6/acpi/platform.asl b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl new file mode 100644 index 000000000000..7da03bfddd02 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asrock/z97_extreme6/acpi/superio.asl b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl new file mode 100644 index 000000000000..ee2eabeb756e --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z97_extreme6/board_info.txt b/src/mainboard/asrock/z97_extreme6/board_info.txt new file mode 100644 index 000000000000..bd0147425432 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z97%20extreme6/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/asrock/z97_extreme6/bootblock.c b/src/mainboard/asrock/z97_extreme6/bootblock.c new file mode 100644 index 000000000000..318cc034f201 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/bootblock.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) +#define GPIO_PP_OD_DEV PNP_DEV(0x2e, NCT6791D_GPIO_PP_OD) + +/* + * Asrock Z97 Extreme6 Super I/O GPIOs + * + * +------+-----+---------------------------+ + * | GPIO | Pin | Description | + * +------+-----+---------------------------+ + * | GP00 | 121 | N/C | + * | GP01 | 122 | CHA_FAN2 PWM output | + * | GP02 | 123 | CHA_FAN3 PWM output | + * | GP03 | 2 | N/C | + * | GP04 | 3 | CHA_FAN3 tach input | + * | GP05 | 4 | CHA_FAN2 tach input | + * | GP06 | 5 | PWR_FAN tach input | + * | GP07 | 6 | N/C (SE_IFDET) | + * +------+-----+---------------------------+ + * | GP10 | 14 | HDD Saver power switch | + * | GP11 | 13 | Assert HDA_SDO (SIO_GP11) | + * | GP12 | 12 | CPU_FAN2 FON# | + * | GP13 | 11 | SATA_SEL (for eSATA) | + * | GP14 | 10 | N/C | + * | GP15 | 9 | N/C (UARTP80_EN) | + * | GP16 | 8 | OTP for VCORE (OTE_GATE1) | + * | GP17 | 7 | LED_EN# | + * +------+-----+---------------------------+ + * | GP20 | 59 | KDAT | + * | GP21 | 58 | KCLK | + * | GP22 | 57 | MDAT | + * | GP23 | 56 | MCLK | + * | GP24 | 95 | SE_DEVSLP (SATA Express) | + * | GP25 | 96 | N/C (SIO_GP25) | + * | GP26 | 53 | N/C | + * | GP27 | 98 | M2_2_SE_IFDET | + * +------+-----+---------------------------+ + * | GP30 | 83 | N/C (RESETCON#) | + * | GP31 | 76 | BIOS_A (or SML1DAT) | + * | GP32 | 75 | BIOS_B (or SML1CLK) | + * | GP33 | 71 | 3VSBSW# | + * | GP34 | 55 | VCORE_OFFSET# | + * | GP35 | 54 | N/C | + * | GP36 | 53 | N/C | + * | GP37 | 7 | LED_EN# | + * +------+-----+---------------------------+ + * | GP40 | 62 | N/C (TEST_EN) | + * | GP41 | 52 | N/C | + * | GP42 | 51 | WLAN1_ON/OFF# | + * | GP43 | 41 | Port 80 display - DGL_0# | + * | GP44 | 40 | PWR_LED gate | + * | GP45 | 39 | HDD_LED gate | + * | GP46 | 38 | CHA_FAN3 FON# | + * | GP47 | 37 | CHA_FAN2 FON# | + * +------+-----+---------------------------+ + * | GP50 | 93 | N/C (SUSWARN#) | + * | GP51 | 92 | CPU_FAN2 tach input | + * | GP52 | 91 | N/C (SUSACK#) | + * | GP53 | 90 | SUSWARN_5VDUAL | + * | GP54 | 89 | SLP_SUS# | + * | GP55 | 88 | SLP_SUS_FET | + * | GP56 | 87 | PEG12V_DET (Molex conn) | + * | GP57 | 86 | PCIE4_SEL (PCIE3 / mPCIe) | + * +------+-----+---------------------------+ + * | GP70 | 69 | N/C (DSW_EN) | + * | GP71 | 68 | N/C | + * | GP72 | 67 | N/C | + * | GP73 | 66 | M.2 / SATA Express select | + * | GP74 | 79 | RESET# of long PCIe ports | + * | GP75 | 78 | RESET# for on-board chips | + * | GP76 | 77 | RESET# SATA Express / M.2 | + * | GP77 | 86 | HDD_LED gate | + * +------+-----+---------------------------+ + * + * HWM voltage inputs + * + * +------+-----+---------------------------+ + * | Name | Pin | Voltage (resistor values) | + * +------+-----+---------------------------+ + * | VIN0 | 104 | +12V (110K / 10K) | + * | VIN1 | 105 | +5V (20K / 10K) | + * | VIN2 | 106 | CPU_VRING | + * | VIN3 | 107 | CPU_VSA | + * | VIN4 | 111 | CPU_VCORE0 | + * | VIN5 | 114 | CPU_VGFX | + * | VIN6 | 115 | V_VCCIOA_LOAD | + * | VIN7 | 116 | N/C | + * | VIN8 | 103 | CPU_VIO | + * +------+-----+---------------------------+ + */ + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0xe6); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x24, 0xfc); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x02); + + /* Select push-pull vs. open-drain output */ + pnp_set_logical_device(GPIO_PP_OD_DEV); + pnp_write_config(GPIO_PP_OD_DEV, 0xe0, 0xfe); + pnp_write_config(GPIO_PP_OD_DEV, 0xe2, 0x79); + pnp_write_config(GPIO_PP_OD_DEV, 0xe6, 0x6f); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z97_extreme6/data.vbt b/src/mainboard/asrock/z97_extreme6/data.vbt Binary files differnew file mode 100644 index 000000000000..6a73a2662626 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/data.vbt diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb new file mode 100644 index 000000000000..2258a1bfd142 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb @@ -0,0 +1,130 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + + # This mainboard has DVI-I + register "gpu_ddi_e_connected" = "1" + + # This mainboard has a DP output + register "gpu_dp_c_hotplug" = "7" + + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1849 0x0c00 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # Bifurcated PEG: PCIE2 slot + device pci 01.1 on end # Bifurcated PEG: PCIE4 slot + device pci 01.2 on end # Bifurcated PEG: M2_1 slot + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" # Super I/O HWM + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on end # Intel GbE through I218-V PHY + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: muxed M2_2 slot, SATA Express + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3: Realtek RTL8111E GbE NIC + device pci 00.0 on end + end + device pci 1c.3 on end # RP #4: ASM1184E 4-Port PCIe switch + device pci 1c.4 on end # RP #5: PCIE5 slot + device pci 1c.5 off end # RP #6 + device pci 1c.6 on end # RP #7: ASM1042A USB 3.0 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x6f + irq 0xe1 = 0x10 + end + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xbe + irq 0xf1 = 0x01 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xff + irq 0xe1 = 0x00 + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x72 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x0f + irq 0xf1 = 0x00 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0x00 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe5 = 0x12 + irq 0xed = 0x01 + irq 0xf0 = 0x30 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + end + end +end diff --git a/src/mainboard/asrock/z97_extreme6/dsdt.asl b/src/mainboard/asrock/z97_extreme6/dsdt.asl new file mode 100644 index 000000000000..17c44b652330 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads new file mode 100644 index 000000000000..cd05ae2fb817 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI1, -- DVI-I + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- DVI-I + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z97_extreme6/gpio.c b/src/mainboard/asrock/z97_extreme6/gpio.c new file mode 100644 index 000000000000..1dee18cc7e76 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c new file mode 100644 index 000000000000..7f716965f4c8 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek ALC1150 */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c new file mode 100644 index 000000000000..a344dee1a58c --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/romstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7 */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, /* ASM1074 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* USB1 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* MINI_PCIE1 */ + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Can be used if ASM1042 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* has not been installed */ +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */ + { 1, USB_OC_PIN_SKIP }, /* ASM1074 */ + { 0, USB_OC_PIN_SKIP }, /* N/A, GbE */ +}; diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 0ec52201c888..efe10d28a2f9 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -16,7 +16,7 @@ config BOARD_GOOGLE_BROX_COMMON select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID - select ENABLE_TCSS_USB_DETECTION if !CHROMEOS + select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS) select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION @@ -29,7 +29,7 @@ config BOARD_GOOGLE_BROX_COMMON select MAINBOARD_HAS_TPM2 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU -# select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -50,6 +50,7 @@ config BOARD_GOOGLE_BASEBOARD_BROX select SOC_INTEL_RAPTORLAKE select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION select DRIVERS_INTEL_ISH select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 @@ -131,9 +132,6 @@ config VARIANT_DIR config VBOOT select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 3d87bf25c8bd..edff2be8583d 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> VRALERT_L (NC) */ PAD_NC(GPP_B2, NONE), /* GPP_B3 : [NF1: PROC_GP2 NF4: ISH_GP4B NF6: USB_C_GPP_B3] ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */ PAD_NC(GPP_B4, NONE), /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */ @@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ PAD_NC(GPP_D13, NONE), /* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */ - PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D14, DN_20K), /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> SOC_ISH_UART0_RTS_L (NC) */ PAD_NC(GPP_D15, NONE), /* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> SOC_GPP_D16 (NC) */ @@ -187,7 +187,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E3 : [NF1: PROC_GP0 NF6: USB_C_GPP_E3] ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, DEEP, LEVEL, INVERT), /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> SOC_GPP_E5 (NC) */ diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c index 512d27ed4c31..3962991325f1 100644 --- a/src/mainboard/google/brox/variants/brox/fw_config.c +++ b/src/mainboard/google/brox/variants/brox/fw_config.c @@ -24,8 +24,8 @@ static const struct pad_config ish_enable_pads[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_NF(GPP_D14, DN_20K, DEEP, NF1), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2), }; diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 7b00098853aa..e9a467a35f11 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -28,6 +28,7 @@ fw_config end chip soc/intel/alderlake + register "platform_pmax" = "208" device domain 0 on device ref dtt on chip drivers/intel/dptf diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 66839d161cdb..85230be3712d 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config ACPI_FNKEY_GEN_SCANCODE + default 94 if BOARD_GOOGLE_XOL + config BOARD_GOOGLE_BRYA_COMMON def_bool n select DRIVERS_GENERIC_ALC1015 @@ -184,6 +187,7 @@ config BOARD_GOOGLE_BRYA0 config BOARD_GOOGLE_BUJIA select BOARD_GOOGLE_BASEBOARD_BRASK + select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_CRAASK @@ -407,6 +411,7 @@ config BOARD_GOOGLE_SUNDANCE config BOARD_GOOGLE_PUJJOGA select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA @@ -439,6 +444,10 @@ config BOARD_GOOGLE_REDRIX4ES select GOOGLE_DSM_PARAM_FILE_NAME if VPD select SOC_INTEL_COMMON_BLOCK_IPU +config BOARD_GOOGLE_RIVEN + select BOARD_GOOGLE_BASEBOARD_NISSA + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_SKOLAS select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_NAU8315 @@ -641,6 +650,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_QUANDISO default 0x1 if BOARD_GOOGLE_REDRIX default 0x3 if BOARD_GOOGLE_REDRIX4ES + default 0x0 if BOARD_GOOGLE_RIVEN default 0x1 if BOARD_GOOGLE_SKOLAS default 0x1 if BOARD_GOOGLE_SKOLAS4ES default 0x1 if BOARD_GOOGLE_TAEKO @@ -729,6 +739,7 @@ config MAINBOARD_PART_NUMBER default "Quandiso" if BOARD_GOOGLE_QUANDISO default "Redrix" if BOARD_GOOGLE_REDRIX default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES + default "Riven" if BOARD_GOOGLE_RIVEN default "Skolas" if BOARD_GOOGLE_SKOLAS default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES default "Sundance" if BOARD_GOOGLE_SUNDANCE @@ -792,6 +803,7 @@ config VARIANT_DIR default "quandiso" if BOARD_GOOGLE_QUANDISO default "redrix" if BOARD_GOOGLE_REDRIX default "redrix4es" if BOARD_GOOGLE_REDRIX4ES + default "riven" if BOARD_GOOGLE_RIVEN default "skolas" if BOARD_GOOGLE_SKOLAS default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES default "sundance" if BOARD_GOOGLE_SUNDANCE @@ -814,9 +826,6 @@ config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index fe8fcc942ec5..52f2c9f95cc2 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -122,6 +122,9 @@ config BOARD_GOOGLE_REDRIX config BOARD_GOOGLE_REDRIX4ES bool "-> Redrix4ES" +config BOARD_GOOGLE_RIVEN + bool "-> Riven" + config BOARD_GOOGLE_SKOLAS bool "-> Skolas" diff --git a/src/mainboard/google/brya/variants/bujia/data.vbt b/src/mainboard/google/brya/variants/bujia/data.vbt Binary files differnew file mode 100644 index 000000000000..6a06e1570d37 --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/data.vbt diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 16c44af69204..61cb50022a3c 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -349,8 +349,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end @@ -377,7 +377,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -385,7 +385,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -398,14 +398,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 49dfea867e8a..61344d7e63fe 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -297,8 +297,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end @@ -325,7 +325,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -333,7 +333,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -346,14 +346,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -365,7 +365,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -379,7 +379,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end end diff --git a/src/mainboard/google/brya/variants/pujjoga/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk new file mode 100644 index 000000000000..d38141ca2476 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c new file mode 100644 index 000000000000..cf5c9bdc0d49 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage for Sundance */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A18 : HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A20 : NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* B5 : SOC_I2C_SUB_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : SOC_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_TERM_GPO(GPP_C1, 1, UP_20K, DEEP), + /* D3 : test point */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D8 : NC */ + PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), + /* D15 : WWAN_SAR_DETECT_2_ODL */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : NC ==> SD_WAKE_N */ + PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* E20 : NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : NC */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H12 : NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_LOCK(GPP_H19, NONE, LOCK_CONFIG), + /* H21 : WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H22 : WCAM_MCLK_R ==> NC */ + PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL ==> NC */ + PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* + * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff + * requirement. WWAN_EN must be asserted before WWAN_RST_L is released + * (with min delay 0 ms), so this works as long as the pin used for + * WWAN_EN comes before the pin used for WWAN_RST_L. + */ + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +/* Pad configuration in romstage for Sundance */ +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk index eace2e443e20..c6e0a1cf1b87 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt index fa247902eeee..adec69c7168c 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt @@ -1 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt + DRAM Part Name ID to assign +H58G56BK7BX068 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL6L60GM-MGCT 2 (0010) +K3KL8L80CM-MGCT 0 (0000) +MT62F1G32D2DS-026 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt index 2499005682ab..b962c72c9cc2 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H58G56BK7BX068 +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT +MT62F1G32D2DS-026 WT:B diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb index 4f2c04a57af4..2804e168a8ee 100644 --- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb @@ -1,6 +1,376 @@ chip soc/intel/alderlake + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "PreWake" = "100" - device domain 0 on - end + register "sagv" = "SaGv_Enabled" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN + + # Configure external V1P05/Vnn/VnnSx Rails for Pujjoga + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN901C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PARA3406"" + register "generic.desc" = ""Parade Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "280" + register "generic.stop_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 24 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on end + end + end + end + end + end end diff --git a/src/mainboard/google/brya/variants/riven/include/variant/ec.h b/src/mainboard/google/brya/variants/riven/include/variant/ec.h new file mode 100644 index 000000000000..7a2a6ff8b774 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/riven/include/variant/gpio.h b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h new file mode 100644 index 000000000000..c4fe342621e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk new file mode 100644 index 000000000000..eace2e443e20 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt new file mode 100644 index 000000000000..fa247902eeee --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt new file mode 100644 index 000000000000..2499005682ab --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb new file mode 100644 index 000000000000..4f2c04a57af4 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index bd1ed7403de7..a6064d509bd4 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -9,51 +9,6 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" - # EMMC Tx CMD Delay - # Refer to EDS-Vol2-42.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" - - # EMMC TX DATA Delay 1 - # Refer to EDS-Vol2-42.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" - - # EMMC TX DATA Delay 2 - # Refer to EDS-Vol2-42.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" - - # EMMC RX CMD/DATA Delay 1 - # Refer to EDS-Vol2-42.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" - - # EMMC RX CMD/DATA Delay 2 - # Refer to EDS-Vol2-42.3.12. - # [17:16] stands for Rx Clock before Output Buffer, - # 00: Rx clock after output buffer, - # 01: Rx clock before output buffer, - # 10: Automatic selection based on working mode. - # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" - - # EMMC Rx Strobe Delay - # Refer to EDS-Vol2-42.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. - register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" - # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 168d9821d053..39478a148912 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -195,6 +195,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ diff --git a/src/mainboard/google/brya/variants/xol/memory.c b/src/mainboard/google/brya/variants/xol/memory.c index f8afa73e1459..4e294122d2c1 100644 --- a/src/mainboard/google/brya/variants/xol/memory.c +++ b/src/mainboard/google/brya/variants/xol/memory.c @@ -65,7 +65,7 @@ static const struct mb_cfg variant_memcfg = { .ect = 1, /* Early Command Training */ - .UserBd = BOARD_TYPE_MOBILE, + .UserBd = BOARD_TYPE_ULT_ULX, }; const struct mb_cfg *variant_memory_params(void) diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 80d15feb6221..e1568f50b9fb 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -25,6 +25,12 @@ chip soc/intel/alderlake # display flickering issue. register "disable_dynamic_tccold_handshake" = "true" + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + register "tcc_offset" = "6" # TCC of 94 register "platform_pmax" = "122" @@ -132,7 +138,7 @@ chip soc/intel/alderlake .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 650, - .fall_time_ns = 400, + .fall_time_ns = 200, .data_hold_time_ns = 50, }, }" diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index f3960ca654c9..1e65ddb3971a 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -101,7 +101,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 8c291ce2799c..6baaeac3db0a 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_KINGLER_COMMON def_bool BOARD_GOOGLE_KINGLER || \ BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ + BOARD_GOOGLE_SQUIRTLE || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB @@ -27,9 +28,9 @@ config BOARD_GOOGLE_STARYU_COMMON if BOARD_GOOGLE_CORSOLA_COMMON config CORSOLA_SDCARD_INIT - def_bool BOARD_GOOGLE_MAGIKARP || \ + def_bool BOARD_GOOGLE_KINGLER_COMMON || \ + BOARD_GOOGLE_MAGIKARP || \ BOARD_GOOGLE_TENTACRUEL || \ - BOARD_GOOGLE_KINGLER_COMMON || \ BOARD_GOOGLE_WUGTRIO config BOARD_SPECIFIC_OPTIONS @@ -56,6 +57,7 @@ config BOARD_SPECIFIC_OPTIONS BOARD_GOOGLE_KINGLER || \ BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ + BOARD_GOOGLE_SQUIRTLE || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_KRABBY || \ @@ -82,19 +84,20 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string + default "Chinchou" if BOARD_GOOGLE_CHINCHOU default "Kingler" if BOARD_GOOGLE_KINGLER default "Krabby" if BOARD_GOOGLE_KRABBY default "Kyogre" if BOARD_GOOGLE_KYOGRE - default "Steelix" if BOARD_GOOGLE_STEELIX - default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Magikarp" if BOARD_GOOGLE_MAGIKARP - default "Voltorb" if BOARD_GOOGLE_VOLTORB - default "Starmie" if BOARD_GOOGLE_STARMIE default "Ponyta" if BOARD_GOOGLE_PONYTA - default "Chinchou" if BOARD_GOOGLE_CHINCHOU - default "Wugtrio" if BOARD_GOOGLE_WUGTRIO default "Skitty" if BOARD_GOOGLE_SKITTY + default "Squirtle" if BOARD_GOOGLE_SQUIRTLE + default "Starmie" if BOARD_GOOGLE_STARMIE + default "Steelix" if BOARD_GOOGLE_STEELIX + default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Veluza" if BOARD_GOOGLE_VELUZA + default "Voltorb" if BOARD_GOOGLE_VOLTORB + default "Wugtrio" if BOARD_GOOGLE_WUGTRIO config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index cbe1928a6fa1..ab6a132868ea 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -8,32 +8,35 @@ config BOARD_GOOGLE_KINGLER config BOARD_GOOGLE_KYOGRE bool "-> Kyogre" +config BOARD_GOOGLE_PONYTA + bool "-> Ponyta" + +config BOARD_GOOGLE_SQUIRTLE + bool "-> Squirtle" + config BOARD_GOOGLE_STEELIX bool "-> Steelix" config BOARD_GOOGLE_VOLTORB bool "-> Voltorb" -config BOARD_GOOGLE_PONYTA - bool "-> Ponyta" - comment "Krabby" +config BOARD_GOOGLE_CHINCHOU + bool "-> Chinchou" + config BOARD_GOOGLE_KRABBY bool "-> Krabby" -config BOARD_GOOGLE_TENTACRUEL - bool "-> Tentacruel" - config BOARD_GOOGLE_MAGIKARP bool "-> Magikarp" -config BOARD_GOOGLE_CHINCHOU - bool "-> Chinchou" - config BOARD_GOOGLE_SKITTY bool "-> Skitty" +config BOARD_GOOGLE_TENTACRUEL + bool "-> Tentacruel" + config BOARD_GOOGLE_VELUZA bool "-> Veluza" diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb index 300ba7b8a78d..bb7f003c0372 100644 --- a/src/mainboard/google/corsola/devicetree.cb +++ b/src/mainboard/google/corsola/devicetree.cb @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only fw_config + field SECONDARY_USB 27 + option DISABLED 0 + option ENABLED 1 + end field AUDIO_AMP 28 29 option AMP_ALC1019 0 option AMP_ALC5645 1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index a1ba5f9356b4..1a0ab3c9171b 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -53,6 +53,11 @@ static void mainboard_init(struct device *dev) setup_usb_host(); + if (fw_config_probe(FW_CONFIG(SECONDARY_USB, ENABLED))) { + /* Change host to USB2 port0 for initialization */ + setup_usb_secondary_host(); + } + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC1019))) configure_alc1019(); diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d6200d9a4863..86aab95ab1ff 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -216,10 +216,8 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on + device ref igpu on chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD0"" @@ -233,18 +231,16 @@ chip soc/intel/cannonlake register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" device generic 0 on end end - end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub + end + device ref dptf on end + device ref thermal on end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""drallion_ish.bin"" device generic 0 on end end end - device pci 14.0 on + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -320,16 +316,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" @@ -389,8 +383,8 @@ chip soc/intel/cannonlake register "device_present_gpio_invert" = "1" device i2c 34 on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -405,59 +399,29 @@ chip soc/intel/cannonlake register "detect" = "1" device i2c 15 on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on + end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on + end + device ref pcie_rp9 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" - end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + end + device ref pcie_rp13 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref uart0 on end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 49b40b95b62b..35d312a03c88 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -89,7 +89,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 070f596d3d05..d1a9563ecf07 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -54,6 +54,19 @@ chip soc/intel/meteorlake }, }" + register "psys_pmax_watts" = "180" + + # As per doc 640982, Intel MTL-U 28W CPU supports FVM on GT and SA + # The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A + # For GT VR configuration + register "enable_fast_vmode[VR_DOMAIN_GT]" = "1" + register "cep_enable[VR_DOMAIN_IA]" = "1" + register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "216" # 54A + # For SA VR configuration + register "enable_fast_vmode[VR_DOMAIN_SA]" = "1" + register "cep_enable[VR_DOMAIN_SA]" = "1" + register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "108" # 27A + device domain 0 on device ref dtt on chip drivers/intel/dptf diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93ec7cf9ca79..fcaa73024030 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -208,21 +208,17 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""arcada_ish.bin"" device generic 0 on end end end - device pci 14.0 on + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -296,16 +292,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" @@ -319,8 +313,8 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x1" device i2c 0A on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -336,65 +330,38 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x20" device i2c 2a on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on + end + device ref sata on end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on + end + device ref uart2 on end + device ref pcie_rp10 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[9]" = "1" - end # PCI Express Port 10 - device pci 1d.2 on # PCI Express Port 11 + end + device ref pcie_rp11 on register "PcieRpSlotImplemented[10]" = "1" end - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + device ref pcie_rp13 on + # x4 lanes chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b21623555012..589ea1c3aa62 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -213,16 +213,11 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -308,16 +303,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" @@ -349,8 +342,8 @@ chip soc/intel/cannonlake register "device_present_gpio_invert" = "1" device i2c 34 on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -358,73 +351,50 @@ chip soc/intel/cannonlake register "detect" = "1" device i2c 2c on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on + end + device ref sata on end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 on # PCI Express Port 1 (USB) + end + device ref uart2 on end + device ref pcie_rp1 on + # USB register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 + device ref pcie_rp8 on register "PcieRpSlotImplemented[7]" = "1" end - device pci 1d.0 on + device ref pcie_rp9 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" - end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 + end + device ref pcie_rp10 on register "PcieRpSlotImplemented[9]" = "1" end - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + device ref pcie_rp13 on + # x4 lanes chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + end + device ref hda on end + device ref smbus on end + device ref gbe on end end end diff --git a/src/mainboard/hp/280_g2/gma-mainboard.ads b/src/mainboard/hp/280_g2/gma-mainboard.ads index 735fe2684c41..062821114240 100644 --- a/src/mainboard/hp/280_g2/gma-mainboard.ads +++ b/src/mainboard/hp/280_g2/gma-mainboard.ads @@ -9,7 +9,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (HDMI3, -- DVI-I + (HDMI3, -- DVI-D eDP, -- VGA others => Disabled); diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 1083ce2b9c41..5ee091bc8be5 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -135,9 +135,6 @@ config DEVICETREE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config DIMM_SPD_SIZE - default 512 - choice prompt "ON BOARD EC" default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC diff --git a/src/mainboard/intel/archercity_crb/Makefile.mk b/src/mainboard/intel/archercity_crb/Makefile.mk index 4c7a7beee194..b28d73c27a74 100644 --- a/src/mainboard/intel/archercity_crb/Makefile.mk +++ b/src/mainboard/intel/archercity_crb/Makefile.mk @@ -2,5 +2,7 @@ bootblock-y += bootblock.c romstage-y += romstage.c +romstage-y += util.c ramstage-y += ramstage.c +ramstage-y += util.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c index 6e4bd8e11ef9..ff56f5936efd 100644 --- a/src/mainboard/intel/archercity_crb/romstage.c +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -35,17 +35,23 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; - - /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", - FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* Setup FSP log */ + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } } + /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; /* Enable - Portions of memory reference code will be skipped diff --git a/src/mainboard/intel/archercity_crb/util.c b/src/mainboard/intel/archercity_crb/util.c new file mode 100644 index 000000000000..5197b2329287 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/util.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/ocp/include/vpd.h> +#include <soc/chip_common.h> +#include <soc/util.h> + +#if CONFIG(SOC_INTEL_HAS_CXL) +enum xeonsp_cxl_mode get_cxl_mode(void) +{ + int ocp_cxl_mode = get_cxl_mode_from_vpd(); + switch (ocp_cxl_mode) { + case CXL_SYSTEM_MEMORY: + return XEONSP_CXL_SYS_MEM; + case CXL_SPM: + return XEONSP_CXL_SP_MEM; + default: + return XEONSP_CXL_DISABLED; + } +} +#endif diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 3d8321793c7a..59ce66c8d72d 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock( { Device (PCI0) { - #include <soc/intel/xeon_sp/acpi/southcluster.asl> + #include <soc/intel/xeon_sp/acpi/gen1/southcluster.asl> #include <soc/intel/common/block/acpi/acpi/lpc.asl> } diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 36842b577a3a..bbff4aa7c564 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -79,7 +79,9 @@ config GBB_HWID config MAINBOARD_PART_NUMBER string - default "mtlrvp" + default "Mtlrvp_P_Ext_Ec" if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP4ES_P_EXT_EC + default "Mtlrvp_P_Mchp" if BOARD_INTEL_MTLRVP_P_MCHP + default "Mtlrvp" if BOARD_INTEL_MTLRVP_P config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 17c0014b4bc3..f01479bcaa39 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -42,9 +42,6 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select VBOOT_EARLY_EC_SYNC -config DIMM_SPD_SIZE - default 512 - config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/inventec/transformers/Makefile.mk b/src/mainboard/inventec/transformers/Makefile.mk index ecb6ef2217fc..eb859d3d6962 100644 --- a/src/mainboard/inventec/transformers/Makefile.mk +++ b/src/mainboard/inventec/transformers/Makefile.mk @@ -2,5 +2,7 @@ bootblock-y += bootblock.c romstage-y += romstage.c +romstage-y += util.c romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c +ramstage-y += util.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c index 9299c7dc041c..1abcf708a9b6 100644 --- a/src/mainboard/inventec/transformers/romstage.c +++ b/src/mainboard/inventec/transformers/romstage.c @@ -98,22 +98,28 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; - /* Since it's the first IPMI command, it's better to run get BMC selftest result first */ if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { init_frb2_wdt(); } - /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* Setup FSP log */ + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } } + /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; /* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on warm boots */ diff --git a/src/mainboard/inventec/transformers/util.c b/src/mainboard/inventec/transformers/util.c new file mode 100644 index 000000000000..5197b2329287 --- /dev/null +++ b/src/mainboard/inventec/transformers/util.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/ocp/include/vpd.h> +#include <soc/chip_common.h> +#include <soc/util.h> + +#if CONFIG(SOC_INTEL_HAS_CXL) +enum xeonsp_cxl_mode get_cxl_mode(void) +{ + int ocp_cxl_mode = get_cxl_mode_from_vpd(); + switch (ocp_cxl_mode) { + case CXL_SYSTEM_MEMORY: + return XEONSP_CXL_SYS_MEM; + case CXL_SPM: + return XEONSP_CXL_SP_MEM; + default: + return XEONSP_CXL_DISABLED; + } +} +#endif diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ead7e0bb871f..a4fbe11ee811 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -12,7 +12,14 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21dd inherit diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index d4b31afe88b7..d469da6b7904 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21ce inherit diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index fb309170fe75..4ce90772a50b 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21d2 inherit diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a2e12c34d7f8..5edb63e95d35 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,6 +15,14 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig index 3fb6f40f5202..ab9fa2b4a8e2 100644 --- a/src/mainboard/msi/ms7d25/Kconfig +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -41,9 +41,6 @@ config MAINBOARD_VERSION string default "2.0" if BOARD_MSI_Z690_A_PRO_WIFI_DDR5 -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig index c46effc9caa9..cfa644798d58 100644 --- a/src/mainboard/msi/ms7e06/Kconfig +++ b/src/mainboard/msi/ms7e06/Kconfig @@ -34,9 +34,6 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY default "Default string" -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE default 0 diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index c1e8beef6982..844231991a93 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -20,11 +20,11 @@ DefinitionBlock( #include <cpu/intel/common/acpi/cpu.asl> // CPX-SP ACPI tables - #include <soc/intel/xeon_sp/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl> // LPC related entries Scope (\_SB.PC00) { - #include <soc/intel/xeon_sp/acpi/pch.asl> + #include <soc/intel/xeon_sp/acpi/gen1/pch.asl> } } diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 06145c4d6dfa..49f20f1e6df9 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,9 +15,9 @@ DefinitionBlock( #include "acpi/platform.asl" #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> - #include <soc/intel/xeon_sp/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl> Scope (\_SB.PC00) { - #include <soc/intel/xeon_sp/acpi/pch.asl> + #include <soc/intel/xeon_sp/acpi/gen1/pch.asl> } } diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index 5a3f3118d3c0..b40e2b796b3b 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -47,9 +47,6 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "Prodrive Technologies B.V." -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/raptor-cs/Kconfig b/src/mainboard/raptor-cs/Kconfig new file mode 100644 index 000000000000..3e9f7ade627b --- /dev/null +++ b/src/mainboard/raptor-cs/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_RAPTOR_CS + +choice + prompt "Mainboard model" + +source "src/mainboard/raptor-cs/*/Kconfig.name" + +endchoice + +source "src/mainboard/raptor-cs/*/Kconfig" + +config MAINBOARD_VENDOR + default "Raptor Computing Systems" + +endif # VENDOR_RAPTOR_CS diff --git a/src/mainboard/raptor-cs/Kconfig.name b/src/mainboard/raptor-cs/Kconfig.name new file mode 100644 index 000000000000..d1731095dd1d --- /dev/null +++ b/src/mainboard/raptor-cs/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_RAPTOR_CS + bool "Raptor Computing Systems" diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig new file mode 100644 index 000000000000..46513945e082 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_RAPTOR_CS_TALOS_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_POWER9 + select SOC_IBM_POWER9 + select BOARD_ROMSIZE_KB_512 + select SUPERIO_ASPEED_AST2400 + select BOOT_DEVICE_NOT_SPI_FLASH + select MISSING_BOARD_RESET + select HAVE_DEBUG_RAM_SETUP + +config MEMLAYOUT_LD_FILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" + +config MAINBOARD_DIR + default "raptor-cs/talos-2" + +config MAINBOARD_PART_NUMBER + default "Talos II" + +config DIMM_MAX + default 8 + +config DIMM_SPD_SIZE + default 512 + +config MAX_CPUS + default 1 + +config DRAM_SIZE_MB + int + default 32768 + +endif # BOARD_RAPTOR_CS_TALOS_2 diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig.name b/src/mainboard/raptor-cs/talos-2/Kconfig.name new file mode 100644 index 000000000000..8e4549af11e9 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_RAPTOR_CS_TALOS_2 + bool "Talos II" diff --git a/src/mainboard/raptor-cs/talos-2/board_info.txt b/src/mainboard/raptor-cs/talos-2/board_info.txt new file mode 100644 index 000000000000..aa2269185bec --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/board_info.txt @@ -0,0 +1,2 @@ +Board name: Raptor CS Talos II +Category: desktop diff --git a/src/mainboard/raptor-cs/talos-2/devicetree.cb b/src/mainboard/raptor-cs/talos-2/devicetree.cb new file mode 100644 index 000000000000..85440064fa47 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/ibm/power9 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/raptor-cs/talos-2/mainboard.c b/src/mainboard/raptor-cs/talos-2/mainboard.c new file mode 100644 index 000000000000..ef2dbd51bc20 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> + +static void mainboard_enable(struct device *dev) +{ + if (!dev) + die("No dev0; die\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld new file mode 100644 index 000000000000..c5136b9d14ec --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +// TODO: fill in these blanks for Power9. +SECTIONS +{ + DRAM_START(0x0) + BOOTBLOCK(0, 64K) + ROMSTAGE(0x120000, 128K) + STACK(0x140000, 0x3ff00) + PRERAM_CBMEM_CONSOLE(0x180000, 8K) + FMAP_CACHE(0x182000, 2K) + CBFS_MCACHE(0x182800, 8K) + RAMSTAGE(0x200000, 16M) +} diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index a8efd67da447..0bf0b306dae9 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -102,7 +102,7 @@ chip northbridge/intel/sandybridge end device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/system76/addw1/cmos.layout b/src/mainboard/system76/addw1/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/addw1/cmos.layout +++ b/src/mainboard/system76/addw1/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 5213cfeaac84..3d364f14828d 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -103,9 +103,6 @@ config CONSOLE_POST config D3COLD_SUPPORT default n -config DIMM_SPD_SIZE - default 512 - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/system76/adl/cmos.layout b/src/mainboard/system76/adl/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/adl/cmos.layout +++ b/src/mainboard/system76/adl/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/bonw14/cmos.layout b/src/mainboard/system76/bonw14/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/bonw14/cmos.layout +++ b/src/mainboard/system76/bonw14/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/cml-u/cmos.layout b/src/mainboard/system76/cml-u/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/cml-u/cmos.layout +++ b/src/mainboard/system76/cml-u/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/gaze15/cmos.layout b/src/mainboard/system76/gaze15/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/gaze15/cmos.layout +++ b/src/mainboard/system76/gaze15/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/kbl-u/cmos.layout b/src/mainboard/system76/kbl-u/cmos.layout index 4e9a300ebf3a..7aec087ea39f 100644 --- a/src/mainboard/system76/kbl-u/cmos.layout +++ b/src/mainboard/system76/kbl-u/cmos.layout @@ -12,7 +12,10 @@ entries 400 8 r 0 century 412 4 e 6 debug_level -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -32,4 +35,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/oryp5/cmos.layout b/src/mainboard/system76/oryp5/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/oryp5/cmos.layout +++ b/src/mainboard/system76/oryp5/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/oryp6/cmos.layout b/src/mainboard/system76/oryp6/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/oryp6/cmos.layout +++ b/src/mainboard/system76/oryp6/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index 2a850ae0894d..60ea71b6bbff 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -125,9 +125,6 @@ config CONSOLE_POST config D3COLD_SUPPORT default n -config DIMM_SPD_SIZE - default 512 - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" diff --git a/src/mainboard/system76/rpl/cmos.layout b/src/mainboard/system76/rpl/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/rpl/cmos.layout +++ b/src/mainboard/system76/rpl/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/tgl-h/cmos.layout b/src/mainboard/system76/tgl-h/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/tgl-h/cmos.layout +++ b/src/mainboard/system76/tgl-h/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/tgl-u/cmos.layout b/src/mainboard/system76/tgl-u/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/tgl-u/cmos.layout +++ b/src/mainboard/system76/tgl-u/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/whl-u/cmos.layout b/src/mainboard/system76/whl-u/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/whl-u/cmos.layout +++ b/src/mainboard/system76/whl-u/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/northbridge/intel/gm45/raminit_meminfo.c b/src/northbridge/intel/gm45/raminit_meminfo.c index c2c7f510d8ab..9fd4065ffc60 100644 --- a/src/northbridge/intel/gm45/raminit_meminfo.c +++ b/src/northbridge/intel/gm45/raminit_meminfo.c @@ -24,14 +24,14 @@ static u8 get_dimm_mod_type(const sysinfo_t *sysinfo, const int idx) static void ddr3_read_ids(const sysinfo_t *sysinfo, struct dimm_info *dimm, const int idx) { const u8 addr = sysinfo->spd_map[idx]; - for (int k = 0; k < SPD_DIMM_SERIAL_LEN; k++) { - dimm->serial[k] = smbus_read_byte(addr, SPD_DIMM_SERIAL_NUM + k); + for (int k = 0; k < SPD_DDR3_SERIAL_LEN; k++) { + dimm->serial[k] = smbus_read_byte(addr, SPD_DDR3_SERIAL_NUM + k); } - for (int k = 0; k < SPD_DIMM_PART_LEN; k++) { - dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DIMM_PART_NUM + k); + for (int k = 0; k < SPD_DDR3_PART_LEN; k++) { + dimm->module_part_number[k] = smbus_read_byte(addr, SPD_DDR3_PART_NUM + k); } - dimm->mod_id = (smbus_read_byte(addr, SPD_DIMM_MOD_ID2) << 8) | - (smbus_read_byte(addr, SPD_DIMM_MOD_ID1) << 0); + dimm->mod_id = (smbus_read_byte(addr, SPD_DDR3_MOD_ID2) << 8) | + (smbus_read_byte(addr, SPD_DDR3_MOD_ID1) << 0); } static u32 get_mem_clock_mt(const int clock_index) diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c index e7e9b634c83d..7af21f578af2 100644 --- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c @@ -219,14 +219,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = slot; dimm->bank_locator = ch * 2; memcpy(dimm->serial, - &pei_data->spd_data[ch][slot][SPD_DIMM_SERIAL_NUM], - SPD_DIMM_SERIAL_LEN); + &pei_data->spd_data[ch][slot][SPD_DDR3_SERIAL_NUM], + SPD_DDR3_SERIAL_LEN); memcpy(dimm->module_part_number, - &pei_data->spd_data[ch][slot][SPD_DIMM_PART_NUM], - SPD_DIMM_PART_LEN); + &pei_data->spd_data[ch][slot][SPD_DDR3_PART_NUM], + SPD_DDR3_PART_LEN); dimm->mod_id = - (pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[ch][slot][SPD_DIMM_MOD_ID1] & 0xff); + (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID2] << 8) | + (pei_data->spd_data[ch][slot][SPD_DDR3_MOD_ID1] & 0xff); dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c index 7109e46da0d1..d97ab2a8acd3 100644 --- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c +++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c @@ -252,14 +252,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = d_num; dimm->bank_locator = ch * 2; memcpy(dimm->serial, - &pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM], - SPD_DIMM_SERIAL_LEN); + &pei_data->spd_data[index][SPD_DDR3_SERIAL_NUM], + SPD_DDR3_SERIAL_LEN); memcpy(dimm->module_part_number, - &pei_data->spd_data[index][SPD_DIMM_PART_NUM], - SPD_DIMM_PART_LEN); + &pei_data->spd_data[index][SPD_DDR3_PART_NUM], + SPD_DDR3_PART_LEN); dimm->mod_id = - (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff); + (pei_data->spd_data[index][SPD_DDR3_MOD_ID2] << 8) | + (pei_data->spd_data[index][SPD_DDR3_MOD_ID1] & 0xff); dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h index 1a0793947e0f..2a168666ac86 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h @@ -33,7 +33,7 @@ enum generic_stepping { }; struct raminit_dimm_info { - spd_raw_data raw_spd; + spd_ddr3_raw_data raw_spd; struct dimm_attr_ddr3_st data; uint8_t spd_addr; bool valid; diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2b59b9e6afb2..8a8bd8310b55 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -123,7 +123,7 @@ static void setup_sdram_meminfo(ramctr_timing *ctrl) } /* Return CRC16 match for all SPDs */ -static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +static int verify_crc16_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) { int channel, slot, spd_slot; int match = 1; @@ -132,17 +132,17 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; match &= ctrl->spd_crc[channel][slot] == - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data)); } } return match; } -static void read_spd(spd_raw_data *spd, u8 addr, bool id_only) +static void read_spd(spd_ddr3_raw_data *spd, u8 addr, bool id_only) { int j; if (id_only) { - for (j = SPD_DIMM_MOD_ID1; j < 128; j++) + for (j = SPD_DDR3_MOD_ID1; j < 128; j++) (*spd)[j] = smbus_read_byte(addr, j); } else { for (j = 0; j < SPD_SIZE_MAX_DDR3; j++) @@ -150,7 +150,7 @@ static void read_spd(spd_raw_data *spd, u8 addr, bool id_only) } } -static void mainboard_get_spd(spd_raw_data *spd, bool id_only) +static void mainboard_get_spd(spd_ddr3_raw_data *spd, bool id_only) { const struct northbridge_intel_sandybridge_config *cfg = config_of_soc(); unsigned int i; @@ -192,7 +192,7 @@ static void mainboard_get_spd(spd_raw_data *spd, bool id_only) } /* CONFIG(HAVE_SPD_IN_CBFS) */ } -static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) +static void dram_find_spds_ddr3(spd_ddr3_raw_data *spd, ramctr_timing *ctrl) { int dimms = 0, ch_dimms; int channel, slot, spd_slot; @@ -254,7 +254,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) /* Fill in CRC16 for MRC cache */ ctrl->spd_crc[channel][slot] = - spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); + spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_ddr3_raw_data)); if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { /* Mark DIMM as invalid */ @@ -339,7 +339,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; ramctr_timing ctrl; - spd_raw_data spds[4]; + spd_ddr3_raw_data spds[4]; size_t mrc_size; ramctr_timing *ctrl_cached = NULL; diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index cad86ba51e71..8d3c4023c879 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -467,14 +467,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 0; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], - sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); + &pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM], + sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][SPD_DIMM_PART_NUM], - sizeof(uint8_t) * SPD_DIMM_PART_LEN); + &pei_data->spd_data[0][SPD_DDR3_PART_NUM], + sizeof(uint8_t) * SPD_DDR3_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); + (pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF); dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; @@ -491,14 +491,14 @@ static void setup_sdram_meminfo(struct pei_data *pei_data) dimm->dimm_num = 1; dimm->bank_locator = i * 2; memcpy(dimm->serial, /* bytes 122-125 */ - &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], - sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); + &pei_data->spd_data[0][SPD_DDR3_SERIAL_NUM], + sizeof(uint8_t) * SPD_DDR3_SERIAL_LEN); memcpy(dimm->module_part_number, /* bytes 128-145 */ - &pei_data->spd_data[0][SPD_DIMM_PART_NUM], - sizeof(uint8_t) * SPD_DIMM_PART_LEN); + &pei_data->spd_data[0][SPD_DDR3_PART_NUM], + sizeof(uint8_t) * SPD_DDR3_PART_LEN); dimm->mod_id = /* bytes 117/118 */ - (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); + (pei_data->spd_data[0][SPD_DDR3_MOD_ID2] << 8) | + (pei_data->spd_data[0][SPD_DDR3_MOD_ID1] & 0xFF); dimm->mod_type = SPD_DDR3_DIMM_TYPE_SO_DIMM; dimm->bus_width = MEMORY_BUS_WIDTH_64; dimm_cnt++; diff --git a/src/soc/amd/phoenix/include/soc/platform_descriptors.h b/src/soc/amd/phoenix/include/soc/platform_descriptors.h index de1801271792..642c2bd01ff2 100644 --- a/src/soc/amd/phoenix/include/soc/platform_descriptors.h +++ b/src/soc/amd/phoenix/include/soc/platform_descriptors.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #ifndef AMD_PHOENIX_PLATFORM_DESCRIPTORS_H #define AMD_PHOENIX_PLATFORM_DESCRIPTORS_H diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig new file mode 100644 index 000000000000..9f3323b63b94 --- /dev/null +++ b/src/soc/ibm/power9/Kconfig @@ -0,0 +1,14 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config SOC_IBM_POWER9 + bool + select ARCH_BOOTBLOCK_PPC64 + select ARCH_VERSTAGE_PPC64 + select ARCH_ROMSTAGE_PPC64 + select ARCH_RAMSTAGE_PPC64 + help + This SoC is the minimal template working on POWER9 Talos II platform. + +if SOC_IBM_POWER9 + # nothing here yet +endif diff --git a/src/soc/ibm/power9/Makefile.mk b/src/soc/ibm/power9/Makefile.mk new file mode 100644 index 000000000000..84a40f9a34aa --- /dev/null +++ b/src/soc/ibm/power9/Makefile.mk @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_IBM_POWER9),y) + +bootblock-y += bootblock.c +bootblock-y += rom_media.c + +romstage-y += cbmem.c +romstage-y += rom_media.c +romstage-y += romstage.c + +ramstage-y += cbmem.c +ramstage-y += chip.c +ramstage-y += rom_media.c +ramstage-y += timer.c + +endif diff --git a/src/soc/ibm/power9/bootblock.c b/src/soc/ibm/power9/bootblock.c new file mode 100644 index 000000000000..86217285b9ac --- /dev/null +++ b/src/soc/ibm/power9/bootblock.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +void bootblock_soc_early_init(void) +{ +} diff --git a/src/soc/ibm/power9/cbmem.c b/src/soc/ibm/power9/cbmem.c new file mode 100644 index 000000000000..9543c4584809 --- /dev/null +++ b/src/soc/ibm/power9/cbmem.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> + +uintptr_t cbmem_top_chipset(void) +{ + /* + * Smallest reported to be working (but not officially supported) DIMM is + * 4GB. This means that we always have at least as much available. Last + * 256MB are reserved for hostboot/coreboot (OCC and HOMER images). + * + * TODO: implement this properly after RAM is detected. + */ + return 4ull * GiB - 256 * MiB; +} diff --git a/src/soc/ibm/power9/chip.c b/src/soc/ibm/power9/chip.c new file mode 100644 index 000000000000..f93c21600a3f --- /dev/null +++ b/src/soc/ibm/power9/chip.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <device/device.h> + +static void enable_soc_dev(struct device *dev) +{ + ram_range(dev, 0, 0, cbmem_top_chipset()); + /* This is for OCC and HOMER images */ + reserved_ram_range(dev, 1, cbmem_top_chipset(), 256 * MiB); +} + +struct chip_operations soc_ibm_power9_ops = { + .name = "POWER9", + .enable_dev = enable_soc_dev, +}; diff --git a/src/soc/ibm/power9/rom_media.c b/src/soc/ibm/power9/rom_media.c new file mode 100644 index 000000000000..c07af1bbf0b6 --- /dev/null +++ b/src/soc/ibm/power9/rom_media.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boot_device.h> + +const struct region_device *boot_device_ro(void) +{ + return NULL; +} diff --git a/src/soc/ibm/power9/romstage.c b/src/soc/ibm/power9/romstage.c new file mode 100644 index 000000000000..4a3ed8304c9a --- /dev/null +++ b/src/soc/ibm/power9/romstage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <console/console.h> +#include <program_loading.h> + +void main(void) +{ + console_init(); + cbmem_initialize_empty(); + run_ramstage(); +} diff --git a/src/soc/ibm/power9/timer.c b/src/soc/ibm/power9/timer.c new file mode 100644 index 000000000000..9a283e3f7612 --- /dev/null +++ b/src/soc/ibm/power9/timer.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> + +void init_timer(void) +{ + /* No need to do anything here as long as udelay() is implemented via monolitic timer */ +} diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 508606961a22..e0afe5aeb7b6 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -82,7 +82,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON + select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION @@ -146,6 +146,9 @@ config SOC_INTEL_RAPTORLAKE_PCH_S if SOC_INTEL_ALDERLAKE +config DIMM_SPD_SIZE + default 512 + config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT bool default n if SOC_INTEL_ALDERLAKE_PCH_S diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index b64364bed81c..6244072c55cf 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -59,7 +59,7 @@ static void populate_smbios_tables(void *dram_data, int speed, int num_channels) enum spd_status status; /* Decode into dimm_attr struct */ - status = spd_decode_ddr3(&dimm, *(spd_raw_data *)dram_data); + status = spd_decode_ddr3(&dimm, *(spd_ddr3_raw_data *)dram_data); /* Some SPDs have bad CRCs, nothing we can do about it */ if (status == SPD_STATUS_OK || status == SPD_STATUS_CRC_ERROR) { diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 7548e46b364a..3aa06f43d864 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -64,7 +64,7 @@ config SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 9cad4ffaebd8..a58c4f01f4e2 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -255,10 +255,9 @@ int soc_madt_sci_irq_polarity(int sci) static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; - const bool emit_igd = igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten; + const bool emit_igd = is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten; if (emit_igd) { unsigned long tmp = current; @@ -268,11 +267,10 @@ static unsigned long soc_fill_dmar(unsigned long current) acpi_dmar_drhd_fixup(tmp, current); } - struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; - if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { + if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) { unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 737e7c399d1e..2b25285ffa6c 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -32,8 +32,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) * Probe for no IGD and disable InternalGfx and panel power to prevent a * crash in FSP-M. */ - dev = pcidev_path_on_root(SA_DEVFN_IGD); - const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; + const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD); if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { /* Set IGD stolen size to 64MB. */ m_cfg->InternalGfx = 1; @@ -90,25 +89,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } - dev = pcidev_path_on_root(PCH_DEVFN_ISH); - /* If ISH is enabled, enable ISH elements */ - if (!dev) - m_cfg->PchIshEnable = 0; - else - m_cfg->PchIshEnable = dev->enabled; + m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH); - /* If HDA is enabled, enable HDA elements */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); - if (!dev) - m_cfg->PchHdaEnable = 0; - else - m_cfg->PchHdaEnable = dev->enabled; + m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); - /* Enable IPU only if the device is enabled */ - m_cfg->SaIpuEnable = 0; - dev = pcidev_path_on_root(SA_DEVFN_IPU); - if (dev) - m_cfg->SaIpuEnable = dev->enabled; + m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU); /* SATA Gen3 strength */ for (i = 0; i < SOC_INTEL_CML_SATA_DEV_MAX; i++) { @@ -136,12 +121,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) tconfig->DisableHeciRetry = config->DisableHeciRetry; #endif - /* Enable SMBus controller based on config */ - dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); - if (!dev) - m_cfg->SmbusEnable = 0; - else - m_cfg->SmbusEnable = dev->enabled; + m_cfg->SmbusEnable = is_devfn_enabled(PCH_DEVFN_SMBUS); /* Set debug probe type */ m_cfg->PlatformDebugConsent = diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index e9cfc230a409..a7762711fa76 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -75,18 +75,28 @@ static uint32_t fast_spi_flash_read_sfdp(struct fast_spi_flash_ctx *ctx, /* Fill FDATAn FIFO in preparation for a write transaction. */ static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const void *data, - size_t len) + size_t len) { - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); + const uint32_t *data32 = (const uint32_t *)data; + for (size_t i = 0; i < len / sizeof(uint32_t); i++) + write32p(ctx->mmio_base + SPIBAR_FDATA(i), *data32++); + + const uint8_t *data8 = (const uint8_t *)data32; + for (size_t i = 0; i < len % sizeof(uint32_t); i++) + write8p(ctx->mmio_base + SPIBAR_FDATA(len / sizeof(uint32_t)) + i, *data8++); } /* Drain FDATAn FIFO after a read transaction populates data. */ -static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *dest, +static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *data, size_t len) { - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len); + uint32_t *data32 = (uint32_t *)data; + for (size_t i = 0; i < len / sizeof(uint32_t); i++) + *data32++ = read32p(ctx->mmio_base + SPIBAR_FDATA(i)); + + uint8_t *data8 = (uint8_t *)data32; + for (size_t i = 0; i < len % sizeof(uint32_t); i++) + *data8++ = read8p(ctx->mmio_base + SPIBAR_FDATA(len / sizeof(uint32_t)) + i); } /* Fire up a transfer using the hardware sequencer. */ diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index b5776b049fa4..eaa429ed393e 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -8,10 +8,20 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS if SOC_INTEL_COMMON_BLOCK_GRAPHICS -config SOC_INTEL_CONFIGURE_DDI_A_4_LANES +config SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION bool help - Selected by platforms that require DDI-A bifurcation setup. + Skylake, Kaby Lake and Coffee Lake desktop CPUs support eDP + bifurcation, i.e. 4 eDP lanes get split between DDI-A (eDP) + and DDI-E (DP, used for VGA). Selected from SoC Kconfig, if + applicable. + +config SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION + bool + depends on SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION + help + Selected by mainboards that use DDI-E, which is most commonly + used to drive a DP-to-VGA adapter to provide a VGA connector. config SOC_INTEL_DISABLE_IGD bool "Disable Integrated GFX Controller (0:2:0)" diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index eabcb9a5a8ca..1a0d64d7c7e0 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -124,6 +124,21 @@ int fsp_soc_report_external_display(void) return graphics_get_framebuffer_address() && get_external_display_status(); } +static void configure_ddi_a_bifurcation(void) +{ + u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); + /* Only program if the buffer is not enabled yet. */ + if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) + return; + + if (CONFIG(SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION)) + ddi_buf_ctl &= ~DDI_A_4_LANES; + else + ddi_buf_ctl |= DDI_A_4_LANES; + + graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); +} + static void gma_init(struct device *const dev) { intel_gma_init_igd_opregion(); @@ -135,12 +150,8 @@ static void gma_init(struct device *const dev) if (!CONFIG(RUN_FSP_GOP)) graphics_soc_panel_init(dev); - if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { - const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); - /* Only program if the buffer is not enabled yet. */ - if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) - graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES); - } + if (CONFIG(SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION) && !acpi_is_wakeup_s3()) + configure_ddi_a_bifurcation(); /* * GFX PEIM module inside FSP binary is taking care of graphics @@ -348,6 +359,7 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_MTL_P_GT2_2, PCI_DID_INTEL_MTL_P_GT2_3, PCI_DID_INTEL_MTL_P_GT2_4, + PCI_DID_INTEL_MTL_P_GT2_5, PCI_DID_INTEL_APL_IGD_HD_505, PCI_DID_INTEL_APL_IGD_HD_500, PCI_DID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/tcss/Kconfig b/src/soc/intel/common/block/tcss/Kconfig index 25113d33f36c..89bab79235b0 100644 --- a/src/soc/intel/common/block/tcss/Kconfig +++ b/src/soc/intel/common/block/tcss/Kconfig @@ -6,10 +6,18 @@ config SOC_INTEL_COMMON_BLOCK_TCSS help Sets up USB2/3 port mapping in TCSS MUX +config SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + def_bool n + help + TCSS uses PDC<->PMC communication to perform mux configuration. When this config is + enabled, communication happens directly between PDC and PMC. Avoid sending PMC + commands from AP/EC. + config TCSS_HAS_USBC_OPS bool "Enable USB-C MUX operations via the EC" default y if EC_GOOGLE_CHROMEEC - depends on SOC_INTEL_COMMON_BLOCK_TCSS + depends on SOC_INTEL_COMMON_BLOCK_TCSS && \ + !SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION help Enable USB-C operations via the EC. Requires `usbc_get_ops` to control features such as HPD and DP Mode entry. Currently, only the ChromeEC implements this, see diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index 84e15fd128ca..dbe76f25ced8 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -718,7 +718,7 @@ Scope (\_SB.PCI0) Method (_STA, 0x0, NotSerialized) { - If (TRE0 == 1) { + If (VDID != 0xFFFFFFFF) { Return (0x0F) } Else { Return (0x0) @@ -748,7 +748,7 @@ Scope (\_SB.PCI0) Method (_STA, 0x0, NotSerialized) { - If (TRE1 == 1) { + If (VDID != 0xFFFFFFFF) { Return (0x0F) } Else { Return (0x0) @@ -778,7 +778,7 @@ Scope (\_SB.PCI0) Method (_STA, 0x0, NotSerialized) { - If (TRE2 == 1) { + If (VDID != 0xFFFFFFFF) { Return (0x0F) } Else { Return (0x0) @@ -808,7 +808,7 @@ Scope (\_SB.PCI0) Method (_STA, 0x0, NotSerialized) { - If (TRE3 == 1) { + If (VDID != 0xFFFFFFFF) { Return (0x0F) } Else { Return (0x0) diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 49d0661f30c5..bc8ae920c101 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -58,6 +58,7 @@ static struct { { PCI_DID_INTEL_MTL_P_GT2_2, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_3, "MeteorLake-P GT2" }, { PCI_DID_INTEL_MTL_P_GT2_4, "Meteorlake-P GT2" }, + { PCI_DID_INTEL_MTL_P_GT2_5, "Meteorlake-P GT2" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 03adfdb73888..51e89dcf3a40 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -185,6 +185,9 @@ void soc_init_pre_device(void *chip_info) /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pcie_rp_table()); + /* Swap enabled TBT root ports in device tree if needed. */ + pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); + /* * Earlier when coreboot used to send EOP at late as possible caused * issue of delayed response from CSE since CSE was busy loading payload. diff --git a/src/soc/intel/meteorlake/include/soc/pcie.h b/src/soc/intel/meteorlake/include/soc/pcie.h index f97543c9167d..7c098e9ca59f 100644 --- a/src/soc/intel/meteorlake/include/soc/pcie.h +++ b/src/soc/intel/meteorlake/include/soc/pcie.h @@ -6,5 +6,6 @@ #include <intelblocks/pcie_rp.h> const struct pcie_rp_group *get_pcie_rp_table(void); +const struct pcie_rp_group *get_tbt_pcie_rp_table(void); #endif /* __SOC_METEORLAKE_PCIE_H__ */ diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c index 9f59ce1f9701..7cfe3ed29181 100644 --- a/src/soc/intel/meteorlake/pcie_rp.c +++ b/src/soc/intel/meteorlake/pcie_rp.c @@ -5,6 +5,17 @@ #include <soc/pcie.h> #include <soc/soc_info.h> +/* + * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe + * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's + * PCIe remapping logic can return correct index (0-based) + */ + +static const struct pcie_rp_group tbt_rp_groups[] = { + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { 0 } +}; + static const struct pcie_rp_group mtlp_rp_groups[] = { { .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 }, { .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 }, @@ -17,6 +28,11 @@ const struct pcie_rp_group *get_pcie_rp_table(void) return mtlp_rp_groups; } +const struct pcie_rp_group *get_tbt_pcie_rp_table(void) +{ + return tbt_rp_groups; +} + enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) { return PCIE_RP_PCH; diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 0d388049a485..3ec84abcc426 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -62,7 +62,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT - select SOC_INTEL_CONFIGURE_DDI_A_4_LANES + select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index f4051eafa8ec..18a53acc50da 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -11,9 +11,10 @@ romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c +ramstage-y += numa.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c -ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c +ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c smm-y += smihandler.c pmutil.c diff --git a/src/soc/intel/xeon_sp/acpi/gpio.asl b/src/soc/intel/xeon_sp/acpi/gen1/gpio.asl index a67bdd7d5ac0..a67bdd7d5ac0 100644 --- a/src/soc/intel/xeon_sp/acpi/gpio.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/gpio.asl diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl index 0dd39a0f5464..0dd39a0f5464 100644 --- a/src/soc/intel/xeon_sp/acpi/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl diff --git a/src/soc/intel/xeon_sp/acpi/pch.asl b/src/soc/intel/xeon_sp/acpi/gen1/pch.asl index fef68b081816..93d468a7ff3d 100644 --- a/src/soc/intel/xeon_sp/acpi/pch.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/pch.asl @@ -3,7 +3,7 @@ /* This file should be included in the proper platform ACPI \_SB PCI scope */ /* GPIO */ -#include <soc/intel/xeon_sp/acpi/gpio.asl> +#include <soc/intel/xeon_sp/acpi/gen1/gpio.asl> /* LPC 0:1f.0 */ #include <soc/intel/common/block/acpi/acpi/lpc.asl> diff --git a/src/soc/intel/xeon_sp/acpi/pch_irq.asl b/src/soc/intel/xeon_sp/acpi/gen1/pch_irq.asl index f36968f9cdb7..f36968f9cdb7 100644 --- a/src/soc/intel/xeon_sp/acpi/pch_irq.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/pch_irq.asl diff --git a/src/soc/intel/xeon_sp/acpi/pci_irqs.asl b/src/soc/intel/xeon_sp/acpi/gen1/pci_irqs.asl index eccb46b93dd5..eccb46b93dd5 100644 --- a/src/soc/intel/xeon_sp/acpi/pci_irqs.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/pci_irqs.asl diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/gen1/southcluster.asl index eb687784e755..eb687784e755 100644 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/southcluster.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore.asl b/src/soc/intel/xeon_sp/acpi/gen1/uncore.asl index 8d178cbb6bbb..8d178cbb6bbb 100644 --- a/src/soc/intel/xeon_sp/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/uncore.asl diff --git a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/acpi/gen1/uncore_irq.asl index e8d1b14c675d..e8d1b14c675d 100644 --- a/src/soc/intel/xeon_sp/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/uncore_irq.asl diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index fe2ca8654a2a..b72417e06afe 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -123,7 +123,6 @@ void save_dimm_info(void) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - const struct device *dev; const config_t *config = config_of_soc(); /* ErrorLevel - 0 (disable) to 8 (verbose) */ @@ -175,8 +174,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) /* Enable PCH thermal device in FSP, the definition of ThermalDeviceEnable is 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI mode */ - dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); - m_cfg->ThermalDeviceEnable = dev && dev->enabled; + m_cfg->ThermalDeviceEnable = is_devfn_enabled(PCH_DEVFN_THERMAL); /* Enable VT-d according to DTB */ m_cfg->VtdSupport = config->vtd_support; diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 2d6005b08fde..3472d589a8f8 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -136,3 +136,8 @@ bool is_memtype_processor_attached(uint16_t mem_type) { return true; } + +uint8_t get_cxl_node_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index e37454496238..e11b19e97e60 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -18,7 +18,6 @@ enum acpi_cstate_mode { unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); unsigned long acpi_fill_cedt(unsigned long current); unsigned long acpi_fill_hmat(unsigned long current); unsigned long cxl_fill_srat(unsigned long current); diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 5fd5dc6f18bb..5bdc87fbf53f 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -33,6 +33,12 @@ static inline void init_xeon_domain_path(struct device_path *path, int socket, path->domain.domain = dp.domain_path; }; +enum xeonsp_cxl_mode { + XEONSP_CXL_DISABLED = 0, + XEONSP_CXL_SYS_MEM, + XEONSP_CXL_SP_MEM, +}; + /* * Every STACK can have multiple PCI domains with an unique domain type. * This is only of cosmetic nature and generates more readable ACPI code, diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h index aba3f0926bc3..7bc86ae52ce2 100644 --- a/src/soc/intel/xeon_sp/include/soc/numa.h +++ b/src/soc/intel/xeon_sp/include/soc/numa.h @@ -7,8 +7,11 @@ #ifndef NUMA_H #define NUMA_H +#include <soc/soc_util.h> #include <types.h> +#define XEONSP_INVALID_PD_INDEX UINT32_MAX + enum proximity_domain_type { PD_TYPE_PROCESSOR, /* @@ -16,6 +19,7 @@ enum proximity_domain_type { * Generic Initiator domain is a CXL memory device. */ PD_TYPE_GENERIC_INITIATOR, + PD_TYPE_MAX }; /* @@ -55,6 +59,7 @@ extern struct proximity_domains pds; void dump_pds(void); void fill_pds(void); +void fill_pd_distances(void); /* * Return the total size of memory regions in generic initiator affinity @@ -62,4 +67,7 @@ void fill_pds(void); */ uint32_t get_generic_initiator_mem_size(void); +uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem); +uint32_t device_to_pd(const struct device *dev); + #endif /* NUMA_H */ diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 177d6d50e338..af749023b56d 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -4,6 +4,7 @@ #define _XEON_SP_SOC_UTIL_H_ #include <cpu/x86/msr.h> +#include <intelblocks/p2sb.h> #include <soc/soc_util.h> #define MEM_ADDR_64MB_SHIFT_BITS 26 @@ -27,5 +28,9 @@ bool is_ubox_stack_res(const xSTACK_RES *res); bool is_ioat_iio_stack_res(const xSTACK_RES *res); bool is_iio_cxl_stack_res(const xSTACK_RES *res); void bios_done_msr(void *unused); +union p2sb_bdf soc_get_hpet_bdf(void); +union p2sb_bdf soc_get_ioapic_bdf(void); + +enum xeonsp_cxl_mode get_cxl_mode(void); #endif diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c index 9e25920011b9..a3d17b46c331 100644 --- a/src/soc/intel/xeon_sp/lockdown.c +++ b/src/soc/intel/xeon_sp/lockdown.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/cfg.h> #include <intelblocks/lpc_lib.h> #include <intelpch/lockdown.h> #include <soc/lockdown.h> @@ -20,6 +21,9 @@ static void lpc_lockdown_config(void) void soc_lockdown_config(int chipset_lockdown) { + if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP) + return; + lpc_lockdown_config(); pmc_lockdown_config(); sata_lockdown_config(chipset_lockdown); diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 62657dce1f91..69ca0637b17a 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -5,6 +5,7 @@ #include <device/pci_ops.h> #include <device/pci.h> #include <device/pciexp.h> +#include <soc/chip_common.h> #include <soc/numa.h> #include <soc/soc_util.h> #include <soc/util.h> @@ -49,9 +50,8 @@ void fill_pds(void) memset(pds.pds, 0, sizeof(struct proximity_domain) * pds.num_pds); /* Fill in processor domains */ - uint8_t i, j, socket; - struct device *dev; - for (socket = 0, i = 0; i < num_sockets; socket++) { + uint8_t i = 0; + for (uint8_t socket = 0; socket < num_sockets; socket++) { if (!soc_cpu_is_enabled(socket)) continue; pds.pds[i].pd_type = PD_TYPE_PROCESSOR; @@ -59,13 +59,6 @@ void fill_pds(void) pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); - /* hard code the distances for now, till we know how to calculate them. */ - for (j = 0; j < pds.num_pds; j++) { - if (j == i) - pds.pds[i].distances[j] = 0x0a; - else - pds.pds[i].distances[j] = 0x0e; - } i++; } @@ -73,30 +66,25 @@ void fill_pds(void) if (num_cxlnodes == 0) return; +#if CONFIG(SOC_INTEL_HAS_CXL) /* There are CXL nodes, fill in generic initiator domain after the processors pds */ - uint8_t skt_id, cxl_id; const CXL_NODE_SOCKET *cxl_hob = get_cxl_node(); - for (skt_id = 0, i = num_sockets; skt_id < MAX_SOCKET; skt_id++, i++) { - for (cxl_id = 0; cxl_id < cxl_hob[skt_id].CxlNodeCount; ++cxl_id) { + for (uint8_t skt_id = 0; skt_id < MAX_SOCKET; skt_id++) { + for (uint8_t cxl_id = 0; cxl_id < cxl_hob[skt_id].CxlNodeCount; ++cxl_id) { const CXL_NODE_INFO node = cxl_hob[skt_id].CxlNodeInfo[cxl_id]; pds.pds[i].pd_type = PD_TYPE_GENERIC_INITIATOR; pds.pds[i].socket_bitmap = node.SocketBitmap; pds.pds[i].base = node.Address; pds.pds[i].size = node.Size; - dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0); + struct device *dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0); pds.pds[i].dev = dev; pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds); if (!pds.pds[i].distances) die("%s %d out of memory.", __FILE__, __LINE__); - /* hard code the distances until we know how to calculate them */ - for (j = 0; j < pds.num_pds; j++) { - if (j == i) - pds.pds[i].distances[j] = 0x0a; - else - pds.pds[i].distances[j] = 0x0e; - } + i++; } } +#endif } /* @@ -116,3 +104,72 @@ uint32_t get_generic_initiator_mem_size(void) return size; } + +static uint32_t socket_to_pd(uint8_t socket) +{ + for (uint8_t i = 0; i < pds.num_pds; i++) { + if (pds.pds[i].pd_type != PD_TYPE_PROCESSOR) + continue; + if (pds.pds[i].socket_bitmap == (1 << socket)) + return i; + } + + printk(BIOS_ERR, "%s: could not find proximity domain for socket %d.\n", + __func__, socket); + + return XEONSP_INVALID_PD_INDEX; +} + +uint32_t device_to_pd(const struct device *dev) +{ + /* first to see if the dev is bound to specific pd */ + for (int i = 0; i < pds.num_pds; i++) + if (pds.pds[i].dev == dev) + return i; + + if (dev->path.type == DEVICE_PATH_APIC) + return socket_to_pd(dev->path.apic.package_id); + + if ((dev->path.type == DEVICE_PATH_DOMAIN) || + (dev->path.type == DEVICE_PATH_PCI)) + return socket_to_pd(iio_pci_domain_socket_from_dev(dev)); + + printk(BIOS_ERR, "%s: could not find proximity domain for device %s.\n", + __func__, dev_path(dev)); + + return XEONSP_INVALID_PD_INDEX; +} + +uint32_t memory_to_pd(const struct SystemMemoryMapElement *mem) +{ + return socket_to_pd(mem->SocketId); +} + +#define PD_DISTANCE_SELF 0x0A +#define PD_DISTANCE_SAME_SOCKET 0x0C +#define PD_DISTANCE_CROSS_SOCKET 0x14 +#define PD_DISTANCE_MAX 0xFF +#define PD_DISTANCE_IO_EXTRA 0x01 + +void fill_pd_distances(void) +{ + for (int i = 0; i < pds.num_pds; i++) { + for (int j = 0; j < pds.num_pds; j++) { + if (i == j) { + pds.pds[i].distances[j] = PD_DISTANCE_SELF; + continue; + } + + if (pds.pds[i].socket_bitmap == pds.pds[j].socket_bitmap) + pds.pds[i].distances[j] = PD_DISTANCE_SAME_SOCKET; + else + pds.pds[i].distances[j] = PD_DISTANCE_CROSS_SOCKET; + + if (pds.pds[i].pd_type == PD_TYPE_GENERIC_INITIATOR) + pds.pds[i].distances[j] += PD_DISTANCE_IO_EXTRA; + + if (pds.pds[j].pd_type == PD_TYPE_GENERIC_INITIATOR) + pds.pds[i].distances[j] += PD_DISTANCE_IO_EXTRA; + } + } +} diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 6f482466cea0..0ccacfb73c37 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -209,3 +209,8 @@ bool is_memtype_processor_attached(uint16_t mem_type) { return true; } + +uint8_t get_cxl_node_count(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 401c8e498159..b84a8ff26771 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -107,9 +107,6 @@ config SOC_INTEL_HAS_BIOS_DONE_MSR config SOC_INTEL_HAS_NCMEM def_bool y -config SOC_INTEL_PCIE_64BIT_ALLOC - def_bool y - config SOC_INTEL_MMAPVTD_ONLY_FOR_DPR def_bool y diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index f9c8e2627393..ad099ab70b71 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -1,28 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> -#include <acpi/acpi.h> -#include <console/console.h> #include <console/debug.h> -#include <cpu/cpu.h> -#include <cpu/intel/cpu_ids.h> #include <cpu/intel/common/common.h> -#include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/microcode.h> #include <cpu/intel/smm_reloc.h> #include <cpu/intel/turbo.h> -#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> -#include <cpu/x86/mtrr.h> #include <cpu/x86/topology.h> -#include <device/pci_mmio_cfg.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> #include <intelpch/lockdown.h> #include <soc/msr.h> -#include <soc/pci_devs.h> #include <soc/pm.h> -#include <soc/soc_util.h> #include <soc/smmrelocate.h> #include <soc/util.h> @@ -235,6 +224,12 @@ static int get_thread_count(void) { unsigned int num_phys = 0, num_virts = 0; + /* + * This call calculates the thread count which is corresponding to num_virts + * (logical cores), while num_phys is corresponding to physical cores (in SMT + * system, one physical core has multiple threads, a.k.a. logical cores). + * Hence num_phys is not actually used. + */ cpu_read_topology(&num_phys, &num_virts); printk(BIOS_SPEW, "Detected %u cores and %u threads\n", num_phys, num_virts); return num_virts * soc_get_num_cpus(); @@ -273,12 +268,9 @@ void mp_init_cpus(struct bus *bus) chip_config = bus->dev->chip_info; microcode_patch = intel_microcode_find(); - - if (!microcode_patch) - printk(BIOS_ERR, "microcode not found in CBFS!\n"); - intel_microcode_load_unlocked(microcode_patch); - if (mp_init_with_smm(bus, &mp_ops) < 0) - printk(BIOS_ERR, "MP initialization failure.\n"); + enum cb_err ret = mp_init_with_smm(bus, &mp_ops); + if (ret != CB_SUCCESS) + printk(BIOS_ERR, "MP initialization failure %d.\n", ret); } diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 3e16608ca4c8..bdb9886a8db1 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -13,12 +13,14 @@ #include <fsp/util.h> #include <hob_iiouds.h> #include <hob_memmap.h> +#include <soc/chip_common.h> #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/soc_pch.h> #include <soc/intel/common/smbios.h> #include <string.h> #include <soc/soc_util.h> +#include <soc/util.h> #include <soc/ddr.h> #include "chip.h" @@ -32,73 +34,10 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd) /* Default weak implementation */ } -/* - * Search from VPD_RW first then VPD_RO for UPD config variables, - * overwrites them from VPD if it's found. - */ -static void config_upd_from_vpd(FSPM_UPD *mupd) +static void config_upd(FSPM_UPD *mupd) { - uint8_t val; - int val_int, cxl_mode; - - /* Send FSP log message to SOL */ - if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to %d\n", - FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; - } - - if (mupd->FspmConfig.SerialIoUartDebugEnable) { - /* FSP memory debug log level */ - if (vpd_get_int(FSP_MEM_LOG_LEVEL, VPD_RW_THEN_RO, &val_int)) { - if (val_int < 0 || val_int > 4) { - printk(BIOS_DEBUG, - "Invalid serialDebugMsgLvl value from VPD: " - "%d\n", - val_int); - val_int = FSP_MEM_LOG_LEVEL_DEFAULT; - } - printk(BIOS_DEBUG, "Setting serialDebugMsgLvl to %d\n", val_int); - mupd->FspmConfig.serialDebugMsgLvl = (uint8_t)val_int; - } else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "DebugPrintLevel to %d\n", - FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT); - mupd->FspmConfig.serialDebugMsgLvl = FSP_MEM_LOG_LEVEL_DEFAULT; - } - /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ - if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { - printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); - mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; - } - } - - /* FSP Dfx PMIC Secure mode */ - if (vpd_get_int(FSP_PMIC_SECURE_MODE, VPD_RW_THEN_RO, &val_int)) { - if (val_int < 0 || val_int > 2) { - printk(BIOS_DEBUG, - "Invalid PMIC secure mode value from VPD: " - "%d\n", - val_int); - val_int = FSP_PMIC_SECURE_MODE_DEFAULT; - } - printk(BIOS_DEBUG, "Setting PMIC secure mode to %d\n", val_int); - mupd->FspmConfig.DfxPmicSecureMode = (uint8_t)val_int; - } else { - printk(BIOS_INFO, - "Not able to get VPD %s, default set " - "PMIC secure mode to %d\n", - FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT); - mupd->FspmConfig.DfxPmicSecureMode = FSP_PMIC_SECURE_MODE_DEFAULT; - } - - cxl_mode = get_cxl_mode_from_vpd(); - if (cxl_mode == CXL_SYSTEM_MEMORY || cxl_mode == CXL_SPM) + int cxl_mode = get_cxl_mode(); + if (cxl_mode == XEONSP_CXL_SYS_MEM || cxl_mode == XEONSP_CXL_SP_MEM) mupd->FspmConfig.DfxCxlType3LegacyEn = 1; else /* Disable CXL */ mupd->FspmConfig.DfxCxlType3LegacyEn = 0; @@ -272,9 +211,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) printk(BIOS_DEBUG, "CPU is D stepping, setting package C state to C0/C1\n"); mupd->FspmConfig.CpuPmPackageCState = 0; } - /* Set some common UPDs from VPD, mainboard can still override them if needed */ - if (CONFIG(VPD)) - config_upd_from_vpd(mupd); + + config_upd(mupd); initialize_iio_upd(mupd); mainboard_memory_init_params(mupd); diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 1249b8ff041d..32ef1edb20f2 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -12,6 +12,7 @@ #include <intelblocks/pmclib.h> #include <soc/acpi.h> #include <soc/iomap.h> +#include <soc/numa.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -155,25 +156,6 @@ void soc_power_states_generation(int core, int cores_per_package) acpigen_pop_len(); } -unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) -{ - struct device *cpu; - uint8_t num_cpus = 0; - - for (cpu = all_devices; cpu; cpu = cpu->next) { - if ((cpu->path.type != DEVICE_PATH_APIC) - || (cpu->upstream->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!cpu->enabled) - continue; - current = acpi_create_madt_one_lapic(current, num_cpus, cpu->path.apic.apic_id); - num_cpus++; - } - - return current; -} - unsigned long acpi_fill_cedt(unsigned long current) { const IIO_UDS *hob = get_iio_uds(); diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index a177a89d6622..efa61b7c1691 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -6,8 +6,8 @@ #include <cpu/x86/lapic_def.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <drivers/ocp/include/vpd.h> #include <soc/acpi.h> +#include <soc/chip_common.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -286,22 +286,20 @@ static void mc_add_dram_resources(struct device *dev, int *res_count) if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) continue; - if (CONFIG(OCP_VPD)) { - unsigned long flags = IORESOURCE_CACHEABLE; - int cxl_mode = get_cxl_mode_from_vpd(); - if (cxl_mode == CXL_SPM) - flags |= IORESOURCE_SOFT_RESERVE; - else - flags |= IORESOURCE_STORED; - - res = fixed_mem_range_flags(dev, index++, - (uint64_t)pds.pds[i].base << 26, - (uint64_t)pds.pds[i].size << 26, flags); - if (cxl_mode == CXL_SPM) - LOG_RESOURCE("specific_purpose_memory", dev, res); - else - LOG_RESOURCE("CXL_memory", dev, res); - } + unsigned long flags = IORESOURCE_CACHEABLE; + int cxl_mode = get_cxl_mode(); + if (cxl_mode == XEONSP_CXL_SP_MEM) + flags |= IORESOURCE_SOFT_RESERVE; + else + flags |= IORESOURCE_STORED; + + res = fixed_mem_range_flags(dev, index++, + (uint64_t)pds.pds[i].base << 26, + (uint64_t)pds.pds[i].size << 26, flags); + if (cxl_mode == XEONSP_CXL_SP_MEM) + LOG_RESOURCE("specific_purpose_memory", dev, res); + else + LOG_RESOURCE("CXL_memory", dev, res); } } else { /* 4GiB -> TOHM */ @@ -338,14 +336,13 @@ static void mmapvtd_read_resources(struct device *dev) { int index = 0; - if (CONFIG(SOC_INTEL_HAS_CXL)) { - static bool once; - if (!once) { - /* Construct NUMA data structure. This is needed for CXL. */ - fill_pds(); - dump_pds(); - once = true; - } + static bool once; + if (!once) { + /* Construct NUMA data structure. This is needed for CXL. */ + fill_pds(); + fill_pd_distances(); + dump_pds(); + once = true; } /* Read standard PCI resources. */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index bcfb4da92d75..6b6363d8ec54 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -18,7 +18,6 @@ #include <soc/pci_devs.h> #include <soc/soc_util.h> #include <soc/util.h> -#include <intelblocks/p2sb.h> #include "chip.h" /* NUMA related ACPI table generation. SRAT, SLIT, etc */ @@ -60,16 +59,16 @@ unsigned long acpi_create_srat_lapics(unsigned long current) if (is_x2apic_mode()) { printk(BIOS_DEBUG, "SRAT: x2apic cpu_index=%04x, node_id=%02x, apic_id=%08x\n", - i, cpu->path.apic.node_id, cpu->path.apic.apic_id); + i, device_to_pd(cpu), cpu->path.apic.apic_id); current += acpi_create_srat_x2apic((acpi_srat_x2apic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); + device_to_pd(cpu), cpu->path.apic.apic_id); } else { printk(BIOS_DEBUG, "SRAT: lapic cpu_index=%02x, node_id=%02x, apic_id=%02x\n", - i, cpu->path.apic.node_id, cpu->path.apic.apic_id); + i, device_to_pd(cpu), cpu->path.apic.apic_id); current += acpi_create_srat_lapic((acpi_srat_lapic_t *)current, - cpu->path.apic.node_id, cpu->path.apic.apic_id); + device_to_pd(cpu), cpu->path.apic.apic_id); } } return current; @@ -129,7 +128,7 @@ static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) srat_mem[mmap_index].base_address_high = (uint32_t)(addr >> 32); srat_mem[mmap_index].length_low = (uint32_t)(size & 0xffffffff); srat_mem[mmap_index].length_high = (uint32_t)(size >> 32); - srat_mem[mmap_index].proximity_domain = mem_element->SocketId; + srat_mem[mmap_index].proximity_domain = memory_to_pd(mem_element); srat_mem[mmap_index].flags = ACPI_SRAT_MEMORY_ENABLED; if (is_memtype_non_volatile(mem_element->Type)) srat_mem[mmap_index].flags |= ACPI_SRAT_MEMORY_NONVOLATILE; @@ -283,7 +282,7 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm // Add PCH IOAPIC if (is_dev_on_domain0(iommu)) { - union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); + union p2sb_bdf ioapic_bdf = soc_get_ioapic_bdf(); printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(IO_APIC_ADDR), ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); @@ -318,7 +317,7 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm const struct device *domain = dev_get_domain(iommu); struct device *dev = NULL; while ((dev = dev_bus_each_child(domain->downstream, dev))) - if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) + if (is_pci_bridge(dev)) current += acpi_create_dmar_ds_pci_br_for_port( current, dev, pcie_seg, false, NULL); @@ -363,7 +362,7 @@ static unsigned long acpi_create_drhd(unsigned long current, struct device *iomm //BIT 15 if (num_hpets && (num_hpets != 0x1f) && (read32p(HPET_BASE_ADDRESS + 0x100) & (0x00008000))) { - union p2sb_bdf hpet_bdf = p2sb_get_hpet_bdf(); + union p2sb_bdf hpet_bdf = soc_get_hpet_bdf(); printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", 0, hpet_bdf.bus, hpet_bdf.dev, hpet_bdf.fn); @@ -422,7 +421,7 @@ static unsigned long acpi_create_atsr(unsigned long current) continue; for (child = dev->upstream->children; child; child = child->sibling) { - if ((child->hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) + if (!is_pci_bridge(child)) continue; current += acpi_create_dmar_ds_pci_br_for_port( @@ -445,7 +444,6 @@ static unsigned long acpi_create_rhsa(unsigned long current) { struct device *dev = NULL; struct resource *resource; - int socket; while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) { /* See if there is a resource with the appropriate index. */ @@ -453,11 +451,9 @@ static unsigned long acpi_create_rhsa(unsigned long current) if (!resource) continue; - socket = iio_pci_domain_socket_from_dev(dev); - printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: %p, " - "Proximity Domain: 0x%x\n", res2mmio(resource, 0, 0), socket); - current += acpi_create_dmar_rhsa(current, (uintptr_t)res2mmio(resource, 0, 0), socket); + "Proximity Domain: 0x%x\n", res2mmio(resource, 0, 0), device_to_pd(dev)); + current += acpi_create_dmar_rhsa(current, (uintptr_t)res2mmio(resource, 0, 0), device_to_pd(dev)); } return current; diff --git a/src/soc/intel/xeon_sp/uncore_acpi_cxl.c b/src/soc/intel/xeon_sp/uncore_acpi_cxl.c index 40a5f1249672..6e1fa71f93de 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi_cxl.c +++ b/src/soc/intel/xeon_sp/uncore_acpi_cxl.c @@ -13,7 +13,9 @@ unsigned long cxl_fill_srat(unsigned long current) * are after processor domains. */ uint32_t base, size; - for (uint8_t i = soc_get_num_cpus(); i < pds.num_pds; i++) { + for (uint8_t i = 0; i < pds.num_pds; i++) { + if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) + continue; if (!pds.pds[i].dev) continue; diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 81dc77db8008..2fdf45e04ffe 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -9,8 +9,10 @@ #include <device/pci_ids.h> #include <intelblocks/cfg.h> #include <intelblocks/cpulib.h> +#include <intelblocks/p2sb.h> #include <intelpch/lockdown.h> #include <soc/chip_common.h> +#include <soc/pch_pci_devs.h> #include <soc/pci_devs.h> #include <soc/msr.h> #include <soc/soc_util.h> @@ -88,6 +90,32 @@ unsigned int soc_get_num_cpus(void) return get_iio_uds()->SystemStatus.numCpus; } +union p2sb_bdf soc_get_hpet_bdf(void) +{ + if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { + union p2sb_bdf bdf = { + .bus = HPET_BUS_NUM, + .dev = HPET_DEV_NUM, + .fn = HPET0_FUNC_NUM + }; + return bdf; + } + return p2sb_get_hpet_bdf(); +} + +union p2sb_bdf soc_get_ioapic_bdf(void) +{ + if (CONFIG(SOC_INTEL_COMMON_IBL_BASE)) { + union p2sb_bdf bdf = { + .bus = PCH_IOAPIC_BUS_NUMBER, + .dev = PCH_IOAPIC_DEV_NUM, + .fn = PCH_IOAPIC_FUNC_NUM + }; + return bdf; + } + return p2sb_get_ioapic_bdf(); +} + #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ void lock_pam0123(void) @@ -237,3 +265,8 @@ void set_bios_init_completion(void) set_bios_init_completion_for_package(sbsp_socket_id); } #endif + +__weak enum xeonsp_cxl_mode get_cxl_mode(void) +{ + return XEONSP_CXL_DISABLED; +} diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h index d390b70ffa67..249959b91042 100644 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_USB_COMMON_H #include <stddef.h> +#include <stdint.h> /* ip_pw_ctrl0 */ #define CTRL0_IP_SW_RST (0x1 << 0) @@ -162,5 +163,7 @@ void mtk_usb_prepare(void); void mtk_usb_adjust_phy_shift(void); void setup_usb_host(void); - +void update_usb_base_regs(uintptr_t ippc_base, uintptr_t sif_base); +void setup_usb_secondary_host(void); +void setup_usb_host_controller(void); #endif diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index b9fe83529d3b..cc2503b4e5fe 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -13,6 +13,12 @@ static struct ssusb_ippc_regs *ippc_regs = (void *)(SSUSB_IPPC_BASE); static struct ssusb_sif_port *phy_ports = (void *)(SSUSB_SIF_BASE); +void update_usb_base_regs(uintptr_t ippc_base, uintptr_t sif_base) +{ + ippc_regs = (void *)ippc_base; + phy_ports = (void *)sif_base; +} + static void phy_index_power_on(int index) { struct ssusb_sif_port *phy = phy_ports + index; @@ -150,7 +156,7 @@ __weak void mtk_usb_adjust_phy_shift(void) /* do nothing */ } -void setup_usb_host(void) +void setup_usb_host_controller(void) { u3p_msg("Setting up USB HOST controller...\n"); @@ -164,3 +170,9 @@ void setup_usb_host(void) mtk_usb_adjust_phy_shift(); u3p_msg("phy power-on done.\n"); } + +void setup_usb_host(void) +{ + update_usb_base_regs(SSUSB_IPPC_BASE, SSUSB_SIF_BASE); + setup_usb_host_controller(); +} diff --git a/src/soc/mediatek/common/usb_secondary.c b/src/soc/mediatek/common/usb_secondary.c new file mode 100644 index 000000000000..ee85630250f0 --- /dev/null +++ b/src/soc/mediatek/common/usb_secondary.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/addressmap.h> +#include <soc/usb.h> + +void setup_usb_secondary_host(void) +{ + /* We always consider USB2 port as the secondary UBS host regardless of the + register naming */ + update_usb_base_regs(SSUSB_IPPC_BASE_P0, SSUSB_SIF_BASE_P0); + setup_usb_host_controller(); +} diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk index 3a3cc07ce6f7..8e116f82e653 100644 --- a/src/soc/mediatek/mt8186/Makefile.mk +++ b/src/soc/mediatek/mt8186/Makefile.mk @@ -51,7 +51,7 @@ ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/tps65132s.c -ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/usb.c ../common/usb_secondary.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include diff --git a/src/soc/mediatek/mt8186/include/soc/addressmap.h b/src/soc/mediatek/mt8186/include/soc/addressmap.h index 5f0b10c5e03e..64500aaad094 100644 --- a/src/soc/mediatek/mt8186/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8186/include/soc/addressmap.h @@ -76,11 +76,13 @@ enum { SPI5_BASE = IO_PHYS + 0x01015000, I2C5_BASE = IO_PHYS + 0x01016000, I2C9_BASE = IO_PHYS + 0x01019000, - /* Corsola uses USB2 port1 instead of USB2 port0. */ + /* IPPC_BASE is for USB2 port1, IPPC_BASE_P0 is for USB2 port0 */ + SSUSB_IPPC_BASE_P0 = IO_PHYS + 0x01203E00, SSUSB_IPPC_BASE = IO_PHYS + 0x01283E00, MSDC0_BASE = IO_PHYS + 0x01230000, - /* Corsola uses USB2 port1 instead of USB2 port0. */ + /* SIF_BASE is for USB2 port1, SIF_BASE_P0 is for USB2 port0 */ SSUSB_SIF_BASE = IO_PHYS + 0x01C80300, + SSUSB_SIF_BASE_P0 = IO_PHYS + 0x01CA0300, EFUSEC_BASE = IO_PHYS + 0x01CB0000, MIPITX_BASE = IO_PHYS + 0x01CC0000, MSDC0_TOP_BASE = IO_PHYS + 0x01CD0000, diff --git a/src/soc/mediatek/mt8188/devapc.c b/src/soc/mediatek/mt8188/devapc.c index 6c585baf50b0..960c70ae0766 100644 --- a/src/soc/mediatek/mt8188/devapc.c +++ b/src/soc/mediatek/mt8188/devapc.c @@ -114,14 +114,14 @@ static const struct apc_infra_peri_dom_16 infra_ao_sys0_devices[] = { DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-2", - NO_PROTECTION, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-3", NO_PROTECTION, FORBIDDEN15), /* 50 */ DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-4", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-5", - NO_PROTECTION, FORBIDDEN15), + SEC_RW_ONLY, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-6", NO_PROTECTION, FORBIDDEN15), DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-7", @@ -1616,6 +1616,8 @@ static void dump_fmem_ao(uintptr_t base) { printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)DOM_REMAP_0_0:%#x\n", base, read32(getreg(base, DOM_REMAP_0_0))); + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_FMEM_AO_BASE %#lx)MAS_DOM_1:%#x\n", + base, read32(getreg(base, MAS_DOM_1))); } static void dump_infra2_ao(uintptr_t base) @@ -1633,6 +1635,12 @@ static void dump_scp_master(uintptr_t base) read32(getreg(base, ONETIME_LOCK))); } +static void dump_sec_mfg_hyp(uintptr_t base) +{ + printk(BIOS_DEBUG, "[DEVAPC] (DEVAPC_INFRA_BASE %#lx)INFRA_AO_SEC_MFG_HYP:%#x\n", + base, read32(getreg(base, 0))); +} + static void infra_init(uintptr_t base) { void *reg; @@ -1715,6 +1723,10 @@ static void peri_par_init(uintptr_t base) static void fmem_master_init(uintptr_t base) { + /* Master Domain */ + SET32_BITFIELDS(getreg(base, MAS_DOM_1), + MFG_M0_DOM, DOMAIN_6); + /* * Domain Remap: TINYSYS to EMI (3-bit to 4-bit) * 1. DSP from 0 to 4 @@ -1770,6 +1782,18 @@ static void scp_master_init(uintptr_t base) write32(getreg(base, ONETIME_LOCK), 0x5); } +static void infra_sec_mfg_hyp_init(uintptr_t base) +{ + /* Set GPU protection mode */ + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID0, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID1, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID2, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), OSID3, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), FM_EN, MFG_NS_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), SEC_EN, MFG_S_D6); + SET32_BITFIELDS(getreg(base, MFG_HPY_OFT), REMAP_EN, 1); +} + const struct devapc_init_ops devapc_init[] = { { DEVAPC_INFRA_AO_BASE, infra_init, dump_infra_ao_apc }, { DEVAPC_PERI_AO_BASE, peri_init, dump_peri_ao_apc }, @@ -1778,6 +1802,10 @@ const struct devapc_init_ops devapc_init[] = { { DEVAPC_FMEM_AO_BASE, fmem_master_init, dump_fmem_ao }, { DEVAPC_INFRA2_AO_BASE, infra2_master_init, dump_infra2_ao }, { SCP_CFG_BASE, scp_master_init, dump_scp_master }, + { INFRACFG_AO_BASE + INFRA_AO_SEC_MFG_HYP, + infra_sec_mfg_hyp_init, dump_sec_mfg_hyp }, + { SUB_INFRACFG_AO_BASE + INFRA_AO_SEC_MFG_HYP2, + infra_sec_mfg_hyp_init, dump_sec_mfg_hyp }, }; const size_t devapc_init_cnt = ARRAY_SIZE(devapc_init); diff --git a/src/soc/mediatek/mt8188/include/soc/addressmap.h b/src/soc/mediatek/mt8188/include/soc/addressmap.h index 53e52146ea76..b942a85d5d7e 100644 --- a/src/soc/mediatek/mt8188/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8188/include/soc/addressmap.h @@ -55,6 +55,7 @@ enum { I2C6_DMA_BASE = IO_PHYS + 0x00220600, DEVAPC_INFRA2_AO_BASE = IO_PHYS + 0x00228000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + SUB_INFRACFG_AO_BASE = IO_PHYS + 0x0030E000, INFRA_TRACKER_BASE = IO_PHYS + 0x00314000, SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, diff --git a/src/soc/mediatek/mt8188/include/soc/devapc.h b/src/soc/mediatek/mt8188/include/soc/devapc.h index d71377c2b80c..8765aded05a9 100644 --- a/src/soc/mediatek/mt8188/include/soc/devapc.h +++ b/src/soc/mediatek/mt8188/include/soc/devapc.h @@ -15,6 +15,7 @@ enum devapc_ao_offset { DOM_REMAP_0_1 = 0x00804, DOM_REMAP_2_0 = 0x00820, MAS_DOM_0 = 0x00900, + MAS_DOM_1 = 0x00904, MAS_SEC_0 = 0x00A00, AO_APC_CON = 0x00F00, }; @@ -26,6 +27,11 @@ enum scp_offset { ONETIME_LOCK = 0xA5104, }; +enum sub_infracfg_ao_mem_offset { + INFRA_AO_SEC_MFG_HYP = 0xFB4, + INFRA_AO_SEC_MFG_HYP2 = 0x68, +}; + /****************************************************************************** * STRUCTURE DEFINITION ******************************************************************************/ @@ -43,6 +49,11 @@ enum devapc_cfg_index { DEVAPC_DEBUGSYS_INDEX = 14, }; +enum mfg_dom { + MFG_S_D6 = 0x16, + MFG_NS_D6 = 0x6, +}; + /* PERM_ATTR MACRO */ #define DAPC_INFRA_AO_SYS0_ATTR(...) { { DAPC_PERM_ATTR_16(__VA_ARGS__) } } #define DAPC_INFRA_AO_SYS1_ATTR(...) { { DAPC_PERM_ATTR_4(__VA_ARGS__) } } @@ -58,6 +69,7 @@ enum devapc_cfg_index { #define MOD_NO_IN_1_DEVAPC 16 #define DOMAIN_OFT 0x40 #define IDX_OFT 0x4 +#define MFG_HPY_OFT 0 /****************************************************************************** * Bit Field DEFINITION @@ -75,4 +87,16 @@ DEFINE_BITFIELD(SPM_DOM, 3, 0) /* 0 */ /* PERI_PAR */ DEFINE_BITFIELD(PCIE0_DOM, 27, 24) /* 19 */ +/* FMEM */ +DEFINE_BITFIELD(MFG_M0_DOM, 19, 16) /* 6 */ + +/* INFRACFG_AO SEC MFG HYP */ +DEFINE_BITFIELD(OSID0, 4, 0) +DEFINE_BITFIELD(OSID1, 9, 5) +DEFINE_BITFIELD(OSID2, 14, 10) +DEFINE_BITFIELD(OSID3, 19, 15) +DEFINE_BITFIELD(FM_EN, 24, 20) +DEFINE_BITFIELD(SEC_EN, 29, 25) +DEFINE_BIT(REMAP_EN, 31) + #endif /* SOC_MEDIATEK_MT8188_DEVAPC_H */ diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c index 43fe6c97f373..8e33988682f5 100644 --- a/tests/lib/dimm_info_util-test.c +++ b/tests/lib/dimm_info_util-test.c @@ -2,6 +2,8 @@ #include <device/dram/ddr2.h> #include <device/dram/ddr3.h> +#include <device/dram/ddr4.h> +#include <device/dram/ddr5.h> #include <dimm_info_util.h> #include <spd.h> #include <tests/test.h> @@ -156,14 +158,16 @@ static void test_smbios_form_factor_to_spd_mod_type(void **state) }, { .memory_type = MEMORY_TYPE_DDR4, - .udimm_allowed = {DDR4_SPD_UDIMM, DDR4_SPD_MINI_UDIMM}, - .rdimm_allowed = {DDR4_SPD_RDIMM, DDR4_SPD_MINI_RDIMM}, - .expected_module_type = DDR4_SPD_SODIMM, + .udimm_allowed = {SPD_DDR4_DIMM_TYPE_UDIMM, + SPD_DDR4_DIMM_TYPE_MINI_UDIMM}, + .rdimm_allowed = {SPD_DDR4_DIMM_TYPE_RDIMM, + SPD_DDR4_DIMM_TYPE_MINI_RDIMM}, + .expected_module_type = SPD_DDR4_DIMM_TYPE_SO_DIMM, }, {.memory_type = MEMORY_TYPE_DDR5, - .udimm_allowed = {DDR5_SPD_UDIMM, DDR5_SPD_MINI_UDIMM}, - .rdimm_allowed = {DDR5_SPD_RDIMM, DDR5_SPD_MINI_RDIMM}, - .expected_module_type = DDR5_SPD_SODIMM}, + .udimm_allowed = {SPD_DDR5_DIMM_TYPE_UDIMM, SPD_DDR5_DIMM_TYPE_MINI_UDIMM}, + .rdimm_allowed = {SPD_DDR5_DIMM_TYPE_RDIMM, SPD_DDR5_DIMM_TYPE_MINI_RDIMM}, + .expected_module_type = SPD_DDR5_DIMM_TYPE_SODIMM}, }; /* Test for DDRx DIMM Modules */ diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 3d0f0612f8af..e72ff7d3950b 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -137,7 +137,7 @@ do_one_board() { # Main # -BOARD=$1 +BOARD=${1,,} exit_if_dependencies_are_missing diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index ecada143b39f..dbbc6ecff1ff 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -42,7 +42,6 @@ RUN \ less \ libcapture-tiny-perl \ libcrypto++-dev \ - libcurl4 \ libcurl4-openssl-dev \ libdatetime-perl \ libelf-dev \ @@ -73,7 +72,7 @@ RUN \ parted \ patch \ pbzip2 \ - pkg-config \ + pkgconf \ python3 \ python-is-python3 \ qemu-system-arm \ diff --git a/util/util_readme/post_util.md b/util/util_readme/post_util.md index 892dc8a766ee..b0b7bac41d19 100644 --- a/util/util_readme/post_util.md +++ b/util/util_readme/post_util.md @@ -1,10 +1,14 @@ ## In depth documentation -* [abuild](util/abuild/index.md) -* [cbfstool](util/cbfstool/index.md) -* [ifdtool](util/ifdtool/index.md) -* [intelp2m](util/intelp2m/index.md) -* [smmstoretool](util/smmstoretool/index.md) +```{toctree} +:maxdepth: 1 + +abuild <util/abuild/index.md> +cbfstool <util/cbfstool/index.md> +ifdtool <util/ifdtool/index.md> +intelp2m <util/intelp2m/index.md> +smmstoretool <util/smmstoretool/index.md> +``` ## Generated documentation |