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-rw-r--r--src/soc/intel/xeon_sp/Makefile.mk3
-rw-r--r--src/soc/intel/xeon_sp/cpx/soc_util.c5
-rw-r--r--src/soc/intel/xeon_sp/numa.c5
-rw-r--r--src/soc/intel/xeon_sp/skx/soc_util.c5
-rw-r--r--src/soc/intel/xeon_sp/uncore.c14
5 files changed, 21 insertions, 11 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk
index f4051eafa8ec..18a53acc50da 100644
--- a/src/soc/intel/xeon_sp/Makefile.mk
+++ b/src/soc/intel/xeon_sp/Makefile.mk
@@ -11,9 +11,10 @@ romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c
romstage-y += ../../../cpu/intel/car/romstage.c
ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c
ramstage-y += memmap.c pch.c lockdown.c finalize.c
+ramstage-y += numa.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c
-ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c numa.c
+ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
ramstage-$(CONFIG_XEON_SP_HAVE_IIO_IOAPIC) += iio_ioapic.c
smm-y += smihandler.c pmutil.c
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 2d6005b08fde..3472d589a8f8 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -136,3 +136,8 @@ bool is_memtype_processor_attached(uint16_t mem_type)
{
return true;
}
+
+uint8_t get_cxl_node_count(void)
+{
+ return 0;
+}
diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c
index 62657dce1f91..0186865e86ee 100644
--- a/src/soc/intel/xeon_sp/numa.c
+++ b/src/soc/intel/xeon_sp/numa.c
@@ -50,7 +50,6 @@ void fill_pds(void)
/* Fill in processor domains */
uint8_t i, j, socket;
- struct device *dev;
for (socket = 0, i = 0; i < num_sockets; socket++) {
if (!soc_cpu_is_enabled(socket))
continue;
@@ -73,6 +72,7 @@ void fill_pds(void)
if (num_cxlnodes == 0)
return;
+#if CONFIG(SOC_INTEL_HAS_CXL)
/* There are CXL nodes, fill in generic initiator domain after the processors pds */
uint8_t skt_id, cxl_id;
const CXL_NODE_SOCKET *cxl_hob = get_cxl_node();
@@ -83,7 +83,7 @@ void fill_pds(void)
pds.pds[i].socket_bitmap = node.SocketBitmap;
pds.pds[i].base = node.Address;
pds.pds[i].size = node.Size;
- dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0);
+ struct device *dev = pcie_find_dsn(node.SerialNumber, node.VendorId, 0);
pds.pds[i].dev = dev;
pds.pds[i].distances = malloc(sizeof(uint8_t) * pds.num_pds);
if (!pds.pds[i].distances)
@@ -97,6 +97,7 @@ void fill_pds(void)
}
}
}
+#endif
}
/*
diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c
index 6f482466cea0..0ccacfb73c37 100644
--- a/src/soc/intel/xeon_sp/skx/soc_util.c
+++ b/src/soc/intel/xeon_sp/skx/soc_util.c
@@ -209,3 +209,8 @@ bool is_memtype_processor_attached(uint16_t mem_type)
{
return true;
}
+
+uint8_t get_cxl_node_count(void)
+{
+ return 0;
+}
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index a177a89d6622..e4c46758556b 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -338,14 +338,12 @@ static void mmapvtd_read_resources(struct device *dev)
{
int index = 0;
- if (CONFIG(SOC_INTEL_HAS_CXL)) {
- static bool once;
- if (!once) {
- /* Construct NUMA data structure. This is needed for CXL. */
- fill_pds();
- dump_pds();
- once = true;
- }
+ static bool once;
+ if (!once) {
+ /* Construct NUMA data structure. This is needed for CXL. */
+ fill_pds();
+ dump_pds();
+ once = true;
}
/* Read standard PCI resources. */