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-rw-r--r--src/soc/intel/xeon_sp/include/soc/util.h8
-rw-r--r--src/soc/intel/xeon_sp/spr/ioat.c2
-rw-r--r--src/soc/intel/xeon_sp/spr/soc_acpi.c4
-rw-r--r--src/soc/intel/xeon_sp/spr/soc_util.c5
-rw-r--r--src/soc/intel/xeon_sp/uncore_acpi.c24
5 files changed, 25 insertions, 18 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h
index 89cc5017fd50..b532b9a7a832 100644
--- a/src/soc/intel/xeon_sp/include/soc/util.h
+++ b/src/soc/intel/xeon_sp/include/soc/util.h
@@ -25,6 +25,14 @@ struct iiostack_resource {
void get_iiostack_info(struct iiostack_resource *info);
bool is_pcie_iio_stack_res(const STACK_RES *res);
bool is_ubox_stack_res(const STACK_RES *res);
+#if CONFIG(HAVE_IOAT_DOMAINS)
+bool is_ioat_iio_stack_res(const STACK_RES *res);
+#else
+static inline bool is_ioat_iio_stack_res(const STACK_RES *res)
+{
+ return false;
+}
+#endif
void bios_done_msr(void *unused);
#endif
diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c
index 60936a8a42c9..0d81d0d2ef74 100644
--- a/src/soc/intel/xeon_sp/spr/ioat.c
+++ b/src/soc/intel/xeon_sp/spr/ioat.c
@@ -86,7 +86,7 @@ void soc_create_ioat_domains(const union xeon_domain_path path, struct bus *cons
/* The FSP HOB doesn't provide accurate information about the
resource allocation. Hence use pre-defined offsets. Based
- on ACPI code in create_dsdt_dino_resource(), soc_acpi.c: */
+ on ACPI code in create_dsdt_ioat_resource(), soc_acpi.c: */
resource_t mem64_base, mem64_limit, bus_base, bus_limit;
/* CPM0 */
diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c
index a48302cf2ebc..ca1cdf993c81 100644
--- a/src/soc/intel/xeon_sp/spr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c
@@ -189,7 +189,7 @@ static void create_dsdt_iou_cxl_resource(uint8_t socket, uint8_t stack, const ST
acpigen_pop_len();
}
-static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
+static void create_dsdt_ioat_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
{
if (!stack_enabled)
return;
@@ -381,7 +381,7 @@ void uncore_fill_ssdt(const struct device *device)
stack_enabled);
create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
} else if (stack >= IioStack8 && stack <= IioStack11) { // TYPE_DINO
- create_dsdt_dino_resource(socket, stack, ri, stack_enabled);
+ create_dsdt_ioat_resource(socket, stack, ri, stack_enabled);
create_dsdt_stack_sta(socket, stack, ri, stack_enabled);
} else if (stack == IioStack13) { // TYPE_UBOX
create_dsdt_ubox_resource(socket, stack, ri, stack_enabled);
diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c
index a2516dfef848..344fa5b3399c 100644
--- a/src/soc/intel/xeon_sp/spr/soc_util.c
+++ b/src/soc/intel/xeon_sp/spr/soc_util.c
@@ -78,6 +78,11 @@ bool is_ubox_stack_res(const STACK_RES *res)
return res->Personality == TYPE_UBOX;
}
+bool is_ioat_iio_stack_res(const STACK_RES *res)
+{
+ return res->Personality == TYPE_DINO;
+}
+
/*
* Given a stack resource, figure out whether the corresponding stack has
* CXL device.
diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c
index 75b281bd8d5d..e3915b5ffbd6 100644
--- a/src/soc/intel/xeon_sp/uncore_acpi.c
+++ b/src/soc/intel/xeon_sp/uncore_acpi.c
@@ -335,9 +335,8 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket,
#endif
}
-#if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)
- // Add DINO End Points (with memory resources. We don't report every End Point device.)
- if (ri->Personality == TYPE_DINO) {
+ // Add IOAT End Points (with memory resources. We don't report every End Point device.)
+ if (is_ioat_iio_stack_res(ri)) {
for (int b = ri->BusBase; b <= ri->BusLimit; ++b) {
struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0));
while (dev) {
@@ -357,7 +356,6 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket,
}
}
}
-#endif
// Add HPET
if (socket == 0 && stack == IioStack0) {
@@ -488,9 +486,7 @@ static unsigned long acpi_create_rhsa(unsigned long current)
return current;
}
-/* Skylake-SP doesn't have DINO but not sure how to verify this on CPX */
-#if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)
-static unsigned long xeonsp_create_satc_dino(unsigned long current, const STACK_RES *ri)
+static unsigned long xeonsp_create_satc_ioat(unsigned long current, const STACK_RES *ri)
{
for (int b = ri->BusBase; b <= ri->BusLimit; ++b) {
struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0));
@@ -517,22 +513,21 @@ static unsigned long acpi_create_satc(unsigned long current, const IIO_UDS *hob)
// Add the SATC header
current += acpi_create_dmar_satc(current, 0, 0);
- // Find the DINO devices on each socket
+ // Find the IOAT devices on each socket
for (int socket = CONFIG_MAX_SOCKET - 1; socket >= 0; --socket) {
if (!soc_cpu_is_enabled(socket))
continue;
for (int stack = (MAX_LOGIC_IIO_STACK - 1); stack >= 0; --stack) {
const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack];
- // Add the DINO ATS devices to the SATC
- if (ri->Personality == TYPE_DINO)
- current = xeonsp_create_satc_dino(current, ri);
+ // Add the IOAT ATS devices to the SATC
+ if (is_ioat_iio_stack_res(ri))
+ current = xeonsp_create_satc_ioat(current, ri);
}
}
acpi_dmar_satc_fixup(tmp, current);
return current;
}
-#endif
static unsigned long acpi_fill_dmar(unsigned long current)
{
@@ -555,10 +550,9 @@ static unsigned long acpi_fill_dmar(unsigned long current)
// RHSA
current = acpi_create_rhsa(current);
-#if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP)
// SATC
- current = acpi_create_satc(current, hob);
-#endif
+ if (CONFIG(HAVE_IOAT_DOMAINS))
+ current = acpi_create_satc(current, hob);
return current;
}