diff options
| -rw-r--r-- | src/include/acpi/acpi.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/uncore_acpi.c | 4 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h | 5 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h | 7 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h | 5 |
5 files changed, 7 insertions, 18 deletions
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index c39683ed4eca..d6c30c1b5f63 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -409,6 +409,10 @@ typedef struct acpi_srat_lapic { u32 clock_domain; /* _CDM Clock Domain */ } __packed acpi_srat_lapic_t; +#define ACPI_SRAT_MEMORY_ENABLED (1 << 0) +#define ACPI_SRAT_MEMORY_HOT_PLUGGABLE (1 << 1) +#define ACPI_SRAT_MEMORY_NONVOLATILE (1 << 2) + /* SRAT: Memory Affinity Structure */ typedef struct acpi_srat_mem { u8 type; /* Type (1) */ diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index e3915b5ffbd6..51c2e0e13d06 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -132,9 +132,9 @@ static unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem) srat_mem[mmap_index].length_low = (uint32_t)(size & 0xffffffff); srat_mem[mmap_index].length_high = (uint32_t)(size >> 32); srat_mem[mmap_index].proximity_domain = mem_element->SocketId; - srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED; + srat_mem[mmap_index].flags = ACPI_SRAT_MEMORY_ENABLED; if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0) - srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE; + srat_mem[mmap_index].flags |= ACPI_SRAT_MEMORY_NONVOLATILE; ++mmap_index; } diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index f7b5fb5179f5..eef8cc6c24d7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -60,11 +60,6 @@ are permitted provided that the following conditions are met: MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ ) -/* ACPI SRAT Memory Flags */ -#define SRAT_ACPI_MEMORY_ENABLED (1 << 0) -#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) -#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) - #define MEM_TYPE_RESERVED (1 << 8) #define MEM_ADDR_64MB_SHIFT_BITS 26 diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h index 9f04b93aa189..89897bcc7a26 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h @@ -45,11 +45,6 @@ are permitted provided that the following conditions are met: #define MEMTYPE_2LM_MASK (1 << 1) #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) -/* ACPI SRAT Memory Flags */ -#define SRAT_ACPI_MEMORY_ENABLED (1 << 0) -#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) -#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) - #define MEM_TYPE_RESERVED (1 << 8) #define MEM_ADDR_64MB_SHIFT_BITS 26 @@ -68,4 +63,4 @@ are permitted provided that the following conditions are met: // #define MAX_SAD_RULES 16 // #define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform -#endif
\ No newline at end of file +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h index 954e43ce1ae2..3440ab746158 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h @@ -46,11 +46,6 @@ are permitted provided that the following conditions are met: MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ ) -/* ACPI SRAT Memory Flags */ -#define SRAT_ACPI_MEMORY_ENABLED (1 << 0) -#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) -#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) - #define MEM_TYPE_RESERVED (1 << 8) #define MEM_ADDR_64MB_SHIFT_BITS 26 |