diff options
| -rw-r--r-- | src/mainboard/google/octopus/variants/baseboard/gpio.c | 13 | ||||
| -rw-r--r-- | src/mainboard/google/octopus/variants/garg/gpio.c | 43 | ||||
| -rw-r--r-- | src/mainboard/google/octopus/variants/garg/variant.c | 47 |
3 files changed, 103 insertions, 0 deletions
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 82f4ee1618ff..b3145d10dfcb 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -331,6 +331,19 @@ static const struct pad_config early_gpio_table[] = { */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1, ENPU), /* ESPI_IO1 */ + + /* GPIO_67 and GPIO_117 are in early_gpio_table and gpio_table. For variants + * having LTE SKUs, these two GPIOs would be overridden to output high first + * in the bootblock then be set to default state in gpio_table for non-LTE + * SKUs and keep to output high for LTE SKUs in ramstage. + */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */ + /* GPIO_161 is in early_gpio_table and gpio_table because LTE SKU needs + * to override this pin to output low then high respectively in two + * stages. + */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ }; const struct pad_config *__weak diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 90601ce850a8..36fde90631df 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -50,6 +50,28 @@ static const struct pad_config hdmi_override_table[] = { DISPUPD), PAD_NC(GPIO_213, DN_20K), + +}; + +static const struct pad_config lte_override_table[] = { + /* Default override table. */ + PAD_NC(GPIO_104, UP_20K), + + /* EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_146, 0, DEEP, NONE, Tx0RxDCRx0, + DISPUPD), + + PAD_NC(GPIO_213, DN_20K), + + /* Be specific to LTE SKU */ + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 1, DEEP), }; const struct pad_config *variant_override_gpio_table(size_t *num) @@ -61,8 +83,29 @@ const struct pad_config *variant_override_gpio_table(size_t *num) case SKU_9_HDMI: *num = ARRAY_SIZE(hdmi_override_table); return hdmi_override_table; + case SKU_17_LTE: + *num = ARRAY_SIZE(lte_override_table); + return lte_override_table; default: *num = ARRAY_SIZE(default_override_table); return default_override_table; } } + +static const struct pad_config lte_early_override_table[] = { + /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + PAD_CFG_GPO(GPIO_67, 1, PWROK), + + /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + PAD_CFG_GPO(GPIO_117, 1, PWROK), + + /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + PAD_CFG_GPO(GPIO_161, 0, DEEP), +}; + +const struct pad_config *variant_early_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(lte_early_override_table); + + return lte_early_override_table; +} diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index a3efe3f8021c..2754e640f9d8 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -13,10 +13,13 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <boardid.h> #include <ec/google/chromeec/ec.h> #include <drivers/intel/gma/opregion.h> #include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> enum { SKU_1_2A2C = 1, @@ -24,6 +27,34 @@ enum { SKU_17_LTE = 17, }; +struct gpio_with_delay { + gpio_t gpio; + unsigned int delay_msecs; +}; + +static void power_off_lte_module(u8 slp_typ) +{ + const struct gpio_with_delay lte_power_off_gpios[] = { + { + GPIO_161, /* AVS_I2S1_MCLK -- PLT_RST_LTE_L */ + 30, + }, + { + GPIO_117, /* PCIE_WAKE1_B -- FULL_CARD_POWER_OFF */ + 100 + }, + { + GPIO_67, /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */ + 0 + } + }; + + for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { + gpio_output(lte_power_off_gpios[i].gpio, 0); + mdelay(lte_power_off_gpios[i].delay_msecs); + } +} + const char *mainboard_vbt_filename(void) { uint32_t sku_id; @@ -37,3 +68,19 @@ const char *mainboard_vbt_filename(void) return "vbt.bin"; } } + +void variant_smi_sleep(u8 slp_typ) +{ + /* Currently use cases here all target to S5 therefore we do early return + * here for saving one transaction to the EC for getting SKU ID. */ + if (slp_typ != ACPI_S5) + return; + + switch (get_board_sku()) { + case SKU_17_LTE: + power_off_lte_module(slp_typ); + return; + default: + return; + } +} |