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-rw-r--r--arch/x86/secondary.S28
1 files changed, 26 insertions, 2 deletions
diff --git a/arch/x86/secondary.S b/arch/x86/secondary.S
index 7d795cfd3976..4fa6f4e17027 100644
--- a/arch/x86/secondary.S
+++ b/arch/x86/secondary.S
@@ -28,28 +28,52 @@ _secondary_start:
.code16
.balign 4096
cli
- movl $1b, %ebx
+ movw $0xdead, 0
+ movw $0xbeef, 2
xorl %eax, %eax
movl %eax, %cr3 /* Invalidate TLB*/
/* On hyper threaded cpus, invalidating the cache here is
* very very bad. Don't.
*/
+ movw $0, 0
+ movl $1b, %ebx
+ movw $1, 0
+ movw $2, 0
/* setup the data segment */
movw %cs, %ax
+ movw %ax, 2
+ movw $3, 0
movw %ax, %ds
+ movw $4, 0
+ /* past this point, "0" means ds:0, i.e. cs:0, or the
+ * segment part of the address.
+ */
data32 lgdt gdtaddr - _secondary_start
+// data32 lgdt %cs:gdtptr
+ movw $5, 0
movl %cr0, %eax
+ movw $6, 0
andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+ movw $7, 0
orl $0x60000001, %eax /* CD, NW, PE = 1 */
+ movw $8, 0
movl %eax, %cr0
+ movw $9, 0
+ hlt
+ /* tested to this point but not past it */
- ljmpl $0x10, $1f
+ /* I am pretty sure this just jumps back into
+ * ROM; it's an abs jump
+ */
+ data32 ljmp $0x10, $secondary32
+ movw $0xa, 0
1:
.code32
secondary32:
+ hlt
movw $0x18, %ax
movw %ax, %ds
movw %ax, %es