diff options
Diffstat (limited to 'southbridge/amd/cs5536/cs5536.c')
| -rw-r--r-- | southbridge/amd/cs5536/cs5536.c | 53 |
1 files changed, 1 insertions, 52 deletions
diff --git a/southbridge/amd/cs5536/cs5536.c b/southbridge/amd/cs5536/cs5536.c index 5e4af9d1d41d..0113a0a37a4c 100644 --- a/southbridge/amd/cs5536/cs5536.c +++ b/southbridge/amd/cs5536/cs5536.c @@ -88,7 +88,7 @@ static const u32 FlashPort[] = { * bits 24 -> 30 reserved and set to zero * bit 31 triggers the config cycle */ -static void hide_vpci(u32 vpci_devid) +void hide_vpci(u32 vpci_devid) { printk(BIOS_DEBUG, "Hiding VPCI device: 0x%08X (%02x:%02x.%01x)\n", vpci_devid, (vpci_devid >> 16) & 0xff, @@ -98,43 +98,6 @@ static void hide_vpci(u32 vpci_devid) } /** - * Enables the FLASH PCI header when NAND device existing in mainboard device - * tree. Used when the mainboard has a FLASH part instead of an IDE drive and - * that fact is expressed in the mainboard device tree. - * Must be called after VSA init but before PCI scans to enable the flash - * PCI device header early enough - that is .phase2_fixup of the device. - * - * @param dev The device. - */ -static void nand_phase2(struct device *dev) -{ - if (dev->enabled) { - /* Tell VSA to use FLASH PCI header. Not IDE header. */ - hide_vpci(0x800079C4); - } -} - -static void nand_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - - /* All memory accesses in the range of 0xF0000000 - 0xFFFFFFFF routed to - * Diverse Integration Logic (DIVIL) get always sent to the device inside - * DIVIL as set in DIVIL_BALL_OPTS PRI_BOOT_LOC and SEC_BOOT_LOC bits - * (see CS5536 data book chapter 6.6.2.10 DIVIL_BALL_OPTS PRI_BOOT_LOC - * description). - * The virtual PCI address limit test gives us a false upper limit of - * 0xFFFFFFFF for this device, but we do not want NAND Flash to be using - * memory addresses 0xF0000000 and above as those accesses would end up - * somewhere else instead. Therefore if VSA2 gave us a MMIO resource for - * NAND Flash, patch this (fixed) resources higher bound to 0xEFFFFFFF. - */ - if ((dev->resources >= 1) && (dev->resource[0].flags & IORESOURCE_MEM) && - (dev->resource[0].limit > 0xefffffff)) - dev->resource[0].limit = 0xefffffff; -} - -/** * Power button setup. * * Setup GPIO24, it is the external signal for CS5536 vsb_work_aux which @@ -749,17 +712,3 @@ struct device_operations cs5536_ide = { .phase6_init = ide_init, .ops_pci = &pci_dev_ops_pci, }; - -struct device_operations cs5536_nand = { - .id = {.type = DEVICE_ID_PCI, - {.pci = {.vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_FLASH}}}, - .constructor = default_device_constructor, - .phase2_fixup = nand_phase2, - .phase3_scan = 0, - .phase4_read_resources = nand_read_resources, - .phase4_set_resources = pci_set_resources, - .phase5_enable_resources = pci_dev_enable_resources, - .phase6_init = 0, /* No Option ROMs */ - .ops_pci = &pci_dev_ops_pci, -}; |