diff options
Diffstat (limited to 'src/drivers/intel/fsp1_1/include/fsp/ramstage.h')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h new file mode 100644 index 000000000000..d6cb895174c6 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTEL_COMMON_RAMSTAGE_H_ +#define _INTEL_COMMON_RAMSTAGE_H_ + +#include <fsp/util.h> +#include <soc/intel/common/util.h> +#include <stdint.h> + +/* Perform Intel silicon init. */ +void intel_silicon_init(void); +/* Called after the silicon init code has run. */ +void soc_after_silicon_init(void); +/* Initialize UPD data before SiliconInit call. */ +void soc_silicon_init_params(SILICON_INIT_UPD *params); +void mainboard_silicon_init_params(SILICON_INIT_UPD *params); +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new); +void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); + +#endif /* _INTEL_COMMON_RAMSTAGE_H_ */ |