diff options
Diffstat (limited to 'src/drivers/intel/fsp1_1/include')
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/gma.h | 182 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/gop.h | 2 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/memmap.h | 51 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/ramstage.h | 39 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/romstage.h | 95 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/stack.h | 35 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/util.h | 2 |
7 files changed, 405 insertions, 1 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/gma.h b/src/drivers/intel/fsp1_1/include/fsp/gma.h new file mode 100644 index 000000000000..64b2a2811e8a --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/gma.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ + diff --git a/src/drivers/intel/fsp1_1/include/fsp/gop.h b/src/drivers/intel/fsp1_1/include/fsp/gop.h index 78d2878917e2..14fafd7cb91a 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/gop.h +++ b/src/drivers/intel/fsp1_1/include/fsp/gop.h @@ -23,7 +23,7 @@ /* GOP support */ #if IS_ENABLED(CONFIG_GOP_SUPPORT) -#include <soc/intel/common/gma.h> +#include <fsp/gma.h> const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); diff --git a/src/drivers/intel/fsp1_1/include/fsp/memmap.h b/src/drivers/intel/fsp1_1/include/fsp/memmap.h new file mode 100644 index 000000000000..3d51539f55a6 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/memmap.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _COMMON_MEMMAP_H_ +#define _COMMON_MEMMAP_H_ + +#include <types.h> + +/* + * mmap_region_granluarity must to return a size which is a positive non-zero + * integer multiple of the SMM size when SMM is in use. When not using SMM, + * this value should be set to 8 MiB. + */ +size_t mmap_region_granluarity(void); + +/* Fills in the arguments for the entire SMM region covered by chipset + * protections. e.g. TSEG. */ +void smm_region(void **start, size_t *size); + +enum { + /* SMM handler area. */ + SMM_SUBREGION_HANDLER, + /* SMM cache region. */ + SMM_SUBREGION_CACHE, + /* Chipset specific area. */ + SMM_SUBREGION_CHIPSET, + /* Total sub regions supported. */ + SMM_SUBREGION_NUM, +}; + +/* Fills in the start and size for the requested SMM subregion. Returns + * 0 on susccess, < 0 on failure. */ +int smm_subregion(int sub, void **start, size_t *size); + +#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h new file mode 100644 index 000000000000..d6cb895174c6 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTEL_COMMON_RAMSTAGE_H_ +#define _INTEL_COMMON_RAMSTAGE_H_ + +#include <fsp/util.h> +#include <soc/intel/common/util.h> +#include <stdint.h> + +/* Perform Intel silicon init. */ +void intel_silicon_init(void); +/* Called after the silicon init code has run. */ +void soc_after_silicon_init(void); +/* Initialize UPD data before SiliconInit call. */ +void soc_silicon_init_params(SILICON_INIT_UPD *params); +void mainboard_silicon_init_params(SILICON_INIT_UPD *params); +void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, + SILICON_INIT_UPD *new); +void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params); + +#endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h new file mode 100644 index 000000000000..272679f8d9b9 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _COMMON_ROMSTAGE_H_ +#define _COMMON_ROMSTAGE_H_ + +#include <stdint.h> +#include <arch/cpu.h> +#include <memory_info.h> +#include <fsp/car.h> +#include <fsp/util.h> +#include <soc/intel/common/util.h> +#include <soc/pei_data.h> +#include <soc/pm.h> /* chip_power_state */ + +struct romstage_params { + unsigned long bist; + struct chipset_power_state *power_state; + struct pei_data *pei_data; + void *chipset_context; +}; + +/* + * FSP Boot Flow: + * 1. src/cpu/x86/16bit/reset.inc + * 2. src/cpu/x86/16bit/entry.inc + * 3. other modules + * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc + * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp + * 6. FSP binary/TempRamInit + * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return + * 8. src/soc/intel/common/romstage.c/romstage_main + * 9 src/soc/.../romstage/.../soc_pre_console_init + * 10 src/console/console.c/console_init + * 11 src/soc/.../romstage/.../soc_romstage_init + * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry + * 13. src/soc/intel/common/romstage.c/romstage_common + * 14 src/soc/.../romstage/.../soc_pre_raminit + * 15. FSP binary/MemoryInit + * 16. src/soc/intel/common/romstage.c/romstage_common - return + * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return + * 18. src/soc/intel/common/romstage.c/romstage_main - return + * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs + * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup + * after call to romstage_main + * 21. FSP binary/TempRamExit + * 22. src/soc/intel/common/romstage.c/romstage_after_car + * 23. FSP binary/SiliconInit + * 24. src/soc/intel/common/romstage.c/romstage_after_car - return + * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback + * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify + * 27. FSP binary/FspNotify + * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback + * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify + * 30. FSP binary/FspNotify + */ + +void mainboard_check_ec_image(struct romstage_params *params); +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params); +void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_save_dimm_info(struct romstage_params *params); +void mainboard_add_dimm_info(struct romstage_params *params, + struct memory_info *mem_info, + int channel, int dimm, int index); +void raminit(struct romstage_params *params); +void report_memory_config(void); +void romstage_common(struct romstage_params *params); +asmlinkage void *romstage_main(FSP_INFO_HEADER *fih); +void *setup_stack_and_mtrrs(void); +void soc_after_ram_init(struct romstage_params *params); +void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, + MEMORY_INIT_UPD *new); +void soc_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *upd); +void soc_pre_ram_init(struct romstage_params *params); + +#endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/stack.h b/src/drivers/intel/fsp1_1/include/fsp/stack.h new file mode 100644 index 000000000000..f5333a7bfcb5 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/stack.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _COMMON_STACK_H_ +#define _COMMON_STACK_H_ + +#include <stdint.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +#endif /* _COMMON_STACK_H_ */ diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index b3772a259837..2905e5998592 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -46,6 +46,8 @@ void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid, const void *hob_start); void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_resource_hob(const EFI_GUID *guid); +void soc_display_upd_value(const char *name, uint32_t size, uint64_t old, + uint64_t new); /* * Relocate FSP entire binary into ram. Returns < 0 on error, 0 on success. * The FSP source is pointed to by region_device and the relocation information |