diff options
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/device.h | 50 | ||||
| -rw-r--r-- | src/include/device/dram/ddr3.h | 20 | ||||
| -rw-r--r-- | src/include/device/dram/ddr4.h | 4 | ||||
| -rw-r--r-- | src/include/device/dram/ddr5.h | 16 | ||||
| -rw-r--r-- | src/include/device/pci_ids.h | 85 | ||||
| -rw-r--r-- | src/include/device/pci_rom.h | 1 |
6 files changed, 157 insertions, 19 deletions
diff --git a/src/include/device/device.h b/src/include/device/device.h index ac7e86917eff..1b2e097772a9 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -193,6 +193,7 @@ bool is_enabled_cpu(const struct device *cpu); bool is_pci(const struct device *pci); bool is_enabled_pci(const struct device *pci); bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus); +bool is_pci_bridge(const struct device *pci); /* Returns whether there is a hotplug port on the path to the given device. */ bool dev_path_hotplug(const struct device *); @@ -262,7 +263,7 @@ void mmconf_resource(struct device *dev, unsigned long index); /* These are temporary resource constructors to get us through the migration away from open-coding all the IORESOURCE_FLAGS. */ -const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index, +const struct resource *resource_range_idx(struct device *dev, unsigned long index, uint64_t base, uint64_t size, unsigned long flags); @@ -271,7 +272,8 @@ const struct resource *fixed_mem_range_flags(struct device *dev, unsigned long i uint64_t base, uint64_t size, unsigned long flags) { - return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_MEM | flags); + return resource_range_idx(dev, index, base, size, + IORESOURCE_FIXED | IORESOURCE_MEM | flags); } static inline @@ -284,6 +286,24 @@ const struct resource *fixed_mem_from_to_flags(struct device *dev, unsigned long } static inline +const struct resource *domain_mem_window_range(struct device *dev, unsigned long index, + uint64_t base, uint64_t size) +{ + return resource_range_idx(dev, index, base, size, + IORESOURCE_MEM | IORESOURCE_BRIDGE); +} + +static inline +const struct resource *domain_mem_window_from_to(struct device *dev, unsigned long index, + uint64_t base, uint64_t end) +{ + if (end <= base) + return NULL; + return domain_mem_window_range(dev, index, base, end - base); +} + + +static inline const struct resource *ram_range(struct device *dev, unsigned long index, uint64_t base, uint64_t size) { @@ -343,15 +363,18 @@ static inline const struct resource *fixed_io_range_flags(struct device *dev, unsigned long index, uint16_t base, uint16_t size, unsigned long flags) { - return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_IO | flags); + return resource_range_idx(dev, index, base, size, + IORESOURCE_FIXED | IORESOURCE_IO | flags); } static inline const struct resource *fixed_io_from_to_flags(struct device *dev, unsigned long index, - uint16_t base, uint16_t end, unsigned long flags) + uint16_t base, uint32_t end, unsigned long flags) { if (end <= base) return NULL; + if (end > UINT16_MAX + 1) + return NULL; return fixed_io_range_flags(dev, index, base, end - base, flags); } @@ -362,6 +385,25 @@ const struct resource *fixed_io_range_reserved(struct device *dev, unsigned long return fixed_io_range_flags(dev, index, base, size, IORESOURCE_RESERVE); } +static inline +const struct resource *domain_io_window_range(struct device *dev, unsigned long index, + uint16_t base, uint16_t size) +{ + return resource_range_idx(dev, index, base, size, + IORESOURCE_IO | IORESOURCE_BRIDGE); +} + +static inline +const struct resource *domain_io_window_from_to(struct device *dev, unsigned long index, + uint16_t base, uint32_t end) +{ + if (end <= base) + return NULL; + if (end > UINT16_MAX + 1) + return NULL; + return domain_io_window_range(dev, index, base, end - base); +} + /* Compatibility code */ static inline void fixed_mem_resource_kb(struct device *dev, unsigned long index, diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 6efe0494dfbf..c4fd253efd5b 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -27,12 +27,12 @@ * * @{ */ -#define SPD_DIMM_MOD_ID1 117 -#define SPD_DIMM_MOD_ID2 118 -#define SPD_DIMM_SERIAL_NUM 122 -#define SPD_DIMM_SERIAL_LEN 4 -#define SPD_DIMM_PART_NUM 128 -#define SPD_DIMM_PART_LEN 18 +#define SPD_DDR3_MOD_ID1 117 +#define SPD_DDR3_MOD_ID2 118 +#define SPD_DDR3_SERIAL_NUM 122 +#define SPD_DDR3_SERIAL_LEN 4 +#define SPD_DDR3_PART_NUM 128 +#define SPD_DDR3_PART_LEN 18 /** @} */ /* Byte 3 [3:0]: DDR3 Module type information */ @@ -145,7 +145,7 @@ struct dimm_attr_ddr3_st { /* ASCII part number - NULL terminated */ u8 part_number[17]; /* Serial number */ - u8 serial[SPD_DIMM_SERIAL_LEN]; + u8 serial[SPD_DDR3_SERIAL_LEN]; }; enum ddr3_xmp_profile { @@ -153,15 +153,15 @@ enum ddr3_xmp_profile { DDR3_XMP_PROFILE_2 = 1, }; -typedef u8 spd_raw_data[256]; +typedef u8 spd_ddr3_raw_data[SPD_SIZE_MAX_DDR3]; u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); -int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data); +int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd_data); int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type); void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm); int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm, - spd_raw_data spd, + spd_ddr3_raw_data spd, enum ddr3_xmp_profile profile); enum cb_err spd_add_smbios17(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 72102125206e..da7359a253a1 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -64,9 +64,9 @@ struct dimm_attr_ddr4_st { bool ecc_extension; }; -typedef u8 spd_raw_data[512]; +typedef u8 spd_ddr4_raw_data[SPD_SIZE_MAX_DDR4]; -int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd); +int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd); enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h index ff1604a808a4..78d18b24f8ab 100644 --- a/src/include/device/dram/ddr5.h +++ b/src/include/device/dram/ddr5.h @@ -15,6 +15,22 @@ /** Maximum SPD size supported */ #define SPD_SIZE_MAX_DDR5 1024 +enum spd_dimm_type_ddr5 { + SPD_DDR5_DIMM_TYPE_RDIMM = 0x01, + SPD_DDR5_DIMM_TYPE_UDIMM = 0x02, + SPD_DDR5_DIMM_TYPE_SODIMM = 0x03, + SPD_DDR5_DIMM_TYPE_LRDIMM = 0x04, + SPD_DDR5_DIMM_TYPE_MINI_RDIMM = 0x05, + SPD_DDR5_DIMM_TYPE_MINI_UDIMM = 0x06, + SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM = 0x08, + SPD_DDR5_DIMM_TYPE_72B_SO_RDIMM = 0x09, + SPD_DDR5_DIMM_TYPE_SOLDERED_DOWN = 0x0b, + SPD_DDR5_DIMM_TYPE_16B_SO_DIMM = 0x0c, + SPD_DDR5_DIMM_TYPE_32B_SO_RDIMM = 0x0d, + SPD_DDR5_DIMM_TYPE_1DPC = 0x0e, + SPD_DDR5_DIMM_TYPE_2DPC = 0x0f, +}; + /** * Converts DDR5 clock speed in MHz to the standard reported speed in MT/s */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d3ba149afbbd..7c3b55ecdeaf 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2185,6 +2185,7 @@ #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_LNL_ISHB 0xa845 +#define PCI_DID_INTEL_PTL_ISHB 0xe445 /* Intel 82371FB (PIIX) */ #define PCI_DID_INTEL_82371FB_ISA 0x122e @@ -3166,6 +3167,14 @@ #define PCI_DID_INTEL_LNL_ESPI_5 0xa805 #define PCI_DID_INTEL_LNL_ESPI_6 0xa806 #define PCI_DID_INTEL_LNL_ESPI_7 0xa807 +#define PCI_DID_INTEL_PTL_ESPI_0 0xe400 +#define PCI_DID_INTEL_PTL_ESPI_1 0xe401 +#define PCI_DID_INTEL_PTL_ESPI_2 0xe402 +#define PCI_DID_INTEL_PTL_ESPI_3 0xe403 +#define PCI_DID_INTEL_PTL_ESPI_4 0xe404 +#define PCI_DID_INTEL_PTL_ESPI_5 0xe405 +#define PCI_DID_INTEL_PTL_ESPI_6 0xe406 +#define PCI_DID_INTEL_PTL_ESPI_7 0xe407 /* Intel PCIE device ids */ #define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3176,6 +3185,14 @@ #define PCI_DID_INTEL_LPT_H_PCIE_RP6 0x8c1a #define PCI_DID_INTEL_LPT_H_PCIE_RP7 0x8c1c #define PCI_DID_INTEL_LPT_H_PCIE_RP8 0x8c1e +#define PCI_DID_INTEL_LPT_H_PCIE_RP1_9 0x8c90 +#define PCI_DID_INTEL_LPT_H_PCIE_RP2_9 0x8c92 +#define PCI_DID_INTEL_LPT_H_PCIE_RP3_9 0x8c94 +#define PCI_DID_INTEL_LPT_H_PCIE_RP4_9 0x8c96 +#define PCI_DID_INTEL_LPT_H_PCIE_RP5_9 0x8c98 +#define PCI_DID_INTEL_LPT_H_PCIE_RP6_9 0x8c9a +#define PCI_DID_INTEL_LPT_H_PCIE_RP7_9 0x8c9c +#define PCI_DID_INTEL_LPT_H_PCIE_RP8_9 0x8c9e #define PCI_DID_INTEL_LPT_LP_PCIE_RP1 0x9c10 #define PCI_DID_INTEL_LPT_LP_PCIE_RP2 0x9c12 #define PCI_DID_INTEL_LPT_LP_PCIE_RP3 0x9c14 @@ -3528,6 +3545,14 @@ #define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d #define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e #define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f +#define PCI_DID_INTEL_PTL_PCIE_RP1 0xe438 +#define PCI_DID_INTEL_PTL_PCIE_RP2 0xe439 +#define PCI_DID_INTEL_PTL_PCIE_RP3 0xe43a +#define PCI_DID_INTEL_PTL_PCIE_RP4 0xe43b +#define PCI_DID_INTEL_PTL_PCIE_RP5 0xe43c +#define PCI_DID_INTEL_PTL_PCIE_RP6 0xe43d +#define PCI_DID_INTEL_PTL_PCIE_RP7 0xe43e +#define PCI_DID_INTEL_PTL_PCIE_RP8 0xe43f #define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38 #define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39 @@ -3672,6 +3697,7 @@ #define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_LNL_PMC 0xa821 +#define PCI_DID_INTEL_PTL_PMC 0xe421 /* Intel I2C device Ids */ #define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61 @@ -3803,6 +3829,13 @@ #define PCI_DID_INTEL_LNL_I2C4 0xa850 #define PCI_DID_INTEL_LNL_I2C5 0xa851 +#define PCI_DID_INTEL_PTL_I2C0 0xe478 +#define PCI_DID_INTEL_PTL_I2C1 0xe479 +#define PCI_DID_INTEL_PTL_I2C2 0xe47a +#define PCI_DID_INTEL_PTL_I2C3 0xe47b +#define PCI_DID_INTEL_PTL_I2C4 0xe450 +#define PCI_DID_INTEL_PTL_I2C5 0xe451 + /* Intel UART device Ids */ #define PCI_DID_INTEL_LPT_LP_UART0 0x9c63 #define PCI_DID_INTEL_LPT_LP_UART1 0x9c64 @@ -3886,6 +3919,10 @@ #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 +#define PCI_DID_INTEL_PTL_UART0 0xe425 +#define PCI_DID_INTEL_PTL_UART1 0xe426 +#define PCI_DID_INTEL_PTL_UART2 0xe452 + /* Intel SPI device Ids */ #define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65 #define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66 @@ -3985,6 +4022,11 @@ #define PCI_DID_INTEL_LNL_GSPI1 0xa830 #define PCI_DID_INTEL_LNL_GSPI2 0xa846 +#define PCI_DID_INTEL_PTL_HWSEQ_SPI 0xe423 +#define PCI_DID_INTEL_PTL_SPI0 0xe427 +#define PCI_DID_INTEL_PTL_SPI1 0xe430 +#define PCI_DID_INTEL_PTL_SPI2 0xe446 + /* Intel IGD device Ids */ #define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906 @@ -4128,6 +4170,7 @@ #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 +#define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5 #define PCI_DID_INTEL_RPL_HX_GT1 0xa788 #define PCI_DID_INTEL_RPL_HX_GT2 0xa78b #define PCI_DID_INTEL_RPL_HX_GT3 0x4688 @@ -4147,8 +4190,9 @@ #define PCI_DID_INTEL_RPL_U_GT4 0xa7ac #define PCI_DID_INTEL_RPL_U_GT5 0xa7ad #define PCI_DID_INTEL_LNL_M_GT2 0x64a0 -#define PCI_DID_INTEL_TWL_GT1_1 0x46D3 -#define PCI_DID_INTEL_TWL_GT1_2 0x46D4 +#define PCI_DID_INTEL_TWL_GT1_1 0x46d3 +#define PCI_DID_INTEL_TWL_GT1_2 0x46d4 +#define PCI_DID_INTEL_PTL_GT2 0x64a0 /* Intel Northbridge Ids */ #define PCI_DID_INTEL_APL_NB 0x5af0 @@ -4291,6 +4335,8 @@ #define PCI_DID_INTEL_RPL_P_ID_7 0xa70a #define PCI_DID_INTEL_RPL_P_ID_8 0xa716 #define PCI_DID_INTEL_LNL_M_ID 0x6400 +#define PCI_DID_INTEL_LNL_M_ID_1 0x6410 +#define PCI_DID_INTEL_PTL_ID 0xb001 /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4320,6 +4366,7 @@ #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 +#define PCI_DID_INTEL_PTL_SMBUS 0xe422 /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4362,6 +4409,8 @@ #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d #define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831 +#define PCI_DID_INTEL_PTL_XHCI 0xe47d +#define PCI_DID_INTEL_PTL_TCSS_XHCI 0xe431 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4390,6 +4439,8 @@ #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 #define PCI_DID_INTEL_LNL_P2SB2 0xa84c +#define PCI_DID_INTEL_PTL_P2SB 0xe420 +#define PCI_DID_INTEL_PTL_P2SB2 0xe44c /* Intel SRAM device Ids */ #define PCI_DID_INTEL_APL_SRAM 0x5aec @@ -4405,6 +4456,7 @@ #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf #define PCI_DID_INTEL_LNL_SRAM 0xa87f +#define PCI_DID_INTEL_PTL_SRAM 0xe47f /* Intel AUDIO device Ids */ #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 @@ -4471,6 +4523,15 @@ #define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e #define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f +#define PCI_DID_INTEL_PTL_AUDIO_1 0xe428 +#define PCI_DID_INTEL_PTL_AUDIO_2 0xe429 +#define PCI_DID_INTEL_PTL_AUDIO_3 0xe42a +#define PCI_DID_INTEL_PTL_AUDIO_4 0xe42b +#define PCI_DID_INTEL_PTL_AUDIO_5 0xe42c +#define PCI_DID_INTEL_PTL_AUDIO_6 0xe42d +#define PCI_DID_INTEL_PTL_AUDIO_7 0xe42e +#define PCI_DID_INTEL_PTL_AUDIO_8 0xe42f + /* Intel HECI/ME device Ids */ #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba @@ -4516,6 +4577,10 @@ #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 #define PCI_DID_INTEL_LNL_CSE0 0xa870 +#define PCI_DID_INTEL_PTL_CSE0 0xe470 +#define PCI_DID_INTEL_PTL_CSE1 0xe471 +#define PCI_DID_INTEL_PTL_CSE2 0xe474 +#define PCI_DID_INTEL_PTL_CSE3 0xe475 /* Intel XDCI device Ids */ #define PCI_DID_INTEL_APL_XDCI 0x5aaa @@ -4539,6 +4604,7 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 +#define PCI_DID_INTEL_PTL_TCSS_XDCI 0xe432 /* Intel SD device Ids */ #define PCI_DID_INTEL_LPT_LP_SD 0x9c35 @@ -4560,6 +4626,7 @@ /* Intel UFS device Ids */ #define PCI_DID_INTEL_LNL_UFS 0xa847 +#define PCI_DID_INTEL_PTL_UFS 0xe447 /* Intel Thunderbolt device Ids */ #define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23 @@ -4597,8 +4664,11 @@ #define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e #define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f #define PCI_DID_INTEL_LNL_TBT_RP2 0xa860 +#define PCI_DID_INTEL_LNL_TBT_RP3 0xa837 #define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833 #define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834 +#define PCI_DID_INTEL_PTL_TBT_DMA0 0xe433 +#define PCI_DID_INTEL_PTL_TBT_DMA1 0xe434 /* Intel WIFI Ids */ #define PCI_DID_1000_SERIES_WIFI 0x0084 @@ -4631,6 +4701,7 @@ #define PCI_DID_TP_6SERIES_WIFI 0x2725 #define PCI_DID_MP_7SERIES_WIFI 0x272b +/* Intel IPU device IDs */ #define PCI_DID_INTEL_TGL_IPU 0x9a19 #define PCI_DID_INTEL_TGL_H_IPU 0x9a39 #define PCI_DID_INTEL_JSL_IPU 0x4e19 @@ -4639,6 +4710,7 @@ #define PCI_DID_INTEL_MTL_IPU 0x7d19 #define PCI_DID_INTEL_RPL_IPU 0xa75d #define PCI_DID_INTEL_LNL_IPU 0x645d +#define PCI_DID_INTEL_PTL_IPU 0xb05d /* Intel Dynamic Tuning Technology Device */ #define PCI_DID_INTEL_CML_DTT 0x1903 @@ -4698,12 +4770,20 @@ #define PCI_DID_INTEL_LNL_CNVI_WIFI_2 0xa842 #define PCI_DID_INTEL_LNL_CNVI_WIFI_3 0xa843 #define PCI_DID_INTEL_LNL_CNVI_BT 0xa876 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_0 0xe440 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_1 0xe441 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_2 0xe442 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_3 0xe443 +#define PCI_DID_INTEL_PTL_CNVI_BT 0xe476 /* Platform Security Engine */ #define PCI_DID_INTEL_LNL_PSE0 0xa862 #define PCI_DID_INTEL_LNL_PSE1 0xa863 #define PCI_DID_INTEL_LNL_PSE2 0xa864 +/* In-memory Analytics Accelerator device IDs */ +#define PCI_DID_INTEL_LNL_IAA 0x642d + /* Intel Crashlog */ #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d #define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d @@ -4717,6 +4797,7 @@ /* Intel Trace Hub */ #define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 +#define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f /* Intel Ethernet Controller device Ids */ #define PCI_DID_INTEL_EHL_GBE_HOST 0x4B32 diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h index 19728f2225f5..531ec18ffa68 100644 --- a/src/include/device/pci_rom.h +++ b/src/include/device/pci_rom.h @@ -55,7 +55,6 @@ pci_rom_write_acpi_tables(const struct device *device, void pci_rom_ssdt(const struct device *device); -void map_oprom_vendev_rev(u32 *vendev, u8 *rev); u32 map_oprom_vendev(u32 vendev); int verified_boot_should_run_oprom(struct rom_header *rom_header); |