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-rw-r--r--src/include/acpi/acpi.h7
-rw-r--r--src/include/acpi/acpigen_pci.h11
-rw-r--r--src/include/arch-generic/io.h96
-rw-r--r--src/include/bootstate.h1
-rw-r--r--src/include/cpu/intel/cpu_ids.h2
-rw-r--r--src/include/cpu/x86/pae.h22
-rw-r--r--src/include/device/device.h50
-rw-r--r--src/include/device/dram/ddr3.h20
-rw-r--r--src/include/device/dram/ddr4.h4
-rw-r--r--src/include/device/dram/ddr5.h16
-rw-r--r--src/include/device/pci_ids.h85
-rw-r--r--src/include/device/pci_rom.h1
-rw-r--r--src/include/device_tree.h35
-rw-r--r--src/include/efi/efi_datatype.h16
-rw-r--r--src/include/rmodule.h1
-rw-r--r--src/include/smbios.h16
-rw-r--r--src/include/spd.h37
-rw-r--r--src/include/spd_bin.h9
-rw-r--r--src/include/stdarg.h3
-rw-r--r--src/include/stdio.h3
-rw-r--r--src/include/string.h10
21 files changed, 353 insertions, 92 deletions
diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h
index d6c30c1b5f63..4a71aef67eae 100644
--- a/src/include/acpi/acpi.h
+++ b/src/include/acpi/acpi.h
@@ -458,6 +458,9 @@ typedef struct acpi_madt {
u32 flags; /* Multiple APIC flags */
} __packed acpi_madt_t;
+/* MADT Feature Flags */
+#define ACPI_MADT_PCAT_COMPAT (1 << 0)
+
/*
* LPIT (Low Power Idle Table)
* Conforms to "Intel Low Power S0 Idle" specification, rev 002 from July 2017.
@@ -723,6 +726,10 @@ typedef struct acpi_madt_lapic {
#define ACPI_MADT_MAX_LAPIC_ID 0xfe
+/* MADT Local APIC Feature Flags */
+#define ACPI_MADT_LAPIC_ENABLED (1 << 0)
+#define ACPI_MADT_LAPIC_ONLINE_CAPABLE (1 << 1)
+
/* MADT: Local APIC NMI Structure */
typedef struct acpi_madt_lapic_nmi {
u8 type; /* Type (4) */
diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h
index 7a07423b7bda..69216ec4fa46 100644
--- a/src/include/acpi/acpigen_pci.h
+++ b/src/include/acpi/acpigen_pci.h
@@ -7,13 +7,6 @@
#include <device/pci_def.h>
#include <device/pci_type.h>
-#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01
-#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02
-#define PCIE_PME_CONTROL 0x04
-#define PCIE_AER_CONTROL 0x08
-#define PCIE_CAP_STRUCTURE_CONTROL 0x10
-#define PCIE_LTR_CONTROL 0x20
-
void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn);
void acpigen_write_ADR_pci_device(const struct device *dev);
@@ -23,8 +16,4 @@ void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin,
void pci_domain_fill_ssdt(const struct device *domain);
-void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain);
-uint32_t soc_get_granted_pci_features(const struct device *domain);
-uint32_t soc_get_granted_cxl_features(const struct device *domain);
-
#endif /* ACPIGEN_PCI_H */
diff --git a/src/include/arch-generic/io.h b/src/include/arch-generic/io.h
new file mode 100644
index 000000000000..5874fc8425f8
--- /dev/null
+++ b/src/include/arch-generic/io.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * I/O device access primitives. Simplified based on related U-Boot code,
+ * which is in turn based on early versions from the Linux kernel:
+ *
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_GENERIC_IO_H__
+#define __ARCH_GENERIC_IO_H__
+
+#include <stdint.h>
+#include <stddef.h>
+#include <endian.h>
+#include <arch/mmio.h>
+
+#define __io(a) (void *)(uintptr_t)(CONFIG_PCI_IOBASE + a)
+
+static inline void outb(uint8_t value, uint16_t port)
+{
+ write8(__io(port), value);
+}
+
+static inline void outw(uint16_t value, uint16_t port)
+{
+ write16(__io(port), cpu_to_le16(value));
+}
+
+static inline void outl(uint32_t value, uint16_t port)
+{
+ write32(__io(port), cpu_to_le32(value));
+}
+
+static inline uint8_t inb(uint16_t port)
+{
+ return read8(__io(port));
+}
+
+static inline uint16_t inw(uint16_t port)
+{
+ return le16_to_cpu(read16(__io(port)));
+}
+
+static inline uint32_t inl(uint16_t port)
+{
+ return le32_to_cpu(read32(__io(port)));
+}
+
+static inline void outsb(uint16_t port, const void *addr, unsigned long count)
+{
+ uint8_t *buf = (uint8_t *)addr;
+ while (count--)
+ write8(__io(port), *buf++);
+}
+
+static inline void outsw(uint16_t port, const void *addr, unsigned long count)
+{
+ uint16_t *buf = (uint16_t *)addr;
+ while (count--)
+ write16(__io(port), *buf++);
+}
+
+static inline void outsl(uint16_t port, const void *addr, unsigned long count)
+{
+ uint32_t *buf = (uint32_t *)addr;
+ while (count--)
+ write32(__io(port), *buf++);
+}
+
+static inline void insb(uint16_t port, void *addr, unsigned long count)
+{
+ uint8_t *buf = (uint8_t *)addr;
+ while (count--)
+ *buf++ = read8(__io(port));
+}
+
+static inline void insw(uint16_t port, void *addr, unsigned long count)
+{
+ uint16_t *buf = (uint16_t *)addr;
+ while (count--)
+ *buf++ = read16(__io(port));
+}
+
+static inline void insl(uint16_t port, void *addr, unsigned long count)
+{
+ uint32_t *buf = (uint32_t *)addr;
+ while (count--)
+ *buf++ = read32(__io(port));
+}
+
+#endif
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 30231ce568a6..ab055afae731 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -3,7 +3,6 @@
#define BOOTSTATE_H
#include <assert.h>
-#include <string.h>
#include <stddef.h>
/* Only declare main() when in ramstage. */
#if ENV_RAMSTAGE
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
index ddb4e54c1e85..ae58110e0e72 100644
--- a/src/include/cpu/intel/cpu_ids.h
+++ b/src/include/cpu/intel/cpu_ids.h
@@ -81,5 +81,7 @@
#define CPUID_RAPTORLAKE_J0 0xb06a2
#define CPUID_RAPTORLAKE_Q0 0xb06a3
#define CPUID_LUNARLAKE_A0_1 0xb06d0
+#define CPUID_LUNARLAKE_A0_2 0xb06d1
+#define CPUID_PANTHERLAKE_A0 0xc06c0
#endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h
index e978682798ff..e4b0a2c4c9e4 100644
--- a/src/include/cpu/x86/pae.h
+++ b/src/include/cpu/x86/pae.h
@@ -35,19 +35,15 @@ void paging_set_default_pat(void);
* failure. */
int paging_enable_for_car(const char *pdpt_name, const char *pt_name);
-/* Identity map the region indicated by 'base' and 'size'. Both 'base' and
- * 'size' need to be 4KiB or 2 MiB aligned. 'pat' should be one of the
- * PAT defines above. 0 is returned on success, < 0 on failure. */
-int paging_identity_map_addr(uintptr_t base, size_t size, int pat);
-
-#define MAPPING_ERROR ((void *)0xffffffffUL)
-void *map_2M_page(unsigned long page);
-
-/* To be used with memset_pae */
-#define MEMSET_PAE_VMEM_ALIGN (2 * MiB)
-#define MEMSET_PAE_VMEM_SIZE (2 * MiB)
-#define MEMSET_PAE_PGTL_ALIGN (4 * KiB)
-#define MEMSET_PAE_PGTL_SIZE (20 * KiB)
+/* To be used with memset_pae and pae_map_2M_page */
+#define PAE_VMEM_ALIGN (2 * MiB)
+#define PAE_VMEM_SIZE (2 * MiB)
+#define PAE_PGTL_ALIGN (4 * KiB)
+#define PAE_PGTL_SIZE (20 * KiB)
+
+int init_pae_pagetables(void *pgtbl);
+
+void pae_map_2M_page(void *pgtbl, uint64_t paddr, void *vmem_addr);
int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,
void *vmem_addr);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index ac7e86917eff..1b2e097772a9 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -193,6 +193,7 @@ bool is_enabled_cpu(const struct device *cpu);
bool is_pci(const struct device *pci);
bool is_enabled_pci(const struct device *pci);
bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus);
+bool is_pci_bridge(const struct device *pci);
/* Returns whether there is a hotplug port on the path to the given device. */
bool dev_path_hotplug(const struct device *);
@@ -262,7 +263,7 @@ void mmconf_resource(struct device *dev, unsigned long index);
/* These are temporary resource constructors to get us through the
migration away from open-coding all the IORESOURCE_FLAGS. */
-const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index,
+const struct resource *resource_range_idx(struct device *dev, unsigned long index,
uint64_t base, uint64_t size,
unsigned long flags);
@@ -271,7 +272,8 @@ const struct resource *fixed_mem_range_flags(struct device *dev, unsigned long i
uint64_t base, uint64_t size,
unsigned long flags)
{
- return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_MEM | flags);
+ return resource_range_idx(dev, index, base, size,
+ IORESOURCE_FIXED | IORESOURCE_MEM | flags);
}
static inline
@@ -284,6 +286,24 @@ const struct resource *fixed_mem_from_to_flags(struct device *dev, unsigned long
}
static inline
+const struct resource *domain_mem_window_range(struct device *dev, unsigned long index,
+ uint64_t base, uint64_t size)
+{
+ return resource_range_idx(dev, index, base, size,
+ IORESOURCE_MEM | IORESOURCE_BRIDGE);
+}
+
+static inline
+const struct resource *domain_mem_window_from_to(struct device *dev, unsigned long index,
+ uint64_t base, uint64_t end)
+{
+ if (end <= base)
+ return NULL;
+ return domain_mem_window_range(dev, index, base, end - base);
+}
+
+
+static inline
const struct resource *ram_range(struct device *dev, unsigned long index, uint64_t base,
uint64_t size)
{
@@ -343,15 +363,18 @@ static inline
const struct resource *fixed_io_range_flags(struct device *dev, unsigned long index,
uint16_t base, uint16_t size, unsigned long flags)
{
- return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_IO | flags);
+ return resource_range_idx(dev, index, base, size,
+ IORESOURCE_FIXED | IORESOURCE_IO | flags);
}
static inline
const struct resource *fixed_io_from_to_flags(struct device *dev, unsigned long index,
- uint16_t base, uint16_t end, unsigned long flags)
+ uint16_t base, uint32_t end, unsigned long flags)
{
if (end <= base)
return NULL;
+ if (end > UINT16_MAX + 1)
+ return NULL;
return fixed_io_range_flags(dev, index, base, end - base, flags);
}
@@ -362,6 +385,25 @@ const struct resource *fixed_io_range_reserved(struct device *dev, unsigned long
return fixed_io_range_flags(dev, index, base, size, IORESOURCE_RESERVE);
}
+static inline
+const struct resource *domain_io_window_range(struct device *dev, unsigned long index,
+ uint16_t base, uint16_t size)
+{
+ return resource_range_idx(dev, index, base, size,
+ IORESOURCE_IO | IORESOURCE_BRIDGE);
+}
+
+static inline
+const struct resource *domain_io_window_from_to(struct device *dev, unsigned long index,
+ uint16_t base, uint32_t end)
+{
+ if (end <= base)
+ return NULL;
+ if (end > UINT16_MAX + 1)
+ return NULL;
+ return domain_io_window_range(dev, index, base, end - base);
+}
+
/* Compatibility code */
static inline void fixed_mem_resource_kb(struct device *dev, unsigned long index,
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 6efe0494dfbf..c4fd253efd5b 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -27,12 +27,12 @@
*
* @{
*/
-#define SPD_DIMM_MOD_ID1 117
-#define SPD_DIMM_MOD_ID2 118
-#define SPD_DIMM_SERIAL_NUM 122
-#define SPD_DIMM_SERIAL_LEN 4
-#define SPD_DIMM_PART_NUM 128
-#define SPD_DIMM_PART_LEN 18
+#define SPD_DDR3_MOD_ID1 117
+#define SPD_DDR3_MOD_ID2 118
+#define SPD_DDR3_SERIAL_NUM 122
+#define SPD_DDR3_SERIAL_LEN 4
+#define SPD_DDR3_PART_NUM 128
+#define SPD_DDR3_PART_LEN 18
/** @} */
/* Byte 3 [3:0]: DDR3 Module type information */
@@ -145,7 +145,7 @@ struct dimm_attr_ddr3_st {
/* ASCII part number - NULL terminated */
u8 part_number[17];
/* Serial number */
- u8 serial[SPD_DIMM_SERIAL_LEN];
+ u8 serial[SPD_DDR3_SERIAL_LEN];
};
enum ddr3_xmp_profile {
@@ -153,15 +153,15 @@ enum ddr3_xmp_profile {
DDR3_XMP_PROFILE_2 = 1,
};
-typedef u8 spd_raw_data[256];
+typedef u8 spd_ddr3_raw_data[SPD_SIZE_MAX_DDR3];
u16 spd_ddr3_calc_crc(u8 *spd, int len);
u16 spd_ddr3_calc_unique_crc(u8 *spd, int len);
-int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_raw_data spd_data);
+int spd_decode_ddr3(struct dimm_attr_ddr3_st *dimm, spd_ddr3_raw_data spd_data);
int spd_dimm_is_registered_ddr3(enum spd_dimm_type_ddr3 type);
void dram_print_spd_ddr3(const struct dimm_attr_ddr3_st *dimm);
int spd_xmp_decode_ddr3(struct dimm_attr_ddr3_st *dimm,
- spd_raw_data spd,
+ spd_ddr3_raw_data spd,
enum ddr3_xmp_profile profile);
enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
const u16 selected_freq,
diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h
index 72102125206e..da7359a253a1 100644
--- a/src/include/device/dram/ddr4.h
+++ b/src/include/device/dram/ddr4.h
@@ -64,9 +64,9 @@ struct dimm_attr_ddr4_st {
bool ecc_extension;
};
-typedef u8 spd_raw_data[512];
+typedef u8 spd_ddr4_raw_data[SPD_SIZE_MAX_DDR4];
-int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd);
+int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_ddr4_raw_data spd);
enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot,
const u16 selected_freq,
diff --git a/src/include/device/dram/ddr5.h b/src/include/device/dram/ddr5.h
index ff1604a808a4..78d18b24f8ab 100644
--- a/src/include/device/dram/ddr5.h
+++ b/src/include/device/dram/ddr5.h
@@ -15,6 +15,22 @@
/** Maximum SPD size supported */
#define SPD_SIZE_MAX_DDR5 1024
+enum spd_dimm_type_ddr5 {
+ SPD_DDR5_DIMM_TYPE_RDIMM = 0x01,
+ SPD_DDR5_DIMM_TYPE_UDIMM = 0x02,
+ SPD_DDR5_DIMM_TYPE_SODIMM = 0x03,
+ SPD_DDR5_DIMM_TYPE_LRDIMM = 0x04,
+ SPD_DDR5_DIMM_TYPE_MINI_RDIMM = 0x05,
+ SPD_DDR5_DIMM_TYPE_MINI_UDIMM = 0x06,
+ SPD_DDR5_DIMM_TYPE_72B_SO_UDIMM = 0x08,
+ SPD_DDR5_DIMM_TYPE_72B_SO_RDIMM = 0x09,
+ SPD_DDR5_DIMM_TYPE_SOLDERED_DOWN = 0x0b,
+ SPD_DDR5_DIMM_TYPE_16B_SO_DIMM = 0x0c,
+ SPD_DDR5_DIMM_TYPE_32B_SO_RDIMM = 0x0d,
+ SPD_DDR5_DIMM_TYPE_1DPC = 0x0e,
+ SPD_DDR5_DIMM_TYPE_2DPC = 0x0f,
+};
+
/**
* Converts DDR5 clock speed in MHz to the standard reported speed in MT/s
*/
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d3ba149afbbd..7c3b55ecdeaf 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2185,6 +2185,7 @@
#define PCI_DID_INTEL_ADL_N_ISHB 0x54fc
#define PCI_DID_INTEL_ADL_P_ISHB 0x51fc
#define PCI_DID_INTEL_LNL_ISHB 0xa845
+#define PCI_DID_INTEL_PTL_ISHB 0xe445
/* Intel 82371FB (PIIX) */
#define PCI_DID_INTEL_82371FB_ISA 0x122e
@@ -3166,6 +3167,14 @@
#define PCI_DID_INTEL_LNL_ESPI_5 0xa805
#define PCI_DID_INTEL_LNL_ESPI_6 0xa806
#define PCI_DID_INTEL_LNL_ESPI_7 0xa807
+#define PCI_DID_INTEL_PTL_ESPI_0 0xe400
+#define PCI_DID_INTEL_PTL_ESPI_1 0xe401
+#define PCI_DID_INTEL_PTL_ESPI_2 0xe402
+#define PCI_DID_INTEL_PTL_ESPI_3 0xe403
+#define PCI_DID_INTEL_PTL_ESPI_4 0xe404
+#define PCI_DID_INTEL_PTL_ESPI_5 0xe405
+#define PCI_DID_INTEL_PTL_ESPI_6 0xe406
+#define PCI_DID_INTEL_PTL_ESPI_7 0xe407
/* Intel PCIE device ids */
#define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10
@@ -3176,6 +3185,14 @@
#define PCI_DID_INTEL_LPT_H_PCIE_RP6 0x8c1a
#define PCI_DID_INTEL_LPT_H_PCIE_RP7 0x8c1c
#define PCI_DID_INTEL_LPT_H_PCIE_RP8 0x8c1e
+#define PCI_DID_INTEL_LPT_H_PCIE_RP1_9 0x8c90
+#define PCI_DID_INTEL_LPT_H_PCIE_RP2_9 0x8c92
+#define PCI_DID_INTEL_LPT_H_PCIE_RP3_9 0x8c94
+#define PCI_DID_INTEL_LPT_H_PCIE_RP4_9 0x8c96
+#define PCI_DID_INTEL_LPT_H_PCIE_RP5_9 0x8c98
+#define PCI_DID_INTEL_LPT_H_PCIE_RP6_9 0x8c9a
+#define PCI_DID_INTEL_LPT_H_PCIE_RP7_9 0x8c9c
+#define PCI_DID_INTEL_LPT_H_PCIE_RP8_9 0x8c9e
#define PCI_DID_INTEL_LPT_LP_PCIE_RP1 0x9c10
#define PCI_DID_INTEL_LPT_LP_PCIE_RP2 0x9c12
#define PCI_DID_INTEL_LPT_LP_PCIE_RP3 0x9c14
@@ -3528,6 +3545,14 @@
#define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d
#define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e
#define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f
+#define PCI_DID_INTEL_PTL_PCIE_RP1 0xe438
+#define PCI_DID_INTEL_PTL_PCIE_RP2 0xe439
+#define PCI_DID_INTEL_PTL_PCIE_RP3 0xe43a
+#define PCI_DID_INTEL_PTL_PCIE_RP4 0xe43b
+#define PCI_DID_INTEL_PTL_PCIE_RP5 0xe43c
+#define PCI_DID_INTEL_PTL_PCIE_RP6 0xe43d
+#define PCI_DID_INTEL_PTL_PCIE_RP7 0xe43e
+#define PCI_DID_INTEL_PTL_PCIE_RP8 0xe43f
#define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38
#define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39
@@ -3672,6 +3697,7 @@
#define PCI_DID_INTEL_RPP_P_PMC 0x51a1
#define PCI_DID_INTEL_RPP_S_PMC 0x7a21
#define PCI_DID_INTEL_LNL_PMC 0xa821
+#define PCI_DID_INTEL_PTL_PMC 0xe421
/* Intel I2C device Ids */
#define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61
@@ -3803,6 +3829,13 @@
#define PCI_DID_INTEL_LNL_I2C4 0xa850
#define PCI_DID_INTEL_LNL_I2C5 0xa851
+#define PCI_DID_INTEL_PTL_I2C0 0xe478
+#define PCI_DID_INTEL_PTL_I2C1 0xe479
+#define PCI_DID_INTEL_PTL_I2C2 0xe47a
+#define PCI_DID_INTEL_PTL_I2C3 0xe47b
+#define PCI_DID_INTEL_PTL_I2C4 0xe450
+#define PCI_DID_INTEL_PTL_I2C5 0xe451
+
/* Intel UART device Ids */
#define PCI_DID_INTEL_LPT_LP_UART0 0x9c63
#define PCI_DID_INTEL_LPT_LP_UART1 0x9c64
@@ -3886,6 +3919,10 @@
#define PCI_DID_INTEL_LNL_UART1 0xa826
#define PCI_DID_INTEL_LNL_UART2 0xa852
+#define PCI_DID_INTEL_PTL_UART0 0xe425
+#define PCI_DID_INTEL_PTL_UART1 0xe426
+#define PCI_DID_INTEL_PTL_UART2 0xe452
+
/* Intel SPI device Ids */
#define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65
#define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66
@@ -3985,6 +4022,11 @@
#define PCI_DID_INTEL_LNL_GSPI1 0xa830
#define PCI_DID_INTEL_LNL_GSPI2 0xa846
+#define PCI_DID_INTEL_PTL_HWSEQ_SPI 0xe423
+#define PCI_DID_INTEL_PTL_SPI0 0xe427
+#define PCI_DID_INTEL_PTL_SPI1 0xe430
+#define PCI_DID_INTEL_PTL_SPI2 0xe446
+
/* Intel IGD device Ids */
#define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902
#define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906
@@ -4128,6 +4170,7 @@
#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50
#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55
#define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60
+#define PCI_DID_INTEL_MTL_P_GT2_5 0x7dd5
#define PCI_DID_INTEL_RPL_HX_GT1 0xa788
#define PCI_DID_INTEL_RPL_HX_GT2 0xa78b
#define PCI_DID_INTEL_RPL_HX_GT3 0x4688
@@ -4147,8 +4190,9 @@
#define PCI_DID_INTEL_RPL_U_GT4 0xa7ac
#define PCI_DID_INTEL_RPL_U_GT5 0xa7ad
#define PCI_DID_INTEL_LNL_M_GT2 0x64a0
-#define PCI_DID_INTEL_TWL_GT1_1 0x46D3
-#define PCI_DID_INTEL_TWL_GT1_2 0x46D4
+#define PCI_DID_INTEL_TWL_GT1_1 0x46d3
+#define PCI_DID_INTEL_TWL_GT1_2 0x46d4
+#define PCI_DID_INTEL_PTL_GT2 0x64a0
/* Intel Northbridge Ids */
#define PCI_DID_INTEL_APL_NB 0x5af0
@@ -4291,6 +4335,8 @@
#define PCI_DID_INTEL_RPL_P_ID_7 0xa70a
#define PCI_DID_INTEL_RPL_P_ID_8 0xa716
#define PCI_DID_INTEL_LNL_M_ID 0x6400
+#define PCI_DID_INTEL_LNL_M_ID_1 0x6410
+#define PCI_DID_INTEL_PTL_ID 0xb001
/* Intel SMBUS device Ids */
#define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22
@@ -4320,6 +4366,7 @@
#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
#define PCI_DID_INTEL_LNL_SMBUS 0xa822
+#define PCI_DID_INTEL_PTL_SMBUS 0xe422
/* Intel EHCI device IDs */
#define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26
@@ -4362,6 +4409,8 @@
#define PCI_DID_INTEL_RPP_S_XHCI 0x7a60
#define PCI_DID_INTEL_LNL_XHCI 0xa87d
#define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831
+#define PCI_DID_INTEL_PTL_XHCI 0xe47d
+#define PCI_DID_INTEL_PTL_TCSS_XHCI 0xe431
/* Intel P2SB device Ids */
#define PCI_DID_INTEL_APL_P2SB 0x5a92
@@ -4390,6 +4439,8 @@
#define PCI_DID_INTEL_RPP_S_P2SB 0x7a20
#define PCI_DID_INTEL_LNL_P2SB 0xa820
#define PCI_DID_INTEL_LNL_P2SB2 0xa84c
+#define PCI_DID_INTEL_PTL_P2SB 0xe420
+#define PCI_DID_INTEL_PTL_P2SB2 0xe44c
/* Intel SRAM device Ids */
#define PCI_DID_INTEL_APL_SRAM 0x5aec
@@ -4405,6 +4456,7 @@
#define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf
#define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf
#define PCI_DID_INTEL_LNL_SRAM 0xa87f
+#define PCI_DID_INTEL_PTL_SRAM 0xe47f
/* Intel AUDIO device Ids */
#define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20
@@ -4471,6 +4523,15 @@
#define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e
#define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f
+#define PCI_DID_INTEL_PTL_AUDIO_1 0xe428
+#define PCI_DID_INTEL_PTL_AUDIO_2 0xe429
+#define PCI_DID_INTEL_PTL_AUDIO_3 0xe42a
+#define PCI_DID_INTEL_PTL_AUDIO_4 0xe42b
+#define PCI_DID_INTEL_PTL_AUDIO_5 0xe42c
+#define PCI_DID_INTEL_PTL_AUDIO_6 0xe42d
+#define PCI_DID_INTEL_PTL_AUDIO_7 0xe42e
+#define PCI_DID_INTEL_PTL_AUDIO_8 0xe42f
+
/* Intel HECI/ME device Ids */
#define PCI_DID_INTEL_LPT_H_MEI 0x8c3a
#define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba
@@ -4516,6 +4577,10 @@
#define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d
#define PCI_DID_INTEL_MTL_CSE0 0x7e70
#define PCI_DID_INTEL_LNL_CSE0 0xa870
+#define PCI_DID_INTEL_PTL_CSE0 0xe470
+#define PCI_DID_INTEL_PTL_CSE1 0xe471
+#define PCI_DID_INTEL_PTL_CSE2 0xe474
+#define PCI_DID_INTEL_PTL_CSE3 0xe475
/* Intel XDCI device Ids */
#define PCI_DID_INTEL_APL_XDCI 0x5aaa
@@ -4539,6 +4604,7 @@
#define PCI_DID_INTEL_MTL_XDCI 0x7e7e
#define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1
#define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1
+#define PCI_DID_INTEL_PTL_TCSS_XDCI 0xe432
/* Intel SD device Ids */
#define PCI_DID_INTEL_LPT_LP_SD 0x9c35
@@ -4560,6 +4626,7 @@
/* Intel UFS device Ids */
#define PCI_DID_INTEL_LNL_UFS 0xa847
+#define PCI_DID_INTEL_PTL_UFS 0xe447
/* Intel Thunderbolt device Ids */
#define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23
@@ -4597,8 +4664,11 @@
#define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e
#define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f
#define PCI_DID_INTEL_LNL_TBT_RP2 0xa860
+#define PCI_DID_INTEL_LNL_TBT_RP3 0xa837
#define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833
#define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834
+#define PCI_DID_INTEL_PTL_TBT_DMA0 0xe433
+#define PCI_DID_INTEL_PTL_TBT_DMA1 0xe434
/* Intel WIFI Ids */
#define PCI_DID_1000_SERIES_WIFI 0x0084
@@ -4631,6 +4701,7 @@
#define PCI_DID_TP_6SERIES_WIFI 0x2725
#define PCI_DID_MP_7SERIES_WIFI 0x272b
+/* Intel IPU device IDs */
#define PCI_DID_INTEL_TGL_IPU 0x9a19
#define PCI_DID_INTEL_TGL_H_IPU 0x9a39
#define PCI_DID_INTEL_JSL_IPU 0x4e19
@@ -4639,6 +4710,7 @@
#define PCI_DID_INTEL_MTL_IPU 0x7d19
#define PCI_DID_INTEL_RPL_IPU 0xa75d
#define PCI_DID_INTEL_LNL_IPU 0x645d
+#define PCI_DID_INTEL_PTL_IPU 0xb05d
/* Intel Dynamic Tuning Technology Device */
#define PCI_DID_INTEL_CML_DTT 0x1903
@@ -4698,12 +4770,20 @@
#define PCI_DID_INTEL_LNL_CNVI_WIFI_2 0xa842
#define PCI_DID_INTEL_LNL_CNVI_WIFI_3 0xa843
#define PCI_DID_INTEL_LNL_CNVI_BT 0xa876
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_0 0xe440
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_1 0xe441
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_2 0xe442
+#define PCI_DID_INTEL_PTL_CNVI_WIFI_3 0xe443
+#define PCI_DID_INTEL_PTL_CNVI_BT 0xe476
/* Platform Security Engine */
#define PCI_DID_INTEL_LNL_PSE0 0xa862
#define PCI_DID_INTEL_LNL_PSE1 0xa863
#define PCI_DID_INTEL_LNL_PSE2 0xa864
+/* In-memory Analytics Accelerator device IDs */
+#define PCI_DID_INTEL_LNL_IAA 0x642d
+
/* Intel Crashlog */
#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d
#define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d
@@ -4717,6 +4797,7 @@
/* Intel Trace Hub */
#define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24
+#define PCI_DID_INTEL_RPL_TRACEHUB 0xa76f
/* Intel Ethernet Controller device Ids */
#define PCI_DID_INTEL_EHL_GBE_HOST 0x4B32
diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h
index 19728f2225f5..531ec18ffa68 100644
--- a/src/include/device/pci_rom.h
+++ b/src/include/device/pci_rom.h
@@ -55,7 +55,6 @@ pci_rom_write_acpi_tables(const struct device *device,
void pci_rom_ssdt(const struct device *device);
-void map_oprom_vendev_rev(u32 *vendev, u8 *rev);
u32 map_oprom_vendev(u32 vendev);
int verified_boot_should_run_oprom(struct rom_header *rom_header);
diff --git a/src/include/device_tree.h b/src/include/device_tree.h
index e7b79e1a94f1..bb522bf1da6d 100644
--- a/src/include/device_tree.h
+++ b/src/include/device_tree.h
@@ -4,6 +4,7 @@
#ifndef __DEVICE_TREE_H__
#define __DEVICE_TREE_H__
+#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <commonlib/list.h>
@@ -33,6 +34,7 @@ struct fdt_header {
#define FDT_TOKEN_BEGIN_NODE 1
#define FDT_TOKEN_END_NODE 2
#define FDT_TOKEN_PROPERTY 3
+#define FDT_TOKEN_NOP 4
#define FDT_TOKEN_END 9
#define FDT_PHANDLE_ILLEGAL 0xdeadbeef
@@ -47,6 +49,11 @@ struct fdt_property
* Unflattened device tree structures.
*/
+struct device_tree_region {
+ u64 addr;
+ u64 size;
+};
+
struct device_tree_property
{
struct fdt_property prop;
@@ -91,6 +98,8 @@ struct device_tree
* which were consumed reading the requested value.
*/
+/* Checks if blob points to a valid FDT */
+bool fdt_is_valid(const void *blob);
/* Read the property at offset, if any exists. */
int fdt_next_property(const void *blob, uint32_t offset,
struct fdt_property *prop);
@@ -100,6 +109,32 @@ int fdt_node_name(const void *blob, uint32_t offset, const char **name);
void fdt_print_node(const void *blob, uint32_t offset);
int fdt_skip_node(const void *blob, uint32_t offset);
+/* Read property and put into fdt_prop. Returns offset to property */
+u32 fdt_read_prop(const void *blob, u32 node_offset, const char *prop_name,
+ struct fdt_property *fdt_prop);
+/* Read reg property and save regions inside 'regions'. Returns number of regions read */
+u32 fdt_read_reg_prop(const void *blob, u32 node_offset, u32 addr_cells, u32 size_cells,
+ struct device_tree_region regions[], size_t regions_count);
+/* Find a node by a given path and return the offset */
+u32 fdt_find_node_by_path(const void *blob, const char *path, u32 *addrcp, u32 *sizecp);
+/* Find multiple nodes matching a given pattern. Returns number of nodes found */
+size_t fdt_find_subnodes_by_prefix(const void *blob, u32 node_offset, const char *prefix,
+ u32 *addrcp, u32 *sizecp, u32 results[], size_t results_len);
+/* Find a node by a given alias and return its offset */
+u32 fdt_find_node_by_alias(const void *blob, const char *alias_name,
+ u32 *addr_cells, u32 *size_cells);
+/*
+ * Read the node name into 'name' of the node behind 'node_offset'
+ * and return total bytes used for name
+ */
+int fdt_next_node_name(const void *blob, uint32_t node_offset, const char **name);
+
+ /* Read memory regions from a flat device-tree. */
+size_t fdt_read_memory_regions(const void *blob, struct device_tree_region regions[],
+ size_t regions_count);
+ /* Find top of memory from a flat device-tree. */
+uint64_t fdt_get_memory_top(const void *blob);
+
/* Read a flattened device tree into a hierarchical structure which refers to
the contents of the flattened tree in place. Modifying the flat tree
invalidates the unflattened one. */
diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h
index 0333a84a4e39..d4152af75493 100644
--- a/src/include/efi/efi_datatype.h
+++ b/src/include/efi/efi_datatype.h
@@ -3,6 +3,22 @@
/* Create EFI equivalent datatype in coreboot based on UEFI specification */
#ifndef __EFI_DATATYPE_H__
#define __EFI_DATATYPE_H__
+
+/*
+ * EDK2 EFIAPI macro definition relies on compiler flags such as __GNUC__ which
+ * is not working well when included by coreboot. While it has no side-effect on
+ * i386 because the C calling convention used by coreboot and FSP are the same,
+ * it breaks on x86_64 because FSP/UEFI uses the Microsoft x64 calling
+ * convention while coreboot uses the System V AMD64 ABI.
+ *
+ * Fortunately, EDK2 header allows to override EFIAPI.
+ */
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
+#define EFIAPI __attribute__((regparm(0)))
+#else
+#define EFIAPI __attribute__((__ms_abi__))
+#endif
+
#include <Base.h>
#include <Uefi/UefiBaseType.h>
diff --git a/src/include/rmodule.h b/src/include/rmodule.h
index bf26ad0b70a4..72faecced700 100644
--- a/src/include/rmodule.h
+++ b/src/include/rmodule.h
@@ -4,7 +4,6 @@
#include <stdint.h>
#include <stddef.h>
-#include <string.h>
#include <commonlib/rmodule-defs.h>
enum {
diff --git a/src/include/smbios.h b/src/include/smbios.h
index d4ae662c57cc..8ef37d8c8423 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -70,6 +70,7 @@ const char *smbios_system_version(void);
void smbios_system_set_uuid(u8 *uuid);
const char *smbios_system_sku(void);
+void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count);
unsigned int smbios_cpu_get_max_speed_mhz(void);
unsigned int smbios_cpu_get_current_speed_mhz(void);
unsigned int smbios_cpu_get_voltage(void);
@@ -495,6 +496,15 @@ struct smbios_type4 {
#define SMBIOS_PROCESSOR_STATUS_POPULATED (1 << 6)
#define SMBIOS_PROCESSOR_STATUS_CPU_ENABLED (1 << 0)
+enum smbios_processor_type {
+ SMBIOS_PROCESSOR_TYPE_OTHER = 0x01,
+ SMBIOS_PROCESSOR_TYPE_UNKNOWN = 0x02,
+ SMBIOS_PROCESSOR_TYPE_CENTRAL = 0x03,
+ SMBIOS_PROCESSOR_TYPE_MATH = 0x04,
+ SMBIOS_PROCESSOR_TYPE_DSP = 0x05,
+ SMBIOS_PROCESSOR_TYPE_VIDEO = 0x06,
+};
+
/* enum for socket type */
enum smbios_processor_upgrade_field {
PROCESSOR_UPGRADE_OTHER = 0x01,
@@ -574,7 +584,13 @@ enum smbios_processor_upgrade_field {
/* defines for processor family */
#define SMBIOS_PROCESSOR_FAMILY_OTHER 0x01
#define SMBIOS_PROCESSOR_FAMILY_UNKNOWN 0x02
+#define SMBIOS_PROCESSOR_FAMILY_INTEL486 0x06
+#define SMBIOS_PROCESSOR_FAMILY_PENTIUM_PRO 0x0c
#define SMBIOS_PROCESSOR_FAMILY_XEON 0xb3
+#define SMBIOS_PROCESSOR_FAMILY_FROM_FAMILY2 0xfe
+
+/* defines for processor family 2 */
+#define SMBIOS_PROCESSOR_FAMILY2_ARMV8 0x101
/* defines for processor characteristics */
#define PROCESSOR_64BIT_CAPABLE (1 << 2)
diff --git a/src/include/spd.h b/src/include/spd.h
index 2fe9f968d436..ff7c73ebb5c2 100644
--- a/src/include/spd.h
+++ b/src/include/spd.h
@@ -154,6 +154,13 @@ enum spd_memory_type {
SPD_MEMORY_TYPE_DDR4E_SDRAM = 0x0e,
SPD_MEMORY_TYPE_LPDDR3_SDRAM = 0x0f,
SPD_MEMORY_TYPE_LPDDR4_SDRAM = 0x10,
+ SPD_MEMORY_TYPE_LPDDR4X_SDRAM = 0x11,
+ SPD_MEMORY_TYPE_DDR5_SDRAM = 0x12,
+ SPD_MEMORY_TYPE_LPDDR5_SDRAM = 0x13,
+ SPD_MEMORY_TYPE_DDR5_NVDIMM_P = 0x14,
+ SPD_MEMORY_TYPE_LPDDR5X_SDRAM = 0x15,
+ /* This is not a JEDEC module type ID */
+ SPD_MEMORY_TYPE_LPDDR3_INTEL = 0xf1,
};
/* SPD_MODULE_VOLTAGE values. */
@@ -201,36 +208,6 @@ enum spd_memory_type {
#define SPD_ECC_8BIT (1<<3)
#define SPD_ECC_8BIT_LP5_DDR5 (1<<4)
-/* Byte 3 [3:0]: DDR4 Module type information */
-enum ddr4_module_type {
- DDR4_SPD_RDIMM = 0x01,
- DDR4_SPD_UDIMM = 0x02,
- DDR4_SPD_SODIMM = 0x03,
- DDR4_SPD_LRDIMM = 0x04,
- DDR4_SPD_MINI_RDIMM = 0x05,
- DDR4_SPD_MINI_UDIMM = 0x06,
- DDR4_SPD_72B_SO_RDIMM = 0x08,
- DDR4_SPD_72B_SO_UDIMM = 0x09,
- DDR4_SPD_16B_SO_DIMM = 0x0c,
- DDR4_SPD_32B_SO_RDIMM = 0x0d,
-};
-
-enum ddr5_module_type {
- DDR5_SPD_RDIMM = 0x01,
- DDR5_SPD_UDIMM = 0x02,
- DDR5_SPD_SODIMM = 0x03,
- DDR5_SPD_LRDIMM = 0x04,
- DDR5_SPD_MINI_RDIMM = 0x05,
- DDR5_SPD_MINI_UDIMM = 0x06,
- DDR5_SPD_72B_SO_UDIMM = 0x08,
- DDR5_SPD_72B_SO_RDIMM = 0x09,
- DDR5_SPD_SOLDERED_DOWN = 0x0b,
- DDR5_SPD_16B_SO_DIMM = 0x0c,
- DDR5_SPD_32B_SO_RDIMM = 0x0d,
- DDR5_SPD_1DPC = 0x0e,
- DDR5_SPD_2DPC = 0x0f,
-};
-
enum lpx_module_type {
LPX_SPD_LPDIMM = 0x07,
LPX_SPD_NONDIMM = 0x0e,
diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h
index d0cdefcac147..c51e449559d2 100644
--- a/src/include/spd_bin.h
+++ b/src/include/spd_bin.h
@@ -3,6 +3,7 @@
#ifndef SPD_BIN_H
#define SPD_BIN_H
+#include <device/dram/ddr3.h>
#include <stdint.h>
#include <commonlib/region.h>
@@ -27,11 +28,11 @@
#define DDR3_BUS_DEV_WIDTH 8
#define DDR4_ORGANIZATION 12
#define DDR4_BUS_DEV_WIDTH 13
-#define DDR3_SPD_PART_OFF 128
-#define DDR3_SPD_PART_LEN 18
+#define DDR3_SPD_PART_OFF SPD_DDR3_PART_NUM
+#define DDR3_SPD_PART_LEN SPD_DDR3_PART_LEN
#define DDR3_SPD_SN_OFF 122
-#define LPDDR3_SPD_PART_OFF 128
-#define LPDDR3_SPD_PART_LEN 18
+#define LPDDR3_SPD_PART_OFF SPD_DDR3_PART_NUM
+#define LPDDR3_SPD_PART_LEN SPD_DDR3_PART_LEN
#define DDR4_SPD_PART_OFF 329
#define DDR4_SPD_PART_LEN 20
#define DDR4_SPD_SN_OFF 325
diff --git a/src/include/stdarg.h b/src/include/stdarg.h
index c5a8cd8dbe96..f55fcc3019b6 100644
--- a/src/include/stdarg.h
+++ b/src/include/stdarg.h
@@ -1,8 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/**
- * Note: This file is only for POSIX compatibility, and is meant to be
- * chain-included via string.h.
+ * Note: This file is only for POSIX compatibility.
*/
#ifndef STDARG_H
diff --git a/src/include/stdio.h b/src/include/stdio.h
index d59b9411ee23..fe7cb586681b 100644
--- a/src/include/stdio.h
+++ b/src/include/stdio.h
@@ -1,8 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/**
- * Note: This file is only for POSIX compatibility, and is meant to be
- * chain-included via string.h.
+ * Note: This file is only for POSIX compatibility.
*/
#ifndef STDIO_H
diff --git a/src/include/string.h b/src/include/string.h
index 92ea5e5f7f77..e752f8f531ef 100644
--- a/src/include/string.h
+++ b/src/include/string.h
@@ -3,9 +3,8 @@
#ifndef STRING_H
#define STRING_H
-#include <stdarg.h> /* IWYU pragma: export */
+#include <commonlib/bsd/string.h>
#include <stddef.h>
-#include <stdio.h> /* IWYU pragma: export */
void *memcpy(void *dest, const void *src, size_t n);
void *memmove(void *dest, const void *src, size_t n);
@@ -38,11 +37,4 @@ long atol(const char *str);
*/
char *strrchr(const char *s, int c);
-/*
- * Parses an unsigned integer and moves the input pointer forward to the first
- * character that's not a valid digit. s and *s must not be NULL. Result
- * undefined if it overruns the return type size.
- */
-unsigned int skip_atoi(char **s);
-
#endif /* STRING_H */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-19 06:16:40 +0000