diff options
Diffstat (limited to 'src/mainboard/asrock')
45 files changed, 1207 insertions, 87 deletions
diff --git a/src/mainboard/asrock/b75m-itx/Makefile.mk b/src/mainboard/asrock/b75m-itx/Makefile.mk index d1b484d2175a..ae57dabd07c3 100644 --- a/src/mainboard/asrock/b75m-itx/Makefile.mk +++ b/src/mainboard/asrock/b75m-itx/Makefile.mk @@ -3,6 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c -bootblock-y += early_init.c -romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 59645f04f2f8..8ecae251f6f3 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -27,6 +27,12 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 1, 5}, {1, 1, 5}, {1, 0, 6} + }" device ref xhci on subsystemid 0x1849 0x1e31 diff --git a/src/mainboard/asrock/b75m-itx/early_init.c b/src/mainboard/asrock/b75m-itx/early_init.c deleted file mode 100644 index b70794aebace..000000000000 --- a/src/mainboard/asrock/b75m-itx/early_init.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, - {1, 0, 3}, {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, {1, 1, 5}, {1, 1, 5}, {1, 0, 6}, -}; diff --git a/src/mainboard/asrock/b75m-itx/hda_verb.c b/src/mainboard/asrock/b75m-itx/hda_verb.c index f770512a1b59..37f763ed65b0 100644 --- a/src/mainboard/asrock/b75m-itx/hda_verb.c +++ b/src/mainboard/asrock/b75m-itx/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x18498892, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x18498892), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19850), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01452130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index e2c898d0b86c..1cf501549e64 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -39,6 +39,22 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 } + }" device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 4052b6f22dd3..1ffd896e2657 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -8,23 +8,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c index 0cd7ad47ea65..a3d894d6a1cd 100644 --- a/src/mainboard/asrock/b75pro3-m/hda_verb.c +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x18498892, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x18498892), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19950), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214120), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01452130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c index dc3c1408570f..8b908c516cf3 100644 --- a/src/mainboard/asrock/b85m_pro4/hda_verb.c +++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c @@ -7,15 +7,15 @@ const u32 cim_verb_data[] = { 0x1849c892, /* Subsystem ID */ 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x1849c892), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014020), AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), AZALIA_PIN_CFG(0, 0x1d, 0x598301f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221102f), 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ @@ -23,18 +23,18 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x1458a002), AZALIA_PIN_CFG(2, 0x11, 0x411110f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1f, 0x41c46060), 0x80862806, /* Codec Vendor / Device ID: Intel Haswell HDMI */ diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c index 5fce4333c889..134c34092f16 100644 --- a/src/mainboard/asrock/g41c-gs/hda_verb.c +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -12,15 +12,15 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19830), AZALIA_PIN_CFG(0, 0x19, 0x02a19940), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x02214120), AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* coreboot specific header */ /* Intel Eaglelake HDMI */ @@ -40,15 +40,15 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c30), AZALIA_PIN_CFG(2, 0x19, 0x02a19c40), AZALIA_PIN_CFG(2, 0x1a, 0x0181343f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asrock/h110m/Makefile.mk b/src/mainboard/asrock/h110m/Makefile.mk index e8ff53e6e8f0..65ac73386c65 100644 --- a/src/mainboard/asrock/h110m/Makefile.mk +++ b/src/mainboard/asrock/h110m/Makefile.mk @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -subdirs-y += spd bootblock-y += bootblock.c ramstage-y += mainboard.c diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c index 82cf54523b19..a19634e6f4f3 100644 --- a/src/mainboard/asrock/h110m/hda_verb.c +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -8,19 +8,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10438445), AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014020), AZALIA_PIN_CFG(0, 0x15, 0x90170110), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19040), AZALIA_PIN_CFG(0, 0x19, 0x02a19050), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214030), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4026c629), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 2624c38ebe46..05cb87050bb0 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -21,6 +21,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 } + }" device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 end diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c index 4637378456a4..df8f0436573a 100644 --- a/src/mainboard/asrock/h77pro4-m/early_init.c +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -21,23 +21,6 @@ enum cpu_fan_tach_src { CPU_FAN_HEADER_BOTH }; -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - /* * The tachometer signal that goes to CPUFANIN of the Super I/O is set via * GPIOs. diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c index 51133e7c7c4b..7fbb3310a820 100644 --- a/src/mainboard/asrock/h77pro4-m/hda_verb.c +++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x18498892, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x18498892), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19950), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214120), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01452130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/h81m-hds/hda_verb.c b/src/mainboard/asrock/h81m-hds/hda_verb.c index 5b372bf35048..eea210d1d097 100644 --- a/src/mainboard/asrock/h81m-hds/hda_verb.c +++ b/src/mainboard/asrock/h81m-hds/hda_verb.c @@ -10,14 +10,14 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(1, 0x18497662), AZALIA_PIN_CFG(1, 0x14, 0x01014010), AZALIA_PIN_CFG(1, 0x15, 0x40000000), - AZALIA_PIN_CFG(1, 0x16, 0x411111f0), + AZALIA_PIN_CFG(1, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x18, 0x01a19040), AZALIA_PIN_CFG(1, 0x19, 0x02a19050), AZALIA_PIN_CFG(1, 0x1a, 0x0181304f), AZALIA_PIN_CFG(1, 0x1b, 0x02214020), - AZALIA_PIN_CFG(1, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x1d, 0x40a4c601), - AZALIA_PIN_CFG(1, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/asrock/z87e-itx/Kconfig b/src/mainboard/asrock/z87e-itx/Kconfig new file mode 100644 index 000000000000..9eebc90e68bf --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z87E_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select GFX_GMA_ANALOG_I2C_HDMI_B + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87e-itx" + +config MAINBOARD_PART_NUMBER + default "Z87E-ITX" + +config USBDEBUG_HCD_INDEX + default 1 # This is the top most of the USB-2.0-only ports +endif diff --git a/src/mainboard/asrock/z87e-itx/Kconfig.name b/src/mainboard/asrock/z87e-itx/Kconfig.name new file mode 100644 index 000000000000..f152649b5c99 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z87E_ITX + bool "Z87E-ITX" diff --git a/src/mainboard/asrock/z87e-itx/Makefile.mk b/src/mainboard/asrock/z87e-itx/Makefile.mk new file mode 100644 index 000000000000..058a390189aa --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87e-itx/acpi/ec.asl b/src/mainboard/asrock/z87e-itx/acpi/ec.asl new file mode 100644 index 000000000000..16990d45f428 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87e-itx/acpi/platform.asl b/src/mainboard/asrock/z87e-itx/acpi/platform.asl new file mode 100644 index 000000000000..aff432b6f47a --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87e-itx/acpi/superio.asl b/src/mainboard/asrock/z87e-itx/acpi/superio.asl new file mode 100644 index 000000000000..ee2eabeb756e --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z87e-itx/board_info.txt b/src/mainboard/asrock/z87e-itx/board_info.txt new file mode 100644 index 000000000000..4b2f887d5e79 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z87e-itx/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87e-itx/bootblock.c b/src/mainboard/asrock/z87e-itx/bootblock.c new file mode 100644 index 000000000000..a64cdfb72384 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/z87e-itx/data.vbt b/src/mainboard/asrock/z87e-itx/data.vbt Binary files differnew file mode 100644 index 000000000000..4bb86662ce3f --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/data.vbt diff --git a/src/mainboard/asrock/z87e-itx/devicetree.cb b/src/mainboard/asrock/z87e-itx/devicetree.cb new file mode 100644 index 000000000000..32883e4144f0 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/devicetree.cb @@ -0,0 +1,132 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1849 0x0412 + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gpe0_en_1" = "0x46" + + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1150 + end + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO8 + irq 0xe4 = 0xef # + GPIO8 direction + irq 0xe5 = 0 # + GPIO8 value + end + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 on end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # + GPIO2 direction + end + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on # GPIO5 + irq 0xf4 = 0x7f # + GPIO5 direction + irq 0xf5 = 0x80 # + GPIO5 value + end + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe6 = 0x4c + irq 0xf0 = 0x40 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + irq 0xf7 = 0 # + Front Panel Green LED + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0 # + GPIOA direction + irq 0xe1 = 0 # + GPIOA value + end + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87e-itx/dsdt.asl b/src/mainboard/asrock/z87e-itx/dsdt.asl new file mode 100644 index 000000000000..b62c922dc252 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87e-itx/gma-mainboard.ads b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads new file mode 100644 index 000000000000..cd05ae2fb817 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI1, -- DVI-I + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- DVI-I + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87e-itx/gpio.c b/src/mainboard/asrock/z87e-itx/gpio.c new file mode 100644 index 000000000000..ff9a21db35e7 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87e-itx/hda_verb.c b/src/mainboard/asrock/z87e-itx/hda_verb.c new file mode 100644 index 000000000000..7164c57149f2 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491150, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491150), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87e-itx/romstage.c b/src/mainboard/asrock/z87e-itx/romstage.c new file mode 100644 index 000000000000..b50390e67c53 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig new file mode 100644 index 000000000000..d47e3a204797 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z97_EXTREME6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT + +config CBFS_SIZE + default 0x200000 + +config MAINBOARD_DIR + default "asrock/z97_extreme6" + +config MAINBOARD_PART_NUMBER + default "Z97 Extreme6" + +endif diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig.name b/src/mainboard/asrock/z97_extreme6/Kconfig.name new file mode 100644 index 000000000000..24435876406b --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z97_EXTREME6 + bool "Z97 Extreme6" diff --git a/src/mainboard/asrock/z97_extreme6/Makefile.mk b/src/mainboard/asrock/z97_extreme6/Makefile.mk new file mode 100644 index 000000000000..513c347cbdad --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z97_extreme6/acpi/ec.asl b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl new file mode 100644 index 000000000000..16990d45f428 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z97_extreme6/acpi/platform.asl b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl new file mode 100644 index 000000000000..7da03bfddd02 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asrock/z97_extreme6/acpi/superio.asl b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl new file mode 100644 index 000000000000..ee2eabeb756e --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z97_extreme6/board_info.txt b/src/mainboard/asrock/z97_extreme6/board_info.txt new file mode 100644 index 000000000000..bd0147425432 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z97%20extreme6/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/asrock/z97_extreme6/bootblock.c b/src/mainboard/asrock/z97_extreme6/bootblock.c new file mode 100644 index 000000000000..318cc034f201 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/bootblock.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) +#define GPIO_PP_OD_DEV PNP_DEV(0x2e, NCT6791D_GPIO_PP_OD) + +/* + * Asrock Z97 Extreme6 Super I/O GPIOs + * + * +------+-----+---------------------------+ + * | GPIO | Pin | Description | + * +------+-----+---------------------------+ + * | GP00 | 121 | N/C | + * | GP01 | 122 | CHA_FAN2 PWM output | + * | GP02 | 123 | CHA_FAN3 PWM output | + * | GP03 | 2 | N/C | + * | GP04 | 3 | CHA_FAN3 tach input | + * | GP05 | 4 | CHA_FAN2 tach input | + * | GP06 | 5 | PWR_FAN tach input | + * | GP07 | 6 | N/C (SE_IFDET) | + * +------+-----+---------------------------+ + * | GP10 | 14 | HDD Saver power switch | + * | GP11 | 13 | Assert HDA_SDO (SIO_GP11) | + * | GP12 | 12 | CPU_FAN2 FON# | + * | GP13 | 11 | SATA_SEL (for eSATA) | + * | GP14 | 10 | N/C | + * | GP15 | 9 | N/C (UARTP80_EN) | + * | GP16 | 8 | OTP for VCORE (OTE_GATE1) | + * | GP17 | 7 | LED_EN# | + * +------+-----+---------------------------+ + * | GP20 | 59 | KDAT | + * | GP21 | 58 | KCLK | + * | GP22 | 57 | MDAT | + * | GP23 | 56 | MCLK | + * | GP24 | 95 | SE_DEVSLP (SATA Express) | + * | GP25 | 96 | N/C (SIO_GP25) | + * | GP26 | 53 | N/C | + * | GP27 | 98 | M2_2_SE_IFDET | + * +------+-----+---------------------------+ + * | GP30 | 83 | N/C (RESETCON#) | + * | GP31 | 76 | BIOS_A (or SML1DAT) | + * | GP32 | 75 | BIOS_B (or SML1CLK) | + * | GP33 | 71 | 3VSBSW# | + * | GP34 | 55 | VCORE_OFFSET# | + * | GP35 | 54 | N/C | + * | GP36 | 53 | N/C | + * | GP37 | 7 | LED_EN# | + * +------+-----+---------------------------+ + * | GP40 | 62 | N/C (TEST_EN) | + * | GP41 | 52 | N/C | + * | GP42 | 51 | WLAN1_ON/OFF# | + * | GP43 | 41 | Port 80 display - DGL_0# | + * | GP44 | 40 | PWR_LED gate | + * | GP45 | 39 | HDD_LED gate | + * | GP46 | 38 | CHA_FAN3 FON# | + * | GP47 | 37 | CHA_FAN2 FON# | + * +------+-----+---------------------------+ + * | GP50 | 93 | N/C (SUSWARN#) | + * | GP51 | 92 | CPU_FAN2 tach input | + * | GP52 | 91 | N/C (SUSACK#) | + * | GP53 | 90 | SUSWARN_5VDUAL | + * | GP54 | 89 | SLP_SUS# | + * | GP55 | 88 | SLP_SUS_FET | + * | GP56 | 87 | PEG12V_DET (Molex conn) | + * | GP57 | 86 | PCIE4_SEL (PCIE3 / mPCIe) | + * +------+-----+---------------------------+ + * | GP70 | 69 | N/C (DSW_EN) | + * | GP71 | 68 | N/C | + * | GP72 | 67 | N/C | + * | GP73 | 66 | M.2 / SATA Express select | + * | GP74 | 79 | RESET# of long PCIe ports | + * | GP75 | 78 | RESET# for on-board chips | + * | GP76 | 77 | RESET# SATA Express / M.2 | + * | GP77 | 86 | HDD_LED gate | + * +------+-----+---------------------------+ + * + * HWM voltage inputs + * + * +------+-----+---------------------------+ + * | Name | Pin | Voltage (resistor values) | + * +------+-----+---------------------------+ + * | VIN0 | 104 | +12V (110K / 10K) | + * | VIN1 | 105 | +5V (20K / 10K) | + * | VIN2 | 106 | CPU_VRING | + * | VIN3 | 107 | CPU_VSA | + * | VIN4 | 111 | CPU_VCORE0 | + * | VIN5 | 114 | CPU_VGFX | + * | VIN6 | 115 | V_VCCIOA_LOAD | + * | VIN7 | 116 | N/C | + * | VIN8 | 103 | CPU_VIO | + * +------+-----+---------------------------+ + */ + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0xe6); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x24, 0xfc); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x02); + + /* Select push-pull vs. open-drain output */ + pnp_set_logical_device(GPIO_PP_OD_DEV); + pnp_write_config(GPIO_PP_OD_DEV, 0xe0, 0xfe); + pnp_write_config(GPIO_PP_OD_DEV, 0xe2, 0x79); + pnp_write_config(GPIO_PP_OD_DEV, 0xe6, 0x6f); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z97_extreme6/data.vbt b/src/mainboard/asrock/z97_extreme6/data.vbt Binary files differnew file mode 100644 index 000000000000..6a73a2662626 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/data.vbt diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb new file mode 100644 index 000000000000..2258a1bfd142 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb @@ -0,0 +1,130 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + + # This mainboard has DVI-I + register "gpu_ddi_e_connected" = "1" + + # This mainboard has a DP output + register "gpu_dp_c_hotplug" = "7" + + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1849 0x0c00 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # Bifurcated PEG: PCIE2 slot + device pci 01.1 on end # Bifurcated PEG: PCIE4 slot + device pci 01.2 on end # Bifurcated PEG: M2_1 slot + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" # Super I/O HWM + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on end # Intel GbE through I218-V PHY + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: muxed M2_2 slot, SATA Express + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3: Realtek RTL8111E GbE NIC + device pci 00.0 on end + end + device pci 1c.3 on end # RP #4: ASM1184E 4-Port PCIe switch + device pci 1c.4 on end # RP #5: PCIE5 slot + device pci 1c.5 off end # RP #6 + device pci 1c.6 on end # RP #7: ASM1042A USB 3.0 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x6f + irq 0xe1 = 0x10 + end + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xbe + irq 0xf1 = 0x01 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xff + irq 0xe1 = 0x00 + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x72 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x0f + irq 0xf1 = 0x00 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0x00 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe5 = 0x12 + irq 0xed = 0x01 + irq 0xf0 = 0x30 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + end + end +end diff --git a/src/mainboard/asrock/z97_extreme6/dsdt.asl b/src/mainboard/asrock/z97_extreme6/dsdt.asl new file mode 100644 index 000000000000..17c44b652330 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads new file mode 100644 index 000000000000..cd05ae2fb817 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI1, -- DVI-I + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- DVI-I + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z97_extreme6/gpio.c b/src/mainboard/asrock/z97_extreme6/gpio.c new file mode 100644 index 000000000000..1dee18cc7e76 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c new file mode 100644 index 000000000000..db4364c4e3a0 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek ALC1150 */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c new file mode 100644 index 000000000000..a344dee1a58c --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/romstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7 */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, /* ASM1074 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* USB1 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* MINI_PCIE1 */ + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Can be used if ASM1042 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* has not been installed */ +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */ + { 1, USB_OC_PIN_SKIP }, /* ASM1074 */ + { 0, USB_OC_PIN_SKIP }, /* N/A, GbE */ +}; |