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-rw-r--r--src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex (renamed from src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex)125
-rw-r--r--src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex231
-rw-r--r--src/mainboard/bap/ode_e20XX/BiosCallOuts.c32
-rw-r--r--src/mainboard/bap/ode_e20XX/Kconfig18
-rw-r--r--src/mainboard/bap/ode_e20XX/Makefile.inc2
5 files changed, 320 insertions, 88 deletions
diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex
index d5fde6de85f0..111310a24a13 100644
--- a/src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex
+++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex
@@ -14,16 +14,18 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
+# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
# BAP ODE E20XX has 2GB ram soldered down on the Q7
+# Memory setting for DDR-1066
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
# bits[3:0]: 1 = 128 SPD Bytes Used
# bits[6:4]: 1 = 256 SPD Bytes Total
# bit7 : 0 = CRC covers bytes 0 ~ 125
-92
+11
# 1 SPD Revision -
-# 0x10 = Revision 1.0
+# 0x12 = Revision 1.2
12
# 2 Key Byte / DRAM Device Type
@@ -36,14 +38,14 @@
03
# 4 SDRAM CHIP Density and Banks
-# bits[3:0]: 3 = 2 Gigabits Total SDRAM capacity per chip
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
# bits[6:4]: 0 = 3 (8 banks)
# bit7 : reserved
04
# 5 SDRAM Addressing
# bits[2:0]: 1 = 10 Column Address Bits
-# bits[5:3]: 2 = 14 Row Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
# bits[7:6]: reserved
19
@@ -62,35 +64,35 @@
# 8 Module Memory Bus Width
# bits[2:0]: 3 = Primary bus width is 64 bits
-# bits[4:3]: 0 = 0 bits (no bus width extension)
+# bits[4:3]: 1 = 1 bit (bus width extension ECC)
# bits[7:5]: reserved
-08
+0B
# 9 Fine Timebase (FTB) Dividend / Divisor
-# bits[3:0]: 0x02 divisor
-# bits[7:4]: 0x05 dividend
-# 5/2 = 2.5ps
-52
+# bits[3:0]: 0x01 divisor
+# bits[7:4]: 0x01 dividend
+# 1/1 = 1ps
+11
# 10 Medium Timebase (MTB) Dividend
# 11 Medium Timebase (MTB) Divisor
-# 1 / 8 = .125 ns - used for clock freq of 400 through 1066 MHz
+# 1 / 8 = .125 ns - used for DDR3
01 08
# 12 SDRAM Minimum Cycle Time (tCKmin)
-# 0x0a = tCKmin of 1.25 ns = DDR3-1600 (800 MHz clock)
-0C
+# 0x0F = tCKmin of 1.875 ns = DDR3-1066 (533 MHz clock)
+0F
# 13 Reserved
00
# 14 CAS Latencies Supported, Least Significant Byte
# 15 CAS Latencies Supported, Most Significant Byte
-# Cas Latencies of 11 - 5 are supported
-7E 00
+# Cas Latencies of 8 - 5 are supported
+1E 00
# 16 Minimum CAS Latency Time (tAAmin)
-# 0x6E = 13.75ns - DDR3-1600K
+# 0x69 = 13.125ns - DDR3-1066F
69
# 17 Minimum Write Recovery Time (tWRmin)
@@ -98,7 +100,7 @@
78
# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
-# 0x6E = 13.75ns - DDR3-1600K
+# 0x69 = 13.125ns - DDR3-1066F
69
# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
@@ -106,7 +108,7 @@
3C
# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x6E = 13.75ns - DDR3-1600K
+# 0x69 = 13.125ns - DDR3-1066F
69
# 21 Upper Nibbles for tRAS and tRC
@@ -115,17 +117,17 @@
11
# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
-# 0x118 = 35ns - DDR3-1600 (see byte 21)
-20
+# 0x12C = 37.5ns - DDR3-1066 (see byte 21)
+2C
# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
-# 0x186 = 48.75ns - DDR3-1600K
-89
+# 0x195 = 50.625ns - DDR3-1066F (see byte 21)
+95
# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips
-20 08
+80 07
# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
@@ -137,24 +139,24 @@
# 28 Upper Nibble for tFAWmin
# 29 Minimum Four Activate Window Delay Time (tFAWmin)
-# 0x0140 = 40ns - DDR3-1600, 2 KB page size
-01 68
+# 0x0190 = 50ns - DDR3-1066, 2 KB page size
+01 90
# 30 SDRAM Optional Feature
# bit0 : 1= RZQ/6 supported
# bit1 : 1 = RZQ/7 supported
# bits[6:2]: reserved
-# bit7 : 1 = DLL Off mode supported
-83
+# bit7 : 0 = DLL Off mode supported
+03
# 31 SDRAM Thermal and Refresh Options
-# bit0 : 1 = Temp up to 95c supported
+# bit0 : 0 = Temp up to 95c supported
# bit1 : 0 = 85-95c uses 2x refresh rate
# bit2 : 1 = Auto Self Refresh supported
# bit3 : 0 = no on die thermal sensor
# bits[6:4]: reserved
# bit7 : 0 = partial self refresh supported
-01
+04
# 32 Module Thermal Sensor
# 0 = Thermal sensor not incorporated onto this assembly
@@ -182,18 +184,18 @@
# 60 Raw Card Extension, Module Nominal Height
# bits[4:0]: 0 = <= 15mm tall
# bits[7:5]: 0 = raw card revision 0-3
-0f
+00
# 61 Module Maximum Thickness
# bits[3:0]: 0 = thickness front <= 1mm
# bits[7:4]: 0 = thinkness back <= 1mm
-11
+00
# 62 Reference Raw Card Used
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
-22
+00
# 63 Address Mapping from Edge Connector to DRAM
# bit0 : 0 = standard mapping (not mirrored)
@@ -210,69 +212,20 @@
00 00 00 00 00
# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
-# 0x0001 = AMD
+# 0x80AD = Hynix
80 AD
# 119 Module ID: Module Manufacturing Location - oem specified
# 120 Module ID: Module Manufacture Year in BCD
-# 0x13 = 2013
-01 00
+# 0x00 = 2000
+00 00
# 121 Module ID: Module Manufacture week
-# 0x12 = 12th week
+# 0x00 = 0th week
00
# 122 - 125: Module Serial Number
00 00 00 00
# 126 - 127: Cyclical Redundancy Code
-D4 51
-
-# Coreboot is only interested in the first 128 values
-#128 - 135
-48 4d 54 34 32 35 53 36
-
-#136 - 143
-4d 46 52 36 43 2d 48 39
-
-#144 - 151
-20 20 4e 30 80 ad 00 00
-
-#152 - 159
-00 00 00 00 00 00 00 00
-
-#160 - 167
-00 00 00 00 00 00 00 00
-
-#168 - 175
-00 00 00 00 00 00 00 00
-
-#176 - 183
-00 00 00 00 00 00 00 00
-
-#184 - 191
-00 00 00 00 00 00 00 00
-
-#192 - 199
-00 00 00 00 00 00 00 00
-
-#200 - 207
-00 00 00 00 00 00 00 00
-
-#208 - 215
-00 00 00 00 00 00 00 00
-
-#216 - 223
-00 00 00 00 00 00 00 00
-
-#224 - 231
-00 00 00 00 00 00 00 00
-
-#232 - 239
-00 00 00 00 00 00 00 00
-
-#240 - 247
-00 00 00 00 00 00 00 00
-
-#248 - 255
-00 00 00 00 00 00 00 00 \ No newline at end of file
+E9 40
diff --git a/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex
new file mode 100644
index 000000000000..ba3d5ac4bf01
--- /dev/null
+++ b/src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex
@@ -0,0 +1,231 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+# Copyright (C) 2015 BAP - Bruhnspace Advanced Projects
+# (Written by Fabian Kunkel <fabi@adv.bruhnspace.com> for BAP)
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+
+# Memory chip: Hynix H5TQ4G63MFR-PBC with ECC
+# BAP ODE E20XX has 2GB ram soldered down on the Q7
+# Memory setting for DDR-800
+
+# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
+# bits[3:0]: 1 = 128 SPD Bytes Used
+# bits[6:4]: 1 = 256 SPD Bytes Total
+# bit7 : 0 = CRC covers bytes 0 ~ 125
+11
+
+# 1 SPD Revision -
+# 0x11 = Revision 1.1
+11
+
+# 2 Key Byte / DRAM Device Type
+# bits[7:0]: 0x0b = DDR3 SDRAM
+0B
+
+# 3 Key Byte / Module Type
+# bits[3:0]: 3 = SO-DIMM
+# bits[7:4]: reserved
+03
+
+# 4 SDRAM CHIP Density and Banks
+# bits[3:0]: 4 = 4 Gigabits Total SDRAM capacity per chip
+# bits[6:4]: 0 = 3 (8 banks)
+# bit7 : reserved
+04
+
+# 5 SDRAM Addressing
+# bits[2:0]: 1 = 10 Column Address Bits
+# bits[5:3]: 3 = 15 Row Address Bits
+# bits[7:6]: reserved
+19
+
+# 6 Module Nominal Voltage, VDD
+# bit0 : 0 = 1.5 V operable
+# bit1 : 0 = NOT 1.35 V operable
+# bit2 : 0 = NOT 1.25 V operable
+# bits[7:3]: reserved
+00
+
+# 7 Module Organization
+# bits[2:0]: 2 = 16 bits
+# bits[5:3]: 0 = 1 Rank
+# bits[7:6]: reserved
+02
+
+# 8 Module Memory Bus Width
+# bits[2:0]: 3 = Primary bus width is 64 bits
+# bits[4:3]: 1 = 1 bit (bus width extension ECC)
+# bits[7:5]: reserved
+0B
+
+# 9 Fine Timebase (FTB) Dividend / Divisor
+# bits[3:0]: 0x01 divisor
+# bits[7:4]: 0x01 dividend
+# 1/1 = 1ps
+11
+
+# 10 Medium Timebase (MTB) Dividend
+# 11 Medium Timebase (MTB) Divisor
+# 1 / 8 = .125 ns - used for DDR3
+01 08
+
+# 12 SDRAM Minimum Cycle Time (tCKmin)
+# 0x14 = tCKmin of 2.5 ns = DDR3-800 (400 MHz clock)
+14
+
+# 13 Reserved
+00
+
+# 14 CAS Latencies Supported, Least Significant Byte
+# 15 CAS Latencies Supported, Most Significant Byte
+# CAS Latencies of 6 - 5 are supported
+06 00
+
+# 16 Minimum CAS Latency Time (tAAmin)
+# 0x78 = 15ns - DDR3-800E
+78
+
+# 17 Minimum Write Recovery Time (tWRmin)
+# 0x78 = tWR of 15ns - All DDR3 speed grades
+78
+
+# 18 Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 0x6E = 15ns - DDR3-800E
+78
+
+# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
+# 0x3C = 7.5ns
+3C
+
+# 20 Minimum Row Precharge Delay Time (tRPmin)
+# 0x6E = 15ns - DDR3-800E
+78
+
+# 21 Upper Nibbles for tRAS and tRC
+# bits[3:0]: tRAS most significant nibble = 1 (see byte 22)
+# bits[7:4]: tRC most significant nibble = 1 (see byte 23)
+11
+
+# 22 Minimum Active to Precharge Delay Time (tRASmin), LSB
+# 0x12C = 37.5ns - DDR3-800E (see byte 21)
+2C
+
+# 23 Minimum Active to Active/Refresh Delay Time (tRCmin), LSB
+# 0x1A4 = 52.5ns - DDR3-800E (see byte 21)
+A4
+
+# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
+# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
+# 0x780 = 208ns - for 4 Gigabit chips
+80 07
+
+# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
+# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins
+3C
+
+# 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)
+# 0x3c = 7.5ns - All DDR3 SDRAM speed bins
+3C
+
+# 28 Upper Nibble for tFAWmin
+# 29 Minimum Four Activate Window Delay Time (tFAWmin)
+# 0x0190 = 50ns - DDR3-800, 2 KB page size
+01 90
+
+# 30 SDRAM Optional Feature
+# bit0 : 1= RZQ/6 supported
+# bit1 : 1 = RZQ/7 supported
+# bits[6:2]: reserved
+# bit7 : 0 = DLL Off mode supported
+03
+
+# 31 SDRAM Thermal and Refresh Options
+# bit0 : 0 = Temp up to 95c supported
+# bit1 : 0 = 85-95c uses 2x refresh rate
+# bit2 : 1 = Auto Self Refresh supported
+# bit3 : 0 = no on die thermal sensor
+# bits[6:4]: reserved
+# bit7 : 0 = partial self refresh supported
+04
+
+# 32 Module Thermal Sensor
+# 0 = Thermal sensor not incorporated onto this assembly
+00
+
+# 33 SDRAM Device Type
+# bits[1:0]: 0 = Signal Loading not specified
+# bits[3:2]: reserved
+# bits[6:4]: 0 = Die count not specified
+# bit7 : 0 = Standard Monolithic DRAM Device
+00
+
+# 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
+# 35 Fine Offset for Minimum CAS Latency Time (tAAmin)
+# 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
+# 37 Fine Offset for Minimum Row Precharge Delay Time (tRPmin)
+# 38 Fine Offset for Minimum Active to Active/Refresh Delay (tRCmin)
+00 00 00 00 00
+
+# 39 - 59 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 60 Raw Card Extension, Module Nominal Height
+# bits[4:0]: 0 = <= 15mm tall
+# bits[7:5]: 0 = raw card revision 0-3
+00
+
+# 61 Module Maximum Thickness
+# bits[3:0]: 0 = thickness front <= 1mm
+# bits[7:4]: 0 = thinkness back <= 1mm
+00
+
+# 62 Reference Raw Card Used
+# bits[4:0]: 0 = Reference Raw card A used
+# bits[6:5]: 0 = revision 0
+# bit7 : 0 = Reference raw cards A through AL
+00
+
+# 63 Address Mapping from Edge Connector to DRAM
+# bit0 : 0 = standard mapping (not mirrored)
+# bits[7:1]: reserved
+00
+
+# 64 - 116 (reserved)
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00
+
+# 117 - 118 Module ID: Module Manufacturers JEDEC ID Code
+# 0x80AD = Hynix
+80 AD
+
+# 119 Module ID: Module Manufacturing Location - oem specified
+# 120 Module ID: Module Manufacture Year in BCD
+# 0x00 = 2000
+00 00
+
+# 121 Module ID: Module Manufacture week
+# 0x00 = 0th week
+00
+
+# 122 - 125: Module Serial Number
+00 00 00 00
+
+# 126 - 127: Cyclical Redundancy Code
+48 91
diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
index b639e9629fb0..787b8339801b 100644
--- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
+++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c
@@ -24,13 +24,15 @@
#include "imc.h"
#endif
#include <stdlib.h>
+#include <spd_cache.h>
static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
const BIOS_CALLOUT_STRUCT BiosCallouts[] =
{
{AGESA_DO_RESET, agesa_Reset },
- {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs },
+ {AGESA_READ_SPD, board_ReadSpd_from_cbfs },
{AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported },
{AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp },
{AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData },
@@ -214,3 +216,31 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
return AGESA_SUCCESS;
}
+
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)
+{
+ AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+ AGESA_READ_SPD_PARAMS *info = ConfigPtr;
+ u8 index;
+
+ if (IS_ENABLED(CONFIG_BAP_E20_DDR3_1066))
+ index = 1;
+ else /* CONFIG_BAP_E20_DDR3_800 */
+ index = 0;
+
+ if (info->MemChannelId > 0)
+ return AGESA_UNSUPPORTED;
+ if (info->SocketId != 0)
+ return AGESA_UNSUPPORTED;
+ if (info->DimmId != 0)
+ return AGESA_UNSUPPORTED;
+
+ /* Read index 0, first SPD_SIZE bytes of spd.bin file. */
+ if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0)
+ die("No SPD data\n");
+
+ Status = AGESA_SUCCESS;
+#endif
+ return Status;
+}
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig
index dbd858300ee8..ad1c3de95eaf 100644
--- a/src/mainboard/bap/ode_e20XX/Kconfig
+++ b/src/mainboard/bap/ode_e20XX/Kconfig
@@ -62,4 +62,22 @@ config HUDSON_LEGACY_FREE
bool
default y
+choice
+ prompt "Select DDR3 clock"
+ default BAP_E20_DDR3_1066
+ help
+ Select your preferred DDR3 clock setting.
+
+ Note: This option changes the total power consumption.
+
+ If unsure, use DDR3-1066.
+
+config BAP_E20_DDR3_800
+ bool "Select DDR3-800"
+
+config BAP_E20_DDR3_1066
+ bool "Select DDR3-1066"
+
+endchoice
+
endif # BOARD_ODE_E20XX
diff --git a/src/mainboard/bap/ode_e20XX/Makefile.inc b/src/mainboard/bap/ode_e20XX/Makefile.inc
index f1c946a3318a..4d8eb8dba08e 100644
--- a/src/mainboard/bap/ode_e20XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e20XX/Makefile.inc
@@ -26,7 +26,7 @@ ramstage-y += OemCustomize.c
SPD_BIN = $(obj)/spd.bin
# Order of names in SPD_SOURCES is important!
-SPD_SOURCES = BAP_Q7
+SPD_SOURCES = BAP_Q7_800 BAP_Q7_1066
SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 07:26:45 +0000