diff options
Diffstat (limited to 'src/mainboard/google/brox/variants/brox')
3 files changed, 38 insertions, 15 deletions
diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c index 512d27ed4c31..3962991325f1 100644 --- a/src/mainboard/google/brox/variants/brox/fw_config.c +++ b/src/mainboard/google/brox/variants/brox/fw_config.c @@ -24,8 +24,8 @@ static const struct pad_config ish_enable_pads[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_NF(GPP_D14, DN_20K, DEEP, NF1), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2), }; diff --git a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h index 482c0a641371..c0b0eb0733aa 100644 --- a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h +++ b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h @@ -110,9 +110,9 @@ const u32 cim_verb_data[] = { * To set LDO1/LDO2 as default (used for headset) */ 0x02050008, - 0x0204EA0C, + 0x02046A0C, 0x02050008, - 0x0204EA0C, + 0x02046A0C, }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 7b00098853aa..424d61c6cbde 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -28,6 +28,7 @@ fw_config end chip soc/intel/alderlake + register "platform_pmax" = "208" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -35,18 +36,42 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[1].desc" = ""Fan-Inlet"" - # TODO: below values are initial reference values only ## Active Policy register "policies.active" = "{ [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(92, 80), + TEMP_PCT(89, 60), + TEMP_PCT(85, 40), + TEMP_PCT(80, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), + } + }, + [2] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), - TEMP_PCT(70, 60), - TEMP_PCT(65, 50), - TEMP_PCT(60, 40), + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), } } }" @@ -137,8 +162,6 @@ chip soc/intel/alderlake end # Integrated Graphics Device device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] device pnp 0c09.0 on end end end @@ -148,12 +171,12 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port use tcss_usb3_port1 as usb3_port - device generic 0 alias conn0 on end + device generic 0 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port3 as usb3_port - device generic 1 alias conn1 on end + device generic 1 on end end end end |