diff options
Diffstat (limited to 'src/mainboard/google/brox/variants')
22 files changed, 781 insertions, 63 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index f901db97352f..89c714d2bfd3 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -21,6 +21,9 @@ chip soc/intel/alderlake # seen on J0 and Q0 SKUs register "disable_package_c_state_demotion" = "1" + # Disable C1 state auto-demotion for all brox baseboards + register "disable_c1_state_auto_demotion" = "1" + # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 3d87bf25c8bd..edff2be8583d 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> VRALERT_L (NC) */ PAD_NC(GPP_B2, NONE), /* GPP_B3 : [NF1: PROC_GP2 NF4: ISH_GP4B NF6: USB_C_GPP_B3] ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */ PAD_NC(GPP_B4, NONE), /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */ @@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ PAD_NC(GPP_D13, NONE), /* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */ - PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D14, DN_20K), /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> SOC_ISH_UART0_RTS_L (NC) */ PAD_NC(GPP_D15, NONE), /* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> SOC_GPP_D16 (NC) */ @@ -187,7 +187,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E3 : [NF1: PROC_GP0 NF6: USB_C_GPP_E3] ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, DEEP, LEVEL, INVERT), /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> SOC_GPP_E5 (NC) */ diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c index 512d27ed4c31..3962991325f1 100644 --- a/src/mainboard/google/brox/variants/brox/fw_config.c +++ b/src/mainboard/google/brox/variants/brox/fw_config.c @@ -24,8 +24,8 @@ static const struct pad_config ish_enable_pads[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_NF(GPP_D14, DN_20K, DEEP, NF1), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2), }; diff --git a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h index 482c0a641371..c0b0eb0733aa 100644 --- a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h +++ b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h @@ -110,9 +110,9 @@ const u32 cim_verb_data[] = { * To set LDO1/LDO2 as default (used for headset) */ 0x02050008, - 0x0204EA0C, + 0x02046A0C, 0x02050008, - 0x0204EA0C, + 0x02046A0C, }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 7b00098853aa..424d61c6cbde 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -28,6 +28,7 @@ fw_config end chip soc/intel/alderlake + register "platform_pmax" = "208" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -35,18 +36,42 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[1].desc" = ""Fan-Inlet"" - # TODO: below values are initial reference values only ## Active Policy register "policies.active" = "{ [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(92, 80), + TEMP_PCT(89, 60), + TEMP_PCT(85, 40), + TEMP_PCT(80, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), + } + }, + [2] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), - TEMP_PCT(70, 60), - TEMP_PCT(65, 50), - TEMP_PCT(60, 40), + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), } } }" @@ -137,8 +162,6 @@ chip soc/intel/alderlake end # Integrated Graphics Device device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] device pnp 0c09.0 on end end end @@ -148,12 +171,12 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port use tcss_usb3_port1 as usb3_port - device generic 0 alias conn0 on end + device generic 0 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port3 as usb3_port - device generic 1 alias conn1 on end + device generic 1 on end end end end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk new file mode 100644 index 000000000000..a5ee3624fd3a --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/greenbayupoc/data.vbt b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt Binary files differnew file mode 100644 index 000000000000..716d09f557da --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt diff --git a/src/mainboard/google/brox/variants/greenbayupoc/gpio.c b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c new file mode 100644 index 000000000000..f26f098e9de5 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: E3110FFB1FCDA587 + * Overrides: None + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */ + PAD_NC(GPP_A19, NONE), + /* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */ + PAD_NC(GPP_A20, NONE), + + /* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX + * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */ + PAD_NC(GPP_D9, NONE), + /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX + * NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */ + PAD_NC(GPP_D10, NONE), + + /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + + /* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */ + PAD_NC(GPP_H15, NONE), + /* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */ + PAD_NC(GPP_H17, NONE), + + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h index 482c0a641371..79c81d1315dd 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h +++ b/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h @@ -7,13 +7,13 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 - 0x10ec12ac, // Subsystem ID + 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC236 + 0x103C8C60, // Subsystem ID 0x00000013, // Number of jacks (NID entries) AZALIA_RESET(0x1), /* NID 0x01, HDA Codec Subsystem ID Verb table */ - AZALIA_SUBVENDOR(0, 0x10ec12ac), + AZALIA_SUBVENDOR(0, 0x103C8C60), /* Pin Widget Verb Table */ @@ -30,41 +30,56 @@ const u32 cim_verb_data[] = { /* Pin widget 0x18 - NPC */ AZALIA_PIN_CFG(0, 0x18, 0x411111F0), /* Pin widget 0x19 - MIC2 (Port-F) */ - AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + AZALIA_PIN_CFG(0, 0x19, 0x03A11020), /* Pin widget 0x1A - LINE1 (Port-C) */ AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), /* Pin widget 0x1B - NPC */ AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), /* Pin widget 0x1D - BEEP-IN */ - AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + AZALIA_PIN_CFG(0, 0x1d, 0x40600001), /* Pin widget 0x1E - NPC */ AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), /* Pin widget 0x21 - HP1-OUT (Port-I) */ - AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x21, 0x03211040), + /* - * Widget node 0x20 - 1 - * Codec hidden reset and speaker power 2W/4ohm + * ;Pin widget 0x19 - MIC2 (Port-F) */ - 0x0205001A, - 0x0204C003, - 0x02050038, - 0x02047901, + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F03, /* - * Widget node 0x20 - 2 - * Class D power on Reset + * Pin widget 0x21 - HP1-OUT (Port-I) + */ + 0x02171C40, + 0x02171D10, + 0x02171E21, + 0x02171F03, + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm */ 0x0205003C, 0x02040354, 0x0205003C, 0x02040314, /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205001B, + 0x02040A4B, + 0x0205000B, + 0x02047778, + /* * Widget node 0x20 - 3 * Disable AGC and set AGC limit to -1.5dB */ - 0x02050016, - 0x02040C50, - 0x02050012, - 0x0204EBC1, + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409A3, /* * Widget node 0x20 - 4 * Set AGC Post gain +1.5dB then Enable AGC diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory.c b/src/mainboard/google/brox/variants/greenbayupoc/memory.c new file mode 100644 index 000000000000..3cfa79e95009 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/memory.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + .resistor = 100, + .targets = {50, 20, 25, 25, 25}, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = 0, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +bool variant_is_half_populated(void) +{ + return false; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; + spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk deleted file mode 100644 index eace2e443e20..000000000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. - -SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt deleted file mode 100644 index 2e0f37a10a61..000000000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt - -DRAM Part Name ID to assign diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt deleted file mode 100644 index 2499005682ab..000000000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt +++ /dev/null @@ -1,11 +0,0 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.mk and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb index ee65135d8845..1939325e44ab 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb +++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb @@ -1,14 +1,202 @@ fw_config - field STORAGE 0 1 + field RETIMER 0 1 + option RETIMER_UNKNOWN 0 + option RETIMER_BYPASS 1 + end + field STORAGE 2 3 option STORAGE_UNKNOWN 0 - option STORAGE_UFS 1 - option STORAGE_NVME 2 + option STORAGE_NVME 1 + option STORAGE_UFS 2 + end + field WIFI 4 + option WIFI_CNVI_WIFI 0 + option WIFI_BT_PCIE 1 + end + field UFC 5 + option UFC_NONE 0 + option UFC_USB 1 + end + field AUDIO 6 7 + option AUDIO_UNKNOWN 0 + option AUDIO_REALTEK_ALC3247 1 end end chip soc/intel/alderlake + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI) device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + probe STORAGE STORAGE_UNKNOWN + end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI WIFI_BT_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI WIFI_BT_PCIE + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI WIFI_CNVI_WIFI + end + device ref smbus on end end end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c new file mode 100644 index 000000000000..b46832035632 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/variant.c b/src/mainboard/google/brox/variants/greenbayupoc/variant.c new file mode 100644 index 000000000000..9452ad0eb987 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/variant.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI))) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + } +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk new file mode 100644 index 000000000000..48683172d658 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c new file mode 100644 index 000000000000..230ecaf005f7 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/gpio.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_D5 : SRCCLKREQ0_L ==> PCIE_REFCLK_SSD1_REQ_N */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SOC_GPP_E10 (NC) */ + PAD_NC(GPP_D6, NONE), + /* GPP_D7 : SRCCLKREQ2_L ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX + * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> HOST_MCU_FW_UP_STRAP */ + PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG), + /* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> GSPI0_SOC_FP_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), + /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 + * NF7: GSPI0_CLK] ==> GSPI0_SOC_FP_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> GSPI0_SOC_DI_FP_DO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> GSPI0_SOC_DO_FP_DI */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), + /* GPP_E15 : SRCCLK_OE8_L ==> SOC_GPP_E15 (NC) */ + PAD_NC(GPP_E15, NONE), + /* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX + * NF6: USB_C_GPP_E18] ==> SOC_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E18, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX + * NF6: USB_C_GPP_E20] ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_E21 : DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_E21, 0, LOCK_CONFIG), + /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK + * NF6: USB_C_GPP_F11] ==> GSPI1_SOC_TCHSCR_CLK */ + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), + /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL + * NF6: USB_C_GPP_F12] ==> GSPI1_SOC_DO_TCHSCR_DI */ + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), + /* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA + * NF6: USB_C_GPP_F13] ==> GSPI1_SOC_DI_TCHSCR_DO */ + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), + /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 + * NF6: USB_C_GPP_F15] ==> PCH_TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_F15, 0, PLTRST), + /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# + * NF6: USB_C_GPP_F16] ==> GSPI1_SOC_TCHSCR_CS_L */ + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), + /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_S4, NONE, PLTRST), + /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_S5, NONE, PLTRST), + /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_S6, NONE, PLTRST), + /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_S7, NONE, PLTRST), + /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, EDGE_SINGLE, NONE), +}; + + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_S4, NONE, PLTRST), + /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_S5, NONE, PLTRST), + /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_S6, NONE, PLTRST), + /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_S7, NONE, PLTRST), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/brox/variants/lotso/memory.c b/src/mainboard/google/brox/variants/lotso/memory.c new file mode 100644 index 000000000000..0765d5e57eb0 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/memory.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* Leave Rcomp unspecified to use the FSP optimized defaults */ + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 15, 14, 12, 11, 9, 10, 8 }, + .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4 }, + }, + .ddr1 = { + .dq0 = { 2, 0, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 13, 15, 12, 14, 10, 11, 8, 9 }, + }, + .ddr2 = { + .dq0 = { 14, 13, 12, 15, 9, 10, 11, 8 }, + .dq1 = { 4, 6, 7, 5, 1, 2, 0, 3 }, + }, + .ddr3 = { + .dq0 = { 14, 13, 15, 12, 8, 11, 9, 10 }, + .dq1 = { 0, 2, 1, 3, 6, 5, 7, 4 }, + }, + .ddr4 = { + .dq0 = { 8, 11, 10, 9, 14, 15, 13, 12 }, + .dq1 = { 3, 0, 2, 1, 5, 7, 4, 6 }, + }, + .ddr5 = { + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5 }, + .dq1 = { 12, 13, 15, 14, 10, 9, 8, 11 }, + }, + .ddr6 = { + .dq0 = { 1, 0, 3, 2, 5, 7, 6, 4 }, + .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6 }, + .dq1 = { 14, 15, 9, 11, 12, 8, 10, 13 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * MEM_STRAP_0 GPP_S4 + * MEM_STRAP_1 GPP_S5 + * MEM_STRAP_2 GPP_S6 + * MEM_STRAP_3 GPP_S7 + */ + gpio_t spd_gpios[] = { + GPP_S4, + GPP_S5, + GPP_S6, + GPP_S7, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk index eace2e443e20..2616d2d015c2 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/lotso/memory src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068 diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt index fa247902eeee..e7d0650b950c 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt @@ -1 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/lotso/memory src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K3KL6L60GM-MGCT 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL8L80DM-MGCU 2 (0010) +MT62F1G32D2DS-023 WT:C 2 (0010) +H58G56BK8BX068 2 (0010) diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt index 2499005682ab..d2c09aee31ed 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K3KL6L60GM-MGCT +H9JCNNNBK3MLYR-N6E +K3KL8L80DM-MGCU +MT62F1G32D2DS-023 WT:C +H58G56BK8BX068 |