diff options
Diffstat (limited to 'src/mainboard/google/link/romstage.c')
| -rw-r--r-- | src/mainboard/google/link/romstage.c | 22 |
1 files changed, 2 insertions, 20 deletions
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index ca58262b9133..8236e2062df1 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -155,8 +155,6 @@ void main(unsigned long bist) { int boot_mode = 0; int cbmem_was_initted; - u32 pm1_cnt; - u16 pm1_sts; struct pei_data pei_data = { .pei_version = PEI_VERSION, @@ -239,24 +237,8 @@ void main(unsigned long bist) sandybridge_early_initialization(SANDYBRIDGE_MOBILE); printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - boot_mode = 2; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } else { + boot_mode = southbridge_detect_s3_resume() ? 2 : 0; + if (boot_mode == 0) { /* This is the fastest way to let users know * the Intel CPU is now alive. */ |