diff options
Diffstat (limited to 'src/mainboard/google')
179 files changed, 4020 insertions, 742 deletions
diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h index 4d269aedafc5..4097b4a3a80d 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h @@ -24,7 +24,7 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ // group 1, cap 0 @@ -34,10 +34,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -54,7 +54,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1A, 0x90a70111), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -64,7 +64,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h index 538f131c2906..f8b509caca04 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h @@ -37,7 +37,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x17, 0x40000008), /* Pin Complex (NID 0x18) Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -47,10 +47,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -60,7 +60,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group1 diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h index c0db8c2c9444..6cc5bf0579b5 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -51,10 +51,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -64,7 +64,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack */ // group2, cap 1 diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h index 33ae19929350..3f9ec3f5e384 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -51,10 +51,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -64,7 +64,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index ae2e94e4b012..064bebfeea79 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -25,19 +25,19 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled*/ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF - 3.5mm Jack*/ AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -47,10 +47,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I - Disabled */ - AZALIA_PIN_CFG(0, 0x21, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_CFG_NC(0)), /* Undocumented settings from Realtek (needed for beep_gen) */ /* Widget node 0x20 */ diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 0ec52201c888..2637e8940a5a 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -16,7 +16,7 @@ config BOARD_GOOGLE_BROX_COMMON select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID - select ENABLE_TCSS_USB_DETECTION if !CHROMEOS + select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS) select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION @@ -29,7 +29,7 @@ config BOARD_GOOGLE_BROX_COMMON select MAINBOARD_HAS_TPM2 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU -# select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -44,13 +44,15 @@ config BOARD_GOOGLE_BASEBOARD_BROX select DRIVERS_AUDIO_SOF select DRIVERS_GFX_GENERIC select HAVE_SLP_S0_GATE - select MEMORY_SOLDERDOWN + select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_GREENBAYUPOC select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG select SOC_INTEL_RAPTORLAKE select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION select DRIVERS_INTEL_ISH + select MAINBOARD_HAS_EARLY_LIBGFXINIT select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 @@ -69,6 +71,8 @@ config BOARD_GOOGLE_LOTSO config BOARD_GOOGLE_GREENBAYUPOC select BOARD_GOOGLE_BASEBOARD_BROX + select CHROMEOS_WIFI_SAR if CHROMEOS + select MEMORY_SODIMM if BOARD_GOOGLE_BROX_COMMON @@ -131,9 +135,6 @@ config VARIANT_DIR config VBOOT select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index f901db97352f..89c714d2bfd3 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -21,6 +21,9 @@ chip soc/intel/alderlake # seen on J0 and Q0 SKUs register "disable_package_c_state_demotion" = "1" + # Disable C1 state auto-demotion for all brox baseboards + register "disable_c1_state_auto_demotion" = "1" + # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 3d87bf25c8bd..edff2be8583d 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> VRALERT_L (NC) */ PAD_NC(GPP_B2, NONE), /* GPP_B3 : [NF1: PROC_GP2 NF4: ISH_GP4B NF6: USB_C_GPP_B3] ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */ PAD_NC(GPP_B4, NONE), /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */ @@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ PAD_NC(GPP_D13, NONE), /* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */ - PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D14, DN_20K), /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> SOC_ISH_UART0_RTS_L (NC) */ PAD_NC(GPP_D15, NONE), /* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> SOC_GPP_D16 (NC) */ @@ -187,7 +187,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E3 : [NF1: PROC_GP0 NF6: USB_C_GPP_E3] ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, DEEP, LEVEL, INVERT), /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> SOC_GPP_E5 (NC) */ diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c index 512d27ed4c31..3962991325f1 100644 --- a/src/mainboard/google/brox/variants/brox/fw_config.c +++ b/src/mainboard/google/brox/variants/brox/fw_config.c @@ -24,8 +24,8 @@ static const struct pad_config ish_enable_pads[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_NF(GPP_D14, DN_20K, DEEP, NF1), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2), }; diff --git a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h index 482c0a641371..c0b0eb0733aa 100644 --- a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h +++ b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h @@ -110,9 +110,9 @@ const u32 cim_verb_data[] = { * To set LDO1/LDO2 as default (used for headset) */ 0x02050008, - 0x0204EA0C, + 0x02046A0C, 0x02050008, - 0x0204EA0C, + 0x02046A0C, }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 7b00098853aa..424d61c6cbde 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -28,6 +28,7 @@ fw_config end chip soc/intel/alderlake + register "platform_pmax" = "208" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -35,18 +36,42 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[1].desc" = ""Fan-Inlet"" - # TODO: below values are initial reference values only ## Active Policy register "policies.active" = "{ [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(92, 80), + TEMP_PCT(89, 60), + TEMP_PCT(85, 40), + TEMP_PCT(80, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), + } + }, + [2] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), - TEMP_PCT(70, 60), - TEMP_PCT(65, 50), - TEMP_PCT(60, 40), + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), } } }" @@ -137,8 +162,6 @@ chip soc/intel/alderlake end # Integrated Graphics Device device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] device pnp 0c09.0 on end end end @@ -148,12 +171,12 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port use tcss_usb3_port1 as usb3_port - device generic 0 alias conn0 on end + device generic 0 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port3 as usb3_port - device generic 1 alias conn1 on end + device generic 1 on end end end end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk new file mode 100644 index 000000000000..a5ee3624fd3a --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/greenbayupoc/data.vbt b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt Binary files differnew file mode 100644 index 000000000000..716d09f557da --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt diff --git a/src/mainboard/google/brox/variants/greenbayupoc/gpio.c b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c new file mode 100644 index 000000000000..f26f098e9de5 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: E3110FFB1FCDA587 + * Overrides: None + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */ + PAD_NC(GPP_A19, NONE), + /* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */ + PAD_NC(GPP_A20, NONE), + + /* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX + * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */ + PAD_NC(GPP_D9, NONE), + /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX + * NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */ + PAD_NC(GPP_D10, NONE), + + /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + + /* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */ + PAD_NC(GPP_H15, NONE), + /* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */ + PAD_NC(GPP_H17, NONE), + + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h index 482c0a641371..79c81d1315dd 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h +++ b/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h @@ -7,13 +7,13 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 - 0x10ec12ac, // Subsystem ID + 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC236 + 0x103C8C60, // Subsystem ID 0x00000013, // Number of jacks (NID entries) AZALIA_RESET(0x1), /* NID 0x01, HDA Codec Subsystem ID Verb table */ - AZALIA_SUBVENDOR(0, 0x10ec12ac), + AZALIA_SUBVENDOR(0, 0x103C8C60), /* Pin Widget Verb Table */ @@ -30,41 +30,56 @@ const u32 cim_verb_data[] = { /* Pin widget 0x18 - NPC */ AZALIA_PIN_CFG(0, 0x18, 0x411111F0), /* Pin widget 0x19 - MIC2 (Port-F) */ - AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + AZALIA_PIN_CFG(0, 0x19, 0x03A11020), /* Pin widget 0x1A - LINE1 (Port-C) */ AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), /* Pin widget 0x1B - NPC */ AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), /* Pin widget 0x1D - BEEP-IN */ - AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + AZALIA_PIN_CFG(0, 0x1d, 0x40600001), /* Pin widget 0x1E - NPC */ AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), /* Pin widget 0x21 - HP1-OUT (Port-I) */ - AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x21, 0x03211040), + /* - * Widget node 0x20 - 1 - * Codec hidden reset and speaker power 2W/4ohm + * ;Pin widget 0x19 - MIC2 (Port-F) */ - 0x0205001A, - 0x0204C003, - 0x02050038, - 0x02047901, + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F03, /* - * Widget node 0x20 - 2 - * Class D power on Reset + * Pin widget 0x21 - HP1-OUT (Port-I) + */ + 0x02171C40, + 0x02171D10, + 0x02171E21, + 0x02171F03, + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm */ 0x0205003C, 0x02040354, 0x0205003C, 0x02040314, /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205001B, + 0x02040A4B, + 0x0205000B, + 0x02047778, + /* * Widget node 0x20 - 3 * Disable AGC and set AGC limit to -1.5dB */ - 0x02050016, - 0x02040C50, - 0x02050012, - 0x0204EBC1, + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409A3, /* * Widget node 0x20 - 4 * Set AGC Post gain +1.5dB then Enable AGC diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory.c b/src/mainboard/google/brox/variants/greenbayupoc/memory.c new file mode 100644 index 000000000000..3cfa79e95009 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/memory.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + .resistor = 100, + .targets = {50, 20, 25, 25, 25}, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = 0, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +bool variant_is_half_populated(void) +{ + return false; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; + spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk deleted file mode 100644 index eace2e443e20..000000000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. - -SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt deleted file mode 100644 index 2e0f37a10a61..000000000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt - -DRAM Part Name ID to assign diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb index ee65135d8845..1939325e44ab 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb +++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb @@ -1,14 +1,202 @@ fw_config - field STORAGE 0 1 + field RETIMER 0 1 + option RETIMER_UNKNOWN 0 + option RETIMER_BYPASS 1 + end + field STORAGE 2 3 option STORAGE_UNKNOWN 0 - option STORAGE_UFS 1 - option STORAGE_NVME 2 + option STORAGE_NVME 1 + option STORAGE_UFS 2 + end + field WIFI 4 + option WIFI_CNVI_WIFI 0 + option WIFI_BT_PCIE 1 + end + field UFC 5 + option UFC_NONE 0 + option UFC_USB 1 + end + field AUDIO 6 7 + option AUDIO_UNKNOWN 0 + option AUDIO_REALTEK_ALC3247 1 end end chip soc/intel/alderlake + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI) device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + probe STORAGE STORAGE_UNKNOWN + end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI WIFI_BT_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI WIFI_BT_PCIE + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI WIFI_CNVI_WIFI + end + device ref smbus on end end end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c new file mode 100644 index 000000000000..b46832035632 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/variant.c b/src/mainboard/google/brox/variants/greenbayupoc/variant.c new file mode 100644 index 000000000000..9452ad0eb987 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/variant.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI))) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + } +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk new file mode 100644 index 000000000000..48683172d658 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c new file mode 100644 index 000000000000..230ecaf005f7 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/gpio.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_D5 : SRCCLKREQ0_L ==> PCIE_REFCLK_SSD1_REQ_N */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SOC_GPP_E10 (NC) */ + PAD_NC(GPP_D6, NONE), + /* GPP_D7 : SRCCLKREQ2_L ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX + * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> HOST_MCU_FW_UP_STRAP */ + PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG), + /* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> GSPI0_SOC_FP_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), + /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 + * NF7: GSPI0_CLK] ==> GSPI0_SOC_FP_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> GSPI0_SOC_DI_FP_DO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> GSPI0_SOC_DO_FP_DI */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), + /* GPP_E15 : SRCCLK_OE8_L ==> SOC_GPP_E15 (NC) */ + PAD_NC(GPP_E15, NONE), + /* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX + * NF6: USB_C_GPP_E18] ==> SOC_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E18, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX + * NF6: USB_C_GPP_E20] ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_E21 : DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_E21, 0, LOCK_CONFIG), + /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK + * NF6: USB_C_GPP_F11] ==> GSPI1_SOC_TCHSCR_CLK */ + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), + /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL + * NF6: USB_C_GPP_F12] ==> GSPI1_SOC_DO_TCHSCR_DI */ + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), + /* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA + * NF6: USB_C_GPP_F13] ==> GSPI1_SOC_DI_TCHSCR_DO */ + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), + /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 + * NF6: USB_C_GPP_F15] ==> PCH_TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_F15, 0, PLTRST), + /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# + * NF6: USB_C_GPP_F16] ==> GSPI1_SOC_TCHSCR_CS_L */ + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), + /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_S4, NONE, PLTRST), + /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_S5, NONE, PLTRST), + /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_S6, NONE, PLTRST), + /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_S7, NONE, PLTRST), + /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, EDGE_SINGLE, NONE), +}; + + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_S4, NONE, PLTRST), + /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_S5, NONE, PLTRST), + /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_S6, NONE, PLTRST), + /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_S7, NONE, PLTRST), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/brox/variants/lotso/memory.c b/src/mainboard/google/brox/variants/lotso/memory.c new file mode 100644 index 000000000000..0765d5e57eb0 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/memory.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* Leave Rcomp unspecified to use the FSP optimized defaults */ + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 15, 14, 12, 11, 9, 10, 8 }, + .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4 }, + }, + .ddr1 = { + .dq0 = { 2, 0, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 13, 15, 12, 14, 10, 11, 8, 9 }, + }, + .ddr2 = { + .dq0 = { 14, 13, 12, 15, 9, 10, 11, 8 }, + .dq1 = { 4, 6, 7, 5, 1, 2, 0, 3 }, + }, + .ddr3 = { + .dq0 = { 14, 13, 15, 12, 8, 11, 9, 10 }, + .dq1 = { 0, 2, 1, 3, 6, 5, 7, 4 }, + }, + .ddr4 = { + .dq0 = { 8, 11, 10, 9, 14, 15, 13, 12 }, + .dq1 = { 3, 0, 2, 1, 5, 7, 4, 6 }, + }, + .ddr5 = { + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5 }, + .dq1 = { 12, 13, 15, 14, 10, 9, 8, 11 }, + }, + .ddr6 = { + .dq0 = { 1, 0, 3, 2, 5, 7, 6, 4 }, + .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6 }, + .dq1 = { 14, 15, 9, 11, 12, 8, 10, 13 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * MEM_STRAP_0 GPP_S4 + * MEM_STRAP_1 GPP_S5 + * MEM_STRAP_2 GPP_S6 + * MEM_STRAP_3 GPP_S7 + */ + gpio_t spd_gpios[] = { + GPP_S4, + GPP_S5, + GPP_S6, + GPP_S7, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk index eace2e443e20..2616d2d015c2 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/lotso/memory src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068 diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt index fa247902eeee..e7d0650b950c 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt @@ -1 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/lotso/memory src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K3KL6L60GM-MGCT 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL8L80DM-MGCU 2 (0010) +MT62F1G32D2DS-023 WT:C 2 (0010) +H58G56BK8BX068 2 (0010) diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt index 2499005682ab..d2c09aee31ed 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K3KL6L60GM-MGCT +H9JCNNNBK3MLYR-N6E +K3KL8L80DM-MGCU +MT62F1G32D2DS-023 WT:C +H58G56BK8BX068 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 66839d161cdb..db2ed796e714 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config ACPI_FNKEY_GEN_SCANCODE + default 94 if BOARD_GOOGLE_XOL + config BOARD_GOOGLE_BRYA_COMMON def_bool n select DRIVERS_GENERIC_ALC1015 @@ -64,7 +67,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP select HAVE_SLP_S0_GATE - select MEMORY_SODIMM if !BOARD_GOOGLE_CONSTITUTION + select MEMORY_SODIMM if !(BOARD_GOOGLE_CONSTITUTION || BOARD_GOOGLE_NOVA) select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE @@ -93,6 +96,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_AUDIO_SOF select DRIVERS_INTEL_ISH select MAINBOARD_DISABLE_STAGE_CACHE + select MAINBOARD_HAS_EARLY_LIBGFXINIT select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW @@ -184,6 +188,7 @@ config BOARD_GOOGLE_BRYA0 config BOARD_GOOGLE_BUJIA select BOARD_GOOGLE_BASEBOARD_BRASK + select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_CRAASK @@ -358,6 +363,7 @@ config BOARD_GOOGLE_NOKRIS config BOARD_GOOGLE_NOVA select BOARD_GOOGLE_BASEBOARD_BRASK select SOC_INTEL_RAPTORLAKE + select MEMORY_SOLDERDOWN config BOARD_GOOGLE_OMNIGUL select BOARD_GOOGLE_BASEBOARD_BRYA @@ -366,6 +372,10 @@ config BOARD_GOOGLE_OMNIGUL select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS +config BOARD_GOOGLE_ORISA + select BOARD_GOOGLE_BASEBOARD_TRULO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + config BOARD_GOOGLE_OSIRIS select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -403,10 +413,17 @@ config BOARD_GOOGLE_PUJJO config BOARD_GOOGLE_SUNDANCE select BOARD_GOOGLE_BASEBOARD_NISSA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_GPIO_KEYS + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_PUJJOGA select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA @@ -439,6 +456,11 @@ config BOARD_GOOGLE_REDRIX4ES select GOOGLE_DSM_PARAM_FILE_NAME if VPD select SOC_INTEL_COMMON_BLOCK_IPU +config BOARD_GOOGLE_RIVEN + select BOARD_GOOGLE_BASEBOARD_NISSA + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_SKOLAS select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_NAU8315 @@ -533,6 +555,7 @@ config BOARD_GOOGLE_XIVU config BOARD_GOOGLE_XOL select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_I2C_DA7219 select DRIVERS_INTEL_ISH select SOC_INTEL_RAPTORLAKE @@ -634,6 +657,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_NIVVIKS default 0x1 if BOARD_GOOGLE_NOVA default 0x1 if BOARD_GOOGLE_OMNIGUL + default 0x0 if BOARD_GOOGLE_ORISA default 0x1 if BOARD_GOOGLE_OSIRIS default 0x0 if BOARD_GOOGLE_PIRRHA default 0x1 if BOARD_GOOGLE_PRIMUS @@ -641,6 +665,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_QUANDISO default 0x1 if BOARD_GOOGLE_REDRIX default 0x3 if BOARD_GOOGLE_REDRIX4ES + default 0x0 if BOARD_GOOGLE_RIVEN default 0x1 if BOARD_GOOGLE_SKOLAS default 0x1 if BOARD_GOOGLE_SKOLAS4ES default 0x1 if BOARD_GOOGLE_TAEKO @@ -669,8 +694,9 @@ config FMDFILE config TPM_TIS_ACPI_INTERRUPT int - default 13 if !BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_13 (GPP_A13_IRQ) + default 17 if BOARD_GOOGLE_ORISA # GPE0_DW0_17 (GPP_A17_IRQ) default 20 if BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_20 (GPP_A20_IRQ) + default 13 if !BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_13 (GPP_A13_IRQ) config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -722,6 +748,7 @@ config MAINBOARD_PART_NUMBER default "Nokris" if BOARD_GOOGLE_NOKRIS default "Nova" if BOARD_GOOGLE_NOVA default "Omnigul" if BOARD_GOOGLE_OMNIGUL + default "Orisa" if BOARD_GOOGLE_ORISA default "Osiris" if BOARD_GOOGLE_OSIRIS default "Pirrha" if BOARD_GOOGLE_PIRRHA default "Primus" if BOARD_GOOGLE_PRIMUS @@ -729,6 +756,7 @@ config MAINBOARD_PART_NUMBER default "Quandiso" if BOARD_GOOGLE_QUANDISO default "Redrix" if BOARD_GOOGLE_REDRIX default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES + default "Riven" if BOARD_GOOGLE_RIVEN default "Skolas" if BOARD_GOOGLE_SKOLAS default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES default "Sundance" if BOARD_GOOGLE_SUNDANCE @@ -785,6 +813,7 @@ config VARIANT_DIR default "nokris" if BOARD_GOOGLE_NOKRIS default "nova" if BOARD_GOOGLE_NOVA default "omnigul" if BOARD_GOOGLE_OMNIGUL + default "orisa" if BOARD_GOOGLE_ORISA default "osiris" if BOARD_GOOGLE_OSIRIS default "pirrha" if BOARD_GOOGLE_PIRRHA default "primus" if BOARD_GOOGLE_PRIMUS @@ -792,6 +821,7 @@ config VARIANT_DIR default "quandiso" if BOARD_GOOGLE_QUANDISO default "redrix" if BOARD_GOOGLE_REDRIX default "redrix4es" if BOARD_GOOGLE_REDRIX4ES + default "riven" if BOARD_GOOGLE_RIVEN default "skolas" if BOARD_GOOGLE_SKOLAS default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES default "sundance" if BOARD_GOOGLE_SUNDANCE @@ -814,9 +844,6 @@ config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index fe8fcc942ec5..3229b18cd884 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -122,6 +122,9 @@ config BOARD_GOOGLE_REDRIX config BOARD_GOOGLE_REDRIX4ES bool "-> Redrix4ES" +config BOARD_GOOGLE_RIVEN + bool "-> Riven" + config BOARD_GOOGLE_SKOLAS bool "-> Skolas" @@ -181,3 +184,6 @@ config BOARD_GOOGLE_SUNDANCE config BOARD_GOOGLE_PUJJOGA bool "-> Pujjoga" + +config BOARD_GOOGLE_ORISA + bool "-> Orisa" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk index 3743228e8e8b..3a6695828f71 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk +++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk @@ -4,6 +4,7 @@ bootblock-y += gpio.c romstage-y += memory.c romstage-y += gpio.c +romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 55bd9c0be22a..495b5713da96 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -155,7 +155,37 @@ chip soc/intel/alderlake }" device domain 0 on - device ref igpu on end + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end device ref dtt on end device ref tcss_xhci on end device ref xhci on end diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads new file mode 100644 index 000000000000..3b02f14d95a7 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (eDP, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c index dc686fe242b1..64e1b14cfb22 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c @@ -16,7 +16,8 @@ void variant_configure_pads(void) base_pads = variant_gpio_table(&base_num); gpio_padbased_override(padbased_table, base_pads, base_num); override_pads = variant_gpio_override_table(&override_num); - gpio_padbased_override(padbased_table, override_pads, override_num); + if (override_pads != NULL) + gpio_padbased_override(padbased_table, override_pads, override_num); fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_padbased(padbased_table); free(padbased_table); diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk index 54a5c5b5c9e4..be05cd4e5c6c 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk +++ b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk @@ -1,8 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c - romstage-y += memory.c -romstage-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index a5e2217fef71..9e6378f6e7a5 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -1,4 +1,57 @@ chip soc/intel/alderlake + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8 + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9 + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 10 + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 11 + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 12 + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 13 + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 14 + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 15 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 3 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 5 + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 6 + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 7 + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 8 + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 9 + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 10 + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref tcss_xhci on end + device ref xhci on end + device ref shared_sram on end + device ref heci1 on end + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end end end diff --git a/src/mainboard/google/brya/variants/bujia/Makefile.mk b/src/mainboard/google/brya/variants/bujia/Makefile.mk new file mode 100644 index 000000000000..d38141ca2476 --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/bujia/data.vbt b/src/mainboard/google/brya/variants/bujia/data.vbt Binary files differnew file mode 100644 index 000000000000..6a06e1570d37 --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/data.vbt diff --git a/src/mainboard/google/brya/variants/bujia/gpio.c b/src/mainboard/google/brya/variants/bujia/gpio.c new file mode 100644 index 000000000000..484ce292299d --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/gpio.c @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> NC */ + PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG), + /* A15 : USB_OC2# ==> NC */ + PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG), + /* A18 : DDSP_HPDB ==> HDMIB_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), + + /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> GPI */ + PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : UART1_TXD */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* E14 : DDSP_HPDA ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* H12 : I2C7_SDA ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 4f2c04a57af4..252d82f8a593 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -1,6 +1,320 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | NC | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | NC | + #| I2C5 | NC | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable Port 6 + + register "usb3_ports[2]" = "USB3_PORT_EMPTY " # Disable Port 2 + # USB3 Port 3 for OPS interface + + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable Port1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #NVME + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 off end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end # I2C1 + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "customized_leds" = "0x060f" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # RTL8111 Ethernet NIC + device ref pcie_rp8 off end # disable SD reader + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 OPS interface TX25A"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port4 on end + end + end + end + end + end end diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 16c44af69204..61cb50022a3c 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -349,8 +349,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end @@ -377,7 +377,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -385,7 +385,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -398,14 +398,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/glassway/Makefile.mk b/src/mainboard/google/brya/variants/glassway/Makefile.mk index 102307a6cafe..e409037840dc 100644 --- a/src/mainboard/google/brya/variants/glassway/Makefile.mk +++ b/src/mainboard/google/brya/variants/glassway/Makefile.mk @@ -4,4 +4,7 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c + ramstage-y += variant.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/glassway/ramstage.c b/src/mainboard/google/brya/variants/glassway/ramstage.c new file mode 100644 index 000000000000..6d63eaa8f7dc --- /dev/null +++ b/src/mainboard/google/brya/variants/glassway/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->VccInAuxImonIccImax = 100; // 25 * 4 for ADL-N + printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax); +} diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 49dfea867e8a..61344d7e63fe 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -297,8 +297,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end @@ -325,7 +325,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -333,7 +333,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -346,14 +346,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -365,7 +365,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -379,7 +379,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end end diff --git a/src/mainboard/google/brya/variants/nova/Makefile.mk b/src/mainboard/google/brya/variants/nova/Makefile.mk index d38141ca2476..f4627aec1b19 100644 --- a/src/mainboard/google/brya/variants/nova/Makefile.mk +++ b/src/mainboard/google/brya/variants/nova/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nova/memory.c b/src/mainboard/google/brya/variants/nova/memory.c new file mode 100644 index 000000000000..c3999501775b --- /dev/null +++ b/src/mainboard/google/brya/variants/nova/memory.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map as per doc #573387 */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 2, 1, 4, 6, 5, 7, }, + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, }, + }, + .ddr1 = { + .dq0 = { 13, 14, 11, 12, 10, 8, 15, 9, }, + .dq1 = { 5, 2, 4, 3, 1, 6, 0, 7, }, + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 7, 6, 5, 4, }, + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, }, + }, + .ddr3 = { + .dq0 = { 13, 14, 12, 15, 11, 9, 8, 10, }, + .dq1 = { 5, 2, 1, 4, 7, 0, 3, 6, }, + }, + .ddr4 = { + .dq0 = { 11, 10, 8, 9, 14, 15, 13, 12, }, + .dq1 = { 3, 0, 2, 1, 5, 4, 6, 7, }, + }, + .ddr5 = { + .dq0 = { 11, 15, 13, 12, 10, 9, 14, 8, }, + .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4, }, + }, + .ddr6 = { + .dq0 = { 11, 13, 10, 12, 15, 9, 14, 8, }, + .dq1 = { 4, 3, 5, 2, 7, 0, 1, 6, }, + }, + .ddr7 = { + .dq0 = { 12, 13, 15, 14, 11, 9, 10, 8, }, + .dq1 = { 4, 5, 1, 2, 6, 3, 0, 7, }, + }, + }, + + /* DQS CPU<>DRAM map as per doc #573387 */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_F16 + * GPIO_MEM_CONFIG_1 GPP_F12 + * GPIO_MEM_CONFIG_2 GPP_F13 + * GPIO_MEM_CONFIG_3 GPP_F15 + */ + gpio_t spd_gpios[] = { + GPP_F16, + GPP_F12, + GPP_F13, + GPP_F15, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_F11 */ + return gpio_get(GPP_F11); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brya/variants/nova/memory/Makefile.mk b/src/mainboard/google/brya/variants/nova/memory/Makefile.mk index bb0957dfe233..121eaba69d05 100644 --- a/src/mainboard/google/brya/variants/nova/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/nova/memory/Makefile.mk @@ -1,8 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt index e2089db069fc..65c620a31b45 100644 --- a/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt @@ -1,10 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt DRAM Part Name ID to assign K4U6E3S4AB-MGCL 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) -MT53E1G32D2NP-046 WT:B 1 (0001) -K4UBE3D4AB-MGCL 1 (0001) diff --git a/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt index 10f244d15b2f..c1727abb80a8 100644 --- a/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt @@ -1,4 +1,2 @@ K4U6E3S4AB-MGCL H9HCNNNBKMMLXR-NEE -MT53E1G32D2NP-046 WT:B -K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index 93018ea074d7..950bb9beabbe 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -6,6 +6,8 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 @@ -178,13 +180,6 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port1 as dfp[0].typec_port - device generic 0 on end - end - end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" diff --git a/src/mainboard/google/brya/variants/orisa/Makefile.mk b/src/mainboard/google/brya/variants/orisa/Makefile.mk new file mode 100644 index 000000000000..c0c42324f803 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/orisa/fw_config.c b/src/mainboard/google/brya/variants/orisa/fw_config.c new file mode 100644 index 000000000000..800fc1f20518 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/fw_config.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/gpio.c b/src/mainboard/google/brya/variants/orisa/gpio.c index 410f194f6502..beee6fcb29a6 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/orisa/gpio.c @@ -16,19 +16,24 @@ static const struct pad_config early_gpio_table[] = { /* TODO */ }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +/* Fill romstage gpio configuration */ +static const struct pad_config romstage_gpio_table[] = { + /* TODO */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } -const struct pad_config *__weak variant_gpio_override_table(size_t *num) +const struct pad_config *variant_gpio_override_table(size_t *num) { *num = 0; return NULL; } -const struct pad_config *__weak variant_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; @@ -39,8 +44,8 @@ static const struct cros_gpio cros_gpios[] = { }; DECLARE_CROS_GPIOS(cros_gpios); -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) +const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } diff --git a/src/mainboard/google/brya/variants/orisa/hda_verb.c b/src/mainboard/google/brya/variants/orisa/hda_verb.c new file mode 100644 index 000000000000..bf998e1f0c6e --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/hda_verb.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0x10ec12ac, // Subsystem ID + 0x00000013, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting - 1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default (used for headset) + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/ec.h b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h new file mode 100644 index 000000000000..7a2a6ff8b774 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h new file mode 100644 index 000000000000..c4fe342621e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/orisa/memory.c b/src/mainboard/google/brya/variants/orisa/memory.c new file mode 100644 index 000000000000..2d738554ec86 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/memory.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg variant_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &variant_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + return true; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brya/variants/orisa/memory/Makefile.mk b/src/mainboard/google/brya/variants/orisa/memory/Makefile.mk new file mode 100644 index 000000000000..28a0bee46b12 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/memory/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/orisa/memory src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/orisa/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/orisa/memory/dram_id.generated.txt new file mode 100644 index 000000000000..7f1a1837443e --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/orisa/memory src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt index 2499005682ab..fc41c85c3324 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt @@ -9,3 +9,4 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb new file mode 100644 index 000000000000..600eb024222a --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -0,0 +1,552 @@ +fw_config + field THERMAL_SOLUTION 0 0 + option THERMAL_SOLUTION_6W 0 + option THERMAL_SOLUTION_15W 1 + end + field STORAGE 30 31 + option STORAGE_EMMC 0 + option STORAGE_UFS 1 + end +end + +chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_B" + + # S0ix enable + register "s0ix_enable" = "1" + + # DPTF enable + register "dptf_enable" = "1" + + register "tcc_offset" = "10" # TCC of 90 + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # eMMC HS400 + register "emmc_enable_hs400_mode" = "1" + + #eMMC DLL tuning parameters + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "0" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_sdi_enable[1]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # FIXME: To be enabled in future based on PNP impact data. + # Disable Package C-state demotion for nissa baseboard. + register "disable_package_c_state_demotion" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Trackpad | + #| I2C5 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + + device domain 0 on + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 60), + TEMP_PCT(39, 55), + TEMP_PCT(38, 50), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 60), + TEMP_PCT(50, 55), + TEMP_PCT(48, 50), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_6W + end + end + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 58), + TEMP_PCT(39, 53), + TEMP_PCT(38, 47), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 58), + TEMP_PCT(50, 53), + TEMP_PCT(48, 47), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 1 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_15W + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)" + device i2c 50 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW1_03" + register "detect" = "1" + device i2c 15 on end + end + end #I2C1 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)" + register "generic.enable_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)" + register "generic.stop_delay_ms" = "150" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C5 + device ref heci1 on end + device ref pcie_rp7 off end + device ref emmc on end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/orisa/variant.c b/src/mainboard/google/brya/variants/orisa/variant.c new file mode 100644 index 000000000000..f34fb2698b1c --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/variant.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <fw_config.h> + +void variant_devtree_update(void) +{ + struct device *emmc = DEV_PTR(emmc); + struct device *ufs = DEV_PTR(ufs); + struct device *ish = DEV_PTR(ish); + + if (!fw_config_is_provisioned()) { + printk(BIOS_INFO, "fw_config unprovisioned so enable all storage devices\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "eMMC disabled by fw_config\n"); + emmc->enabled = 0; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "UFS disabled by fw_config\n"); + ufs->enabled = 0; + ish->enabled = 0; + } +} diff --git a/src/mainboard/google/brya/variants/pujjoga/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk new file mode 100644 index 000000000000..e04a887191b2 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/pujjoga/fw_config.c b/src/mainboard/google/brya/variants/pujjoga/fw_config.c new file mode 100644 index 000000000000..eaef2a2fe338 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/fw_config.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config wwan_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* A12 : WWAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_A12, NONE), + /* D5 : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */ + PAD_NC(GPP_D5, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* D15 : EN_PP2800_WCAM_X ==> WWAN_SAR_DETECT_2_ODL */ + PAD_NC(GPP_D15, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H21 : WCAM_MCLK_R ==> WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT))) { + printk(BIOS_INFO, "Disable WWAN-related GPIO pins.\n"); + gpio_padbased_override(padbased_table, wwan_disable_pads, + ARRAY_SIZE(wwan_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c new file mode 100644 index 000000000000..cf5c9bdc0d49 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage for Sundance */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A18 : HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A20 : NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* B5 : SOC_I2C_SUB_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : SOC_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_TERM_GPO(GPP_C1, 1, UP_20K, DEEP), + /* D3 : test point */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D8 : NC */ + PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), + /* D15 : WWAN_SAR_DETECT_2_ODL */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : NC ==> SD_WAKE_N */ + PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* E20 : NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : NC */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H12 : NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_LOCK(GPP_H19, NONE, LOCK_CONFIG), + /* H21 : WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H22 : WCAM_MCLK_R ==> NC */ + PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL ==> NC */ + PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* + * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff + * requirement. WWAN_EN must be asserted before WWAN_RST_L is released + * (with min delay 0 ms), so this works as long as the pin used for + * WWAN_EN comes before the pin used for WWAN_RST_L. + */ + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +/* Pad configuration in romstage for Sundance */ +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h index c4fe342621e6..c96b01fc1509 100644 --- a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk index eace2e443e20..c6e0a1cf1b87 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt index fa247902eeee..adec69c7168c 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt @@ -1 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt + DRAM Part Name ID to assign +H58G56BK7BX068 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL6L60GM-MGCT 2 (0010) +K3KL8L80CM-MGCT 0 (0000) +MT62F1G32D2DS-026 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt index 2499005682ab..b962c72c9cc2 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H58G56BK7BX068 +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT +MT62F1G32D2DS-026 WT:B diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb index 4f2c04a57af4..951d60ef22d1 100644 --- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb @@ -1,6 +1,428 @@ +fw_config + field WWAN 3 4 + option WWAN_ABSENT 0 + option LTE_PRESENT 1 + option 5G_PRESENT 2 + end + field WIFI_SAR_ID 13 16 + option WIFI_SAR_TABLE_AX211 0 + option WIFI_SAR_TABLE_AX203 1 + end +end + chip soc/intel/alderlake + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "PreWake" = "100" + + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN + + # Configure external V1P05/Vnn/VnnSx Rails for Pujjoga + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "20" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "3" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0a" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x19" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x08" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end - device domain 0 on - end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on + probe WWAN LTE_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on + probe WWAN LTE_PRESENT + end + end + end + end + end + end end diff --git a/src/mainboard/google/brya/variants/pujjoga/variant.c b/src/mainboard/google/brya/variants/pujjoga/variant.c new file mode 100644 index 000000000000..c4a6face5b57 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/variant.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); +} diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 21c9aba4818c..bebc927864c4 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -264,6 +264,9 @@ chip soc/intel/alderlake register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "50" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "55" + register "generic.stop_off_delay_ms" = "5" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" diff --git a/src/mainboard/google/brya/variants/riven/Makefile.mk b/src/mainboard/google/brya/variants/riven/Makefile.mk new file mode 100644 index 000000000000..d38141ca2476 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/riven/data.vbt b/src/mainboard/google/brya/variants/riven/data.vbt Binary files differnew file mode 100644 index 000000000000..bc735476a5da --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/data.vbt diff --git a/src/mainboard/google/brya/variants/riven/gpio.c b/src/mainboard/google/brya/variants/riven/gpio.c new file mode 100644 index 000000000000..4d0a6fea79b0 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/gpio.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage for craask */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A18 : NC ==> HDMI_HPD_SUB_ODL*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H12 : UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : HDMI_SRC_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/riven/include/variant/ec.h b/src/mainboard/google/brya/variants/riven/include/variant/ec.h new file mode 100644 index 000000000000..7a2a6ff8b774 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/riven/include/variant/gpio.h b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h new file mode 100644 index 000000000000..c4fe342621e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk new file mode 100644 index 000000000000..0288c51143e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt new file mode 100644 index 000000000000..f76709207524 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3LKLKL0EM-MGCN 2 (0010) +K3LKBKB0BM-MGCP 3 (0011) +H9JCNNNCP3MLYR-N6E 0 (0000) diff --git a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt new file mode 100644 index 000000000000..b08faac3e744 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F1G32D4DR-031 WT:B +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +K3LKLKL0EM-MGCN +K3LKBKB0BM-MGCP +H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb new file mode 100644 index 000000000000..4f2c04a57af4 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/brya/variants/sundance/Makefile.mk b/src/mainboard/google/brya/variants/sundance/Makefile.mk index d38141ca2476..be823735219d 100644 --- a/src/mainboard/google/brya/variants/sundance/Makefile.mk +++ b/src/mainboard/google/brya/variants/sundance/Makefile.mk @@ -3,4 +3,6 @@ bootblock-y += gpio.c romstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/sundance/fw_config.c b/src/mainboard/google/brya/variants/sundance/fw_config.c new file mode 100644 index 000000000000..f8f9a07933e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/fw_config.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config wwan_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* A12 : WWAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_A12, NONE), + /* D5 : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */ + PAD_NC(GPP_D5, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* D15 : EN_PP2800_WCAM_X ==> WWAN_SAR_DETECT_2_ODL */ + PAD_NC(GPP_D15, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H21 : WCAM_MCLK_R ==> WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(WWAN, LTE_ABSENT))) { + printk(BIOS_INFO, "Disable WWAN-related GPIO pins.\n"); + gpio_padbased_override(padbased_table, wwan_disable_pads, + ARRAY_SIZE(wwan_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h index c4fe342621e6..c96b01fc1509 100644 --- a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index bd1ed7403de7..bd5112fe44fd 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -1,3 +1,13 @@ +fw_config + field WWAN 3 4 + option LTE_ABSENT 0 + option LTE_PRESENT 1 + end + field WIFI_SAR_ID 12 15 + option WIFI_SAR_TABLE_AX211 0 + end +end + chip soc/intel/alderlake # Acoustic settings register "acoustic_noise_mitigation" = "1" @@ -11,31 +21,31 @@ chip soc/intel/alderlake # EMMC Tx CMD Delay # Refer to EDS-Vol2-42.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39, total 625ps. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39, total 625ps. register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-42.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78, total 465ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79, total 465ps. register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-42.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 5250ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79, total 5000ps. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79, total 5000ps. register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-42.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 3375ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119, total 3250ps. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119, total 3375ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. @@ -44,14 +54,14 @@ chip soc/intel/alderlake # 01: Rx clock before output buffer, # 10: Automatic selection based on working mode. # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39, total 0ps. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79, total 5000ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + # [14:8] Rx Strobe Delay DLL 1 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. + # [6:0] Rx Strobe Delay DLL 2 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" # SOC Aux orientation override: @@ -195,7 +205,7 @@ chip soc/intel/alderlake register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" register "generic.wake" = "GPE0_DW2_14" register "generic.detect" = "1" - register "hid_desc_reg_offset" = "0x20" + register "hid_desc_reg_offset" = "0x01" device i2c 0x38 on end end end @@ -275,7 +285,9 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port5 on end + device ref usb2_port5 on + probe WWAN LTE_PRESENT + end end chip drivers/usb/acpi register "desc" = ""USB2 UFC"" @@ -304,7 +316,9 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb3_port3 on end + device ref usb3_port3 on + probe WWAN LTE_PRESENT + end end end end diff --git a/src/mainboard/google/brya/variants/sundance/variant.c b/src/mainboard/google/brya/variants/sundance/variant.c new file mode 100644 index 000000000000..c4a6face5b57 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/variant.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); +} diff --git a/src/mainboard/google/brya/variants/trulo/Makefile.mk b/src/mainboard/google/brya/variants/trulo/Makefile.mk new file mode 100644 index 000000000000..91f031e7a474 --- /dev/null +++ b/src/mainboard/google/brya/variants/trulo/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c new file mode 100644 index 000000000000..1a6d1b14662d --- /dev/null +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A14 : USB_OC1# ==> USB_A0_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A14, NONE, NF1, LOCK_CONFIG), + /* A15 : USB_OC2# ==> USB_A1_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A15, NONE, NF1, LOCK_CONFIG), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* TODO */ +}; + +/* Fill romstage gpio configuration */ +static const struct pad_config romstage_gpio_table[] = { + /* TODO */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + /* TODO */ +}; +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index ee861420f699..9285c3304305 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/alderlake - device domain 0 on - end + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + + device domain 0 on + end end diff --git a/src/mainboard/google/brya/variants/xol/Makefile.mk b/src/mainboard/google/brya/variants/xol/Makefile.mk index c346b0abc938..d85ce1bfbe2a 100644 --- a/src/mainboard/google/brya/variants/xol/Makefile.mk +++ b/src/mainboard/google/brya/variants/xol/Makefile.mk @@ -4,3 +4,4 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 168d9821d053..39478a148912 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -195,6 +195,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ diff --git a/src/mainboard/google/brya/variants/xol/include/variant/gpio.h b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h index c4fe342621e6..f62197dfe618 100644 --- a/src/mainboard/google/brya/variants/xol/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h @@ -5,4 +5,6 @@ #include <baseboard/gpio.h> +#define CAM_PWR GPP_A17 + #endif diff --git a/src/mainboard/google/brya/variants/xol/memory.c b/src/mainboard/google/brya/variants/xol/memory.c index f8afa73e1459..b0cbaad72fd9 100644 --- a/src/mainboard/google/brya/variants/xol/memory.c +++ b/src/mainboard/google/brya/variants/xol/memory.c @@ -63,9 +63,11 @@ static const struct mb_cfg variant_memcfg = { .ccc_config = 0xff, }, + .LpDdrDqDqsReTraining = 1, + .ect = 1, /* Early Command Training */ - .UserBd = BOARD_TYPE_MOBILE, + .UserBd = BOARD_TYPE_ULT_ULX, }; const struct mb_cfg *variant_memory_params(void) diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 80d15feb6221..d73702c4bbe2 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -3,6 +3,10 @@ fw_config option STORAGE_UFS 0 option STORAGE_NVME 1 end + field WIFI_SAR_ID 31 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + end end chip soc/intel/alderlake @@ -25,6 +29,12 @@ chip soc/intel/alderlake # display flickering issue. register "disable_dynamic_tccold_handshake" = "true" + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + register "tcc_offset" = "6" # TCC of 94 register "platform_pmax" = "122" @@ -132,7 +142,7 @@ chip soc/intel/alderlake .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 650, - .fall_time_ns = 400, + .fall_time_ns = 200, .data_hold_time_ns = 50, }, }" diff --git a/src/mainboard/google/brya/variants/xol/variant.c b/src/mainboard/google/brya/variants/xol/variant.c new file mode 100644 index 000000000000..8d14715a670c --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <baseboard/variants.h> +#include <variant/gpio.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + /* Add board-specific MS0X entries */ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(CAM_PWR); + if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(CAM_PWR); +} diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index f3960ca654c9..cb34f3c55edd 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -25,22 +25,6 @@ chip northbridge/intel/sandybridge # Force double refresh rate register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0080 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref peg10 off end # PCIe Bridge for discrete graphics @@ -69,6 +53,19 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, 0, -1}, /* P0: Right USB 3.0 #1 (no OC) */ + {1, 0, -1}, /* P1: Right USB 3.0 #2 (no OC) */ + {1, 0, -1}, /* P2: Camera (no OC) */ + /* P3-P8: Empty */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, + {1, 1, -1}, /* P9: Left USB 1 (no OC) */ + {1, 0, -1}, /* P10: Mini PCIe - WLAN / BT (no OC) */ + /* P11-P13: Empty */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1} + }" + device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 @@ -101,7 +98,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index f63d3c3d75fc..8d07a38b14ee 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -44,24 +44,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, -1 }, /* P2: Camera (no OC) */ - { 0, 0, -1 }, /* P3: Empty */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 0, 0, -1 }, /* P8: Empty */ - { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ - { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 8c291ce2799c..6baaeac3db0a 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_KINGLER_COMMON def_bool BOARD_GOOGLE_KINGLER || \ BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ + BOARD_GOOGLE_SQUIRTLE || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB @@ -27,9 +28,9 @@ config BOARD_GOOGLE_STARYU_COMMON if BOARD_GOOGLE_CORSOLA_COMMON config CORSOLA_SDCARD_INIT - def_bool BOARD_GOOGLE_MAGIKARP || \ + def_bool BOARD_GOOGLE_KINGLER_COMMON || \ + BOARD_GOOGLE_MAGIKARP || \ BOARD_GOOGLE_TENTACRUEL || \ - BOARD_GOOGLE_KINGLER_COMMON || \ BOARD_GOOGLE_WUGTRIO config BOARD_SPECIFIC_OPTIONS @@ -56,6 +57,7 @@ config BOARD_SPECIFIC_OPTIONS BOARD_GOOGLE_KINGLER || \ BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ + BOARD_GOOGLE_SQUIRTLE || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_KRABBY || \ @@ -82,19 +84,20 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string + default "Chinchou" if BOARD_GOOGLE_CHINCHOU default "Kingler" if BOARD_GOOGLE_KINGLER default "Krabby" if BOARD_GOOGLE_KRABBY default "Kyogre" if BOARD_GOOGLE_KYOGRE - default "Steelix" if BOARD_GOOGLE_STEELIX - default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Magikarp" if BOARD_GOOGLE_MAGIKARP - default "Voltorb" if BOARD_GOOGLE_VOLTORB - default "Starmie" if BOARD_GOOGLE_STARMIE default "Ponyta" if BOARD_GOOGLE_PONYTA - default "Chinchou" if BOARD_GOOGLE_CHINCHOU - default "Wugtrio" if BOARD_GOOGLE_WUGTRIO default "Skitty" if BOARD_GOOGLE_SKITTY + default "Squirtle" if BOARD_GOOGLE_SQUIRTLE + default "Starmie" if BOARD_GOOGLE_STARMIE + default "Steelix" if BOARD_GOOGLE_STEELIX + default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Veluza" if BOARD_GOOGLE_VELUZA + default "Voltorb" if BOARD_GOOGLE_VOLTORB + default "Wugtrio" if BOARD_GOOGLE_WUGTRIO config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index cbe1928a6fa1..ab6a132868ea 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -8,32 +8,35 @@ config BOARD_GOOGLE_KINGLER config BOARD_GOOGLE_KYOGRE bool "-> Kyogre" +config BOARD_GOOGLE_PONYTA + bool "-> Ponyta" + +config BOARD_GOOGLE_SQUIRTLE + bool "-> Squirtle" + config BOARD_GOOGLE_STEELIX bool "-> Steelix" config BOARD_GOOGLE_VOLTORB bool "-> Voltorb" -config BOARD_GOOGLE_PONYTA - bool "-> Ponyta" - comment "Krabby" +config BOARD_GOOGLE_CHINCHOU + bool "-> Chinchou" + config BOARD_GOOGLE_KRABBY bool "-> Krabby" -config BOARD_GOOGLE_TENTACRUEL - bool "-> Tentacruel" - config BOARD_GOOGLE_MAGIKARP bool "-> Magikarp" -config BOARD_GOOGLE_CHINCHOU - bool "-> Chinchou" - config BOARD_GOOGLE_SKITTY bool "-> Skitty" +config BOARD_GOOGLE_TENTACRUEL + bool "-> Tentacruel" + config BOARD_GOOGLE_VELUZA bool "-> Veluza" diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb index 300ba7b8a78d..bb7f003c0372 100644 --- a/src/mainboard/google/corsola/devicetree.cb +++ b/src/mainboard/google/corsola/devicetree.cb @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only fw_config + field SECONDARY_USB 27 + option DISABLED 0 + option ENABLED 1 + end field AUDIO_AMP 28 29 option AMP_ALC1019 0 option AMP_ALC5645 1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index a1ba5f9356b4..1a0ab3c9171b 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -53,6 +53,11 @@ static void mainboard_init(struct device *dev) setup_usb_host(); + if (fw_config_probe(FW_CONFIG(SECONDARY_USB, ENABLED))) { + /* Change host to USB2 port0 for initialization */ + setup_usb_secondary_host(); + } + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC1019))) configure_alc1019(); diff --git a/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk b/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk index 892563e28d82..3e346616922d 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk @@ -5,3 +5,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-5.hex # ID = 1(0b0001) Parts = SDVB8D8A34XGCL3N3T diff --git a/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt index 6a92eb9c1c57..6bd852744b7d 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt @@ -9,3 +9,4 @@ K4U6E3S4AA-MGCR 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AB-MGCL 0 (0000) +SDVB8D8A34XGCL3N3T 1 (0001) diff --git a/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt index 86b3025417b3..f8d00775e731 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt @@ -3,3 +3,4 @@ K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E512M32D1NP-046 WT:B K4U6E3S4AB-MGCL +SDVB8D8A34XGCL3N3T diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 5e39c884e41f..2c25e60a1bfc 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -134,6 +134,15 @@ chip soc/intel/jasperlake end end chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on + probe DB_PORTS DB_PORTS_1C_1A + probe DB_PORTS DB_PORTS_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 2)" @@ -152,6 +161,15 @@ chip soc/intel/jasperlake device usb 2.6 on end end chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on + probe DB_PORTS DB_PORTS_1C_1A + probe DB_PORTS DB_PORTS_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(2, 2)" diff --git a/src/mainboard/google/dedede/variants/kracko/ramstage.c b/src/mainboard/google/dedede/variants/kracko/ramstage.c index 255e58557ec0..459fc77dc1b2 100644 --- a/src/mainboard/google/dedede/variants/kracko/ramstage.c +++ b/src/mainboard/google/dedede/variants/kracko/ramstage.c @@ -11,7 +11,23 @@ static void ext_vr_update(void) cfg->disable_external_bypass_vr = 1; } +static void usb_port_update(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + + if (fw_config_is_provisioned() && + fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_NONE))) { + /* Disable USB C1 port */ + cfg->usb2_ports[1].enable = 0; + cfg->usb3_ports[1].enable = 0; + /* Disable USB A1 port */ + cfg->usb2_ports[3].enable = 0; + cfg->usb3_ports[3].enable = 0; + } +} + void variant_devtree_update(void) { ext_vr_update(); + usb_port_update(); } diff --git a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk index 8b4d130e9621..90505f8f5f46 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267 SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4CBAM-ML-A diff --git a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt index 76ab7e0c78de..c62f08b15f5d 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt @@ -1,10 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) K4U6E3S4AB-MGCL 0 (0000) CXDB4CBAM-ML-A 1 (0001) +MT53E512M32D1NP-046 WT:B 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt index b93cdbf0db89..c87f6c1ca2c5 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt @@ -2,3 +2,5 @@ H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR K4U6E3S4AB-MGCL CXDB4CBAM-ML-A +MT53E512M32D1NP-046 WT:B +H54G46CYRBX267 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d6200d9a4863..86aab95ab1ff 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -216,10 +216,8 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on + device ref igpu on chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD0"" @@ -233,18 +231,16 @@ chip soc/intel/cannonlake register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" device generic 0 on end end - end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub + end + device ref dptf on end + device ref thermal on end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""drallion_ish.bin"" device generic 0 on end end end - device pci 14.0 on + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -320,16 +316,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" @@ -389,8 +383,8 @@ chip soc/intel/cannonlake register "device_present_gpio_invert" = "1" device i2c 34 on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -405,59 +399,29 @@ chip soc/intel/cannonlake register "detect" = "1" device i2c 15 on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on + end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on + end + device ref pcie_rp9 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" - end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + end + device ref pcie_rp13 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref uart0 on end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h index 89c5175d9cf1..3298d9c322b8 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -18,14 +18,14 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x12, 0xb7a60130), - AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x16, 0x40000000), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40c00001), AZALIA_PIN_CFG(0, 0x1e, 0x421212f2), AZALIA_PIN_CFG(0, 0x21, 0x04211020), diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 906f98e0bb6d..31a9461d99e2 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <boardid.h> +#include <device/dram/ddr3.h> #include <string.h> #include <ec/google/chromeec/ec.h> #include <fsp/soc_binding.h> @@ -37,7 +38,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3; /* Limit K4EBE304EB-EGCF memory to 1600MHz for stability */ if (board_id() < 6 && mainboard_get_spd_index() == 5) { diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index c053177d55d3..2f0d2e42181f 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -2,8 +2,10 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <gpio.h> #include <soc/romstage.h> +#include <spd.h> #include <string.h> #include "../gpio.h" @@ -18,7 +20,7 @@ static void mainboard_print_spd_info(uint8_t spd[]) const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; + char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 }; int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; @@ -30,21 +32,21 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Module type */ printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: + switch (spd[SPD_MEMORY_TYPE]) { + case SPD_MEMORY_TYPE_SDRAM_DDR3: printk(BIOS_INFO, "DDR3\n"); break; - case SPD_DRAM_LPDDR3: + case SPD_MEMORY_TYPE_LPDDR3_INTEL: printk(BIOS_INFO, "LPDDR3\n"); break; default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]); break; } /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; + memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN); + spd_name[SPD_DDR3_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); printk(BIOS_INFO, @@ -86,16 +88,16 @@ uintptr_t mainboard_get_spd_data(void) die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); spd_index = 1; } - spd_index *= SPD_LEN; + spd_index *= SPD_SIZE_MAX_DDR3; mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); return (uintptr_t)(spd_file + spd_index); diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 7b53fd43c0e3..847160de9cf7 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -3,18 +3,10 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 #define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 int mainboard_get_spd_index(void); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 0d631cc5e4a4..795d96ef9b8a 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -14,7 +14,7 @@ #include <smbios.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> -#include <string.h> +#include <stdio.h> #include <timer.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 35b53e26af95..64b363db2c37 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variant.h> +#include <device/dram/ddr3.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/romstage.h> @@ -30,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3; mem_cfg->DqPinsInterleaved = FALSE; spd_memory_init_params(mupd, spd_idx); diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index a6e655bbef7a..edbedffa654c 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -2,8 +2,10 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <gpio.h> #include <soc/romstage.h> +#include <spd.h> #include <string.h> #include <baseboard/variant.h> @@ -19,7 +21,7 @@ static void mainboard_print_spd_info(uint8_t spd[]) const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; + char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 }; int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; @@ -31,21 +33,21 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Module type */ printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: + switch (spd[SPD_MEMORY_TYPE]) { + case SPD_MEMORY_TYPE_SDRAM_DDR3: printk(BIOS_INFO, "DDR3\n"); break; - case SPD_DRAM_LPDDR3: + case SPD_MEMORY_TYPE_LPDDR3_INTEL: printk(BIOS_INFO, "LPDDR3\n"); break; default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]); break; } /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; + memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN); + spd_name[SPD_DDR3_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); printk(BIOS_INFO, @@ -83,16 +85,16 @@ void spd_memory_init_params(FSPM_UPD *mupd, int spd_index) die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); spd_index = 1; } - const size_t spd_offset = spd_index * SPD_LEN; + const size_t spd_offset = spd_index * SPD_SIZE_MAX_DDR3; /* Make sure a valid SPD was found */ if (spd_file[spd_offset] == 0) die("Invalid SPD data."); diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index 764958b86afd..8e1a5f43c377 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -3,17 +3,9 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 #define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 #endif diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 64f45dea9e9e..02790b0762a3 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -5,7 +5,7 @@ #include <console/console.h> #include <gpio.h> #include <soc/sdram.h> -#include <string.h> +#include <stdio.h> #include <types.h> static const char *sdram_configs[] = { diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 3609de92743a..f55b0c5da703 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ - AZALIA_PIN_CFG(0, 0x14, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 427f094677a9..685414e64776 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpi.h> -#include <string.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -16,6 +15,7 @@ #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> +#include <stdio.h> #include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 69047fa4a22a..22f8150d5e9e 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -19,7 +19,7 @@ #include <soc/mtcmos.h> #include <soc/spm.h> #include <soc/usb.h> -#include <string.h> +#include <stdio.h> #include "gpio.h" #include "panel.h" diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 88983dcfc676..028db5e52803 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge @@ -65,6 +49,23 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, -1 }, /* P3: SDCARD (no OC) */ + { 0, 0, -1 }, /* P4: Empty */ + { 1, 0, -1 }, /* P5: WWAN (no OC) */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, -1 }, /* P8: Camera (no OC) */ + { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ + { 0, 0, -1 }, /* P10: Empty */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index e40531dac153..2d20ac03a9f0 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -63,24 +63,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, -1 }, /* P3: SDCARD (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 1, 0, -1 }, /* P5: WWAN (no OC) */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: Camera (no OC) */ - { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ - { 0, 0, -1 }, /* P10: Empty */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { /* LINK has 2 channels of memory down */ diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 49b40b95b62b..1509f0a1cc09 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref igd on end # vga controller @@ -56,6 +40,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x1" + register "usb_port_config" = "{ + {0, 0, -1}, /* P0: Empty */ + {1, 0, 0}, /* P1: Left USB 1 (OC0) */ + {1, 0, 1}, /* P2: Left USB 2 (OC1) */ + {1, 0, 1}, /* P3: Left USB 3 (OC1) */ + {0, 0, -1}, /* P4-P7: Empty */ + {0, 0, -1}, + {0, 0, -1}, + {0, 0, -1}, + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + {1, 0, -1}, /* P8: MiniPCIe (WLAN) (no OC) */ + {0, 0, -1}, /* P9: Empty */ + {1, 0, -1}, /* P10: Camera (no OC) */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1} + }" + # EC range is 0xFD60 (EC_IO) and 0x68/0x6C register "gen1_dec" = "0x0004fd61" register "gen2_dec" = "0x00040069" @@ -89,7 +89,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f91b7d9f459d..077cb64576cb 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -50,22 +50,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ - { 0, 0, -1 }, /* P9: Empty */ - { 1, 0, -1 }, /* P10: Camera (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index 1c838a390b82..9b8d62174d26 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -29,7 +29,7 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ // group 1, front left/right @@ -39,10 +39,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 2, cap 1 @@ -52,7 +52,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x04a71021), /* Pin Complex (NID 0x1A) LINE1 PORTC */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE */ // group 2, cap 0 @@ -69,7 +69,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORTA? */ // group1, diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index aaa51dd84026..7bdfb5e17719 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -13,7 +13,7 @@ #include <intelblocks/power_limit.h> #include <smbios.h> #include <soc/ramstage.h> -#include <string.h> +#include <stdio.h> #include <variant/sku.h> #include <gpio.h> #include <delay.h> diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 7350fb05c801..b77513ba56f4 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -6,7 +6,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> #include <variant/sku.h> #define R_PCH_OC_WDT_CTL 0x54 diff --git a/src/mainboard/google/poppy/variants/rammus/mainboard.c b/src/mainboard/google/poppy/variants/rammus/mainboard.c index 90cf7cec611f..7eafebcff076 100644 --- a/src/mainboard/google/poppy/variants/rammus/mainboard.c +++ b/src/mainboard/google/poppy/variants/rammus/mainboard.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> #include <sar.h> #define SKU_UNKNOWN 0xFFFFFFFF diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 28496b15badf..b9aa870c109e 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -2,6 +2,7 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <soc/gpio.h> #include <soc/mrc_wrapper.h> #include <soc/romstage.h> @@ -38,7 +39,7 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) if (dual_channel_config & (1 << ram_id)) *dual = 1; - return &spd_file_content[SPD_SIZE * ram_id]; + return &spd_file_content[SPD_SIZE_MAX_DDR3 * ram_id]; } void mainboard_fill_mrc_params(struct mrc_params *mp) @@ -52,7 +53,7 @@ void mainboard_fill_mrc_params(struct mrc_params *mp) if (!spd_file) die("SPD data not found."); - spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, + spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE_MAX_DDR3, &dual_channel); mp->mainboard.dram_type = DRAM_DDR3L; diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h index c9cf327586d2..47e0a2671fed 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 1) | (1 << 3) | (1 << 5); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h index dcecbbeddc37..33ad2e62662a 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h @@ -24,7 +24,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 10); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h index c41b4aafae71..5105201114ee 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h index 8944e7b1505b..60c424d149d0 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h b/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h index 17d9acc35368..1536601f8cc1 100644 --- a/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h index d581de8e5f9b..e26402330533 100644 --- a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h @@ -24,7 +24,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 6) | (1 << 7); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h index 50e9ad872543..4df3c8d83c3a 100644 --- a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h index 2e00104265f8..b357c6f52679 100644 --- a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 6) | (1 << 7); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h index 25c3f373fbe3..ea3e8927923f 100644 --- a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h index 8a48c11e91e4..7b20daf1c787 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h index 4d8eebb5a0f1..16d39710997d 100644 --- a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h index 51051e25918b..d74551e270a3 100644 --- a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h index 46ee249f411a..a9bd04c942a3 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h @@ -17,7 +17,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h index 51051e25918b..d74551e270a3 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h index 8a48c11e91e4..7b20daf1c787 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h index 97094a952cb2..f5ec6a613d07 100644 --- a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h @@ -16,7 +16,6 @@ static const uint32_t dual_channel_config = (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h index f4aa2137274d..223823366607 100644 --- a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index ff3bb36e09c2..964fc1ce7463 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -10,7 +10,7 @@ #include <nhlt.h> #include <smbios.h> #include <soc/nhlt.h> -#include <string.h> +#include <stdio.h> #include <variant/ec.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 5e019ee38d46..9ee0bc066392 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -122,6 +122,11 @@ config BOARD_GOOGLE_OVIS4ES config BOARD_GOOGLE_REX0 select BOARD_GOOGLE_MODEL_REX +config BOARD_GOOGLE_REX64 + select BOARD_GOOGLE_MODEL_REX + select HAVE_X86_64_SUPPORT + select USE_X86_64_SUPPORT + config BOARD_GOOGLE_REX_EC_ISH select BOARD_GOOGLE_MODEL_REX_EC_ISH @@ -182,6 +187,7 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Rex" if BOARD_GOOGLE_REX0 + default "Rex64" if BOARD_GOOGLE_REX64 default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH default "Rex4ES" if BOARD_GOOGLE_REX4ES default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index 6aca8faca2f6..f4fed2a82855 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -32,6 +32,9 @@ config BOARD_GOOGLE_REX4ES config BOARD_GOOGLE_REX4ES_EC_ISH bool "-> Rex4ES EC ISH" +config BOARD_GOOGLE_REX64 + bool "-> Rex 64" + config BOARD_GOOGLE_SCREEBO bool "-> Screebo" diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index bf489ff52831..9157abbe38f1 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -9,6 +9,7 @@ #include <ec/ec.h> #include <fw_config.h> #include <soc/ramstage.h> +#include <stdio.h> #include <stdlib.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h index bd3d535c16a9..8a97d00deb98 100644 --- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h @@ -24,6 +24,9 @@ int variant_memory_sku(void); bool variant_is_half_populated(void); void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config); +/* Get soc power limit config struct for current CPU sku */ +struct soc_power_limits_config *variant_get_soc_power_limit_config(void); + enum s0ix_entry { S0IX_EXIT, S0IX_ENTRY, diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index aace5adcf4cb..7cb10d278c6a 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -86,6 +86,7 @@ chip soc/intel/meteorlake device domain 0 on device ref igpu on end device ref dtt on end + device ref vpu on end device ref ioe_shared_sram on end device ref xhci on end device ref pmc_shared_sram on end diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c index 1eec1ec01b9e..2798be6c7b94 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c @@ -1,8 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <intelblocks/power_limit.h> +#include <soc/pci_devs.h> + +struct soc_power_limits_config *variant_get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + size_t i = 0; + + if (mchid == 0xffff) + return NULL; + + for (i = 0; i < ARRAY_SIZE(cpuid_to_mtl); i++) { + if (mchid == cpuid_to_mtl[i].cpu_id && tdp == cpuid_to_mtl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_mtl[i].limits]; + } + } + + if (i == ARRAY_SIZE(cpuid_to_mtl)) { + printk(BIOS_ERR, "Cannot find correct ovis sku index.\n"); + return NULL; + } + + return NULL; +} /* * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 58c1719b4889..1a80e2aecb20 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -97,6 +97,7 @@ chip soc/intel/meteorlake device domain 0 on device ref igpu on end device ref dtt on end + device ref vpu on end device ref ioe_shared_sram on end device ref xhci on end device ref pmc_shared_sram on end diff --git a/src/mainboard/google/rex/variants/deku/Makefile.mk b/src/mainboard/google/rex/variants/deku/Makefile.mk index 91f031e7a474..090dd5be738d 100644 --- a/src/mainboard/google/rex/variants/deku/Makefile.mk +++ b/src/mainboard/google/rex/variants/deku/Makefile.mk @@ -3,3 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c index 52cb2e010304..55464dd46806 100644 --- a/src/mainboard/google/rex/variants/deku/gpio.c +++ b/src/mainboard/google/rex/variants/deku/gpio.c @@ -27,99 +27,99 @@ static const struct pad_config gpio_table[] = { /* GPP_A12 : [] ==> LAN1_ISOLATE_R_ODL */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* GPP_A13 : net NC is not present in the given design */ - PAD_NC(GPP_A13, UP_20K), + PAD_NC(GPP_A13, NONE), /* GPP_A14 : net NC is not present in the given design */ - PAD_NC(GPP_A14, UP_20K), + PAD_NC(GPP_A14, NONE), /* GPP_A15 : net NC is not present in the given design */ - PAD_NC(GPP_A15, UP_20K), + PAD_NC(GPP_A15, NONE), /* GPP_A16 : [] ==> ESPI_SOC_ALERT_L */ PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_A18 : net NC is not present in the given design */ - PAD_NC(GPP_A18, UP_20K), + PAD_NC(GPP_A18, NONE), /* GPP_A21 : [] ==> SOC_GPP_A21 */ - PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A21, NONE), /* GPP_B00 : net NC is not present in the given design */ - PAD_NC(GPP_B00, UP_20K), + PAD_NC(GPP_B00, NONE), /* GPP_B01 : [] ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_B01, 1, DEEP), /* GPP_B02 : net NC is not present in the given design */ - PAD_NC(GPP_B02, UP_20K), + PAD_NC(GPP_B02, NONE), /* GPP_B03 : net NC is not present in the given design */ - PAD_NC(GPP_B03, UP_20K), + PAD_NC(GPP_B03, NONE), /* GPP_B04 : [GPP_B04_STRAP] ==> Component NC */ - PAD_NC(GPP_B04, UP_20K), + PAD_NC(GPP_B04, NONE), /* GPP_B05 : net NC is not present in the given design */ - PAD_NC(GPP_B05, UP_20K), + PAD_NC(GPP_B05, NONE), /* GPP_B06 : net NC is not present in the given design */ - PAD_NC(GPP_B06, UP_20K), + PAD_NC(GPP_B06, NONE), /* GPP_B07 : net NC is not present in the given design */ - PAD_NC(GPP_B07, UP_20K), + PAD_NC(GPP_B07, NONE), /* GPP_B08 : [] ==> PWM_BUZZER */ PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPP_B09 : net NC is not present in the given design */ - PAD_NC(GPP_B09, UP_20K), + PAD_NC(GPP_B09, NONE), /* GPP_B10 : [] ==> WIFI_DISABLE_L */ PAD_CFG_GPO(GPP_B10, 1, DEEP), /* GPP_B11 : net NC is not present in the given design */ - PAD_NC(GPP_B11, UP_20K), + PAD_NC(GPP_B11, NONE), /* GPP_B12 : [] ==> SLP_S0_R_L */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 : [] ==> PLT_PCIE_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 : [GPP_B14_STRAP] ==> Component NC */ - PAD_NC(GPP_B14, UP_20K), + PAD_NC(GPP_B14, NONE), /* GPP_B15 : [] ==> USB_A_OC_ODL */ PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), /* GPP_B16 : net NC is not present in the given design */ - PAD_NC(GPP_B16, UP_20K), + PAD_NC(GPP_B16, NONE), /* GPP_B17 : net NC is not present in the given design */ - PAD_NC(GPP_B17, UP_20K), + PAD_NC(GPP_B17, NONE), /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), /* GPP_B20 : net NC is not present in the given design */ - PAD_NC(GPP_B20, UP_20K), + PAD_NC(GPP_B20, NONE), /* GPP_B21 : net NC is not present in the given design */ - PAD_NC(GPP_B21, UP_20K), + PAD_NC(GPP_B21, NONE), /* GPP_B22 : [] ==> USB_C_FORCE_PWR */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 : net NC is not present in the given design */ - PAD_NC(GPP_B23, UP_20K), + PAD_NC(GPP_B23, NONE), /* GPP_C00 : net NC is not present in the given design */ - PAD_NC(GPP_C00, UP_20K), + PAD_NC(GPP_C00, NONE), /* GPP_C01 : net NC is not present in the given design */ - PAD_NC(GPP_C01, UP_20K), + PAD_NC(GPP_C01, NONE), /* GPP_C02 : [GPP_C02_STRAP] ==> Component NC */ - PAD_NC(GPP_C02, UP_20K), + PAD_NC(GPP_C02, NONE), /* GPP_C03 : net NC is not present in the given design */ - PAD_NC(GPP_C03, UP_20K), + PAD_NC(GPP_C03, NONE), /* GPP_C04 : net NC is not present in the given design */ - PAD_NC(GPP_C04, UP_20K), + PAD_NC(GPP_C04, NONE), /* GPP_C05 : [GPP_C05_STRAP] ==> Component NC */ - PAD_NC(GPP_C05, UP_20K), + PAD_NC(GPP_C05, NONE), /* GPP_C06 : net NC is not present in the given design */ - PAD_NC(GPP_C06, UP_20K), + PAD_NC(GPP_C06, NONE), /* GPP_C07 : net NC is not present in the given design */ - PAD_NC(GPP_C07, UP_20K), + PAD_NC(GPP_C07, NONE), /* GPP_C08 : [] ==> SOCHOT_ODL */ PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), /* GPP_C09 : [] ==> MISC_SYNC_OD */ PAD_CFG_GPI(GPP_C09, NONE, DEEP), /* GPP_C10 : net NC is not present in the given design*/ - PAD_NC(GPP_C10, UP_20K), + PAD_NC(GPP_C10, NONE), /* GPP_C11 : [] ==> LAN1_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* GPP_C12 : net NC is not present in the given design */ - PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C12, NONE), /* GPP_C13 : [] ==> LAN0_PERST_L */ PAD_CFG_GPO_LOCK(GPP_C13, 1, LOCK_CONFIG), /* GPP_C15 : [GPP_C15_STRAP] ==> Component NC */ - PAD_NC(GPP_C15, UP_20K), + PAD_NC(GPP_C15, NONE), /* GPP_C16 : [] ==> USB_C0_LSX_TX */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GPP_C17 : [] ==> USB_C0_LSX_RX */ @@ -138,43 +138,43 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* GPP_D00 : net NC is not present in the given design */ - PAD_NC(GPP_D00, UP_20K), + PAD_NC(GPP_D00, NONE), /* GPP_D01 : [] ==> LAN1_PCIE_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_D01, NONE, DEEP, EDGE_SINGLE), /* GPP_D02 : [] ==> LAN1_PERST_L */ PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), /* GPP_D03 : net NC is not present in the given design */ - PAD_NC(GPP_D03, UP_20K), + PAD_NC(GPP_D03, NONE), /* GPP_D04 : net NC is not present in the given design */ - PAD_NC(GPP_D04, UP_20K), + PAD_NC(GPP_D04, NONE), /* GPP_D05 : [] ==> UART_DBG_TX_ISH_RX */ - PAD_NC(GPP_D05, UP_20K), + PAD_NC(GPP_D05, NONE), /* GPP_D06 : [] ==> UART_ISH_TX_DBG_RX */ - PAD_NC(GPP_D06, UP_20K), + PAD_NC(GPP_D06, NONE), /* GPP_D07 : [] ==> SOC_GPP_D07 */ - PAD_NC(GPP_D07, UP_20K), + PAD_NC(GPP_D07, NONE), /* GPP_D08 : net NC is not present in the given design */ - PAD_NC(GPP_D08, UP_20K), + PAD_NC(GPP_D08, NONE), /* GPP_D09 : net NC is not present in the given design */ - PAD_NC(GPP_D09, UP_20K), + PAD_NC(GPP_D09, NONE), /* GPP_D10 : net NC is not present in the given design */ - PAD_NC(GPP_D10, UP_20K), + PAD_NC(GPP_D10, NONE), /* GPP_D11 : net NC is not present in the given design */ - PAD_NC(GPP_D11, UP_20K), + PAD_NC(GPP_D11, NONE), /* GPP_D12 : [GPP_D12_STRAP] ==> Component NC */ - PAD_NC(GPP_D12, UP_20K), + PAD_NC(GPP_D12, NONE), /* GPP_D13 : net NC is not present in the given design */ - PAD_NC(GPP_D13, UP_20K), + PAD_NC(GPP_D13, NONE), /* GPP_D14 : net NC is not present in the given design */ - PAD_NC(GPP_D14, UP_20K), + PAD_NC(GPP_D14, NONE), /* GPP_D15 : net NC is not present in the given design */ - PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D15, NONE), /* GPP_D16 : net NC is not present in the given design */ - PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D16, NONE), /* GPP_D17 : net NC is not present in the given design */ - PAD_NC(GPP_D17, UP_20K), + PAD_NC(GPP_D17, NONE), /* GPP_D18 : net NC is not present in the given design */ - PAD_NC(GPP_D18, UP_20K), + PAD_NC(GPP_D18, NONE), /* GPP_D19 : [] ==> SSD_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* GPP_D20 : [] ==> LAN0_PCIE_CLKREQ_ODL */ @@ -182,12 +182,12 @@ static const struct pad_config gpio_table[] = { /* GPP_D21 : [] ==> WLAN_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* GPP_D22 : [] ==> SOC_DBG_BPKI3C_SDA */ - PAD_NC(GPP_D22, UP_20K), + PAD_NC(GPP_D22, NONE), /* GPP_D23 : [] ==> SOC_DBG_BPKI3C_SCL */ - PAD_NC(GPP_D23, UP_20K), + PAD_NC(GPP_D23, NONE), /* GPP_E00 : net NC is not present in the given design */ - PAD_NC(GPP_E00, UP_20K), + PAD_NC(GPP_E00, NONE), /* GPP_E01 : [] ==> MEM_STRAP_2 */ PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), /* GPP_E02 : [] ==> MEM_STRAP_1 */ @@ -199,15 +199,15 @@ static const struct pad_config gpio_table[] = { /* GPP_E05 : [] ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_E05, NONE, PLTRST, LEVEL, INVERT), /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ - PAD_NC(GPP_E06, UP_20K), + PAD_NC(GPP_E06, NONE), /* GPP_E07 : net NC is not present in the given design */ - PAD_NC(GPP_E07, UP_20K), + PAD_NC(GPP_E07, NONE), /* GPP_E08 : [] ==> USB_C0_AUX_DC_N */ PAD_CFG_NF(GPP_E08, NONE, DEEP, NF6), /* GPP_E09 : [] ==> USB_C_OC_ODL */ PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), /* GPP_E10 : net NC is not present in the given design */ - PAD_NC(GPP_E10, UP_20K), + PAD_NC(GPP_E10, NONE), /* GPP_E11 : [] ==> MEM_STRAP_0 */ PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* GPP_E12 : [] ==> MEM_STRAP_3 */ @@ -215,13 +215,13 @@ static const struct pad_config gpio_table[] = { /* GPP_E13 : [] ==> MEM_CH_SEL */ PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* GPP_E14 : net NC is not present in the given design */ - PAD_NC(GPP_E14, UP_20K), + PAD_NC(GPP_E14, NONE), /* GPP_E15 : [] ==> SOC_GPP_E15 */ - PAD_NC(GPP_E15, UP_20K), + PAD_NC(GPP_E15, NONE), /* GPP_E16 : [] ==> GPP_E16_ISH_GP10 */ - PAD_NC(GPP_E16, UP_20K), + PAD_NC(GPP_E16, NONE), /* GPP_E17 : net NC is not present in the given design */ - PAD_NC(GPP_E17, UP_20K), + PAD_NC(GPP_E17, NONE), /* GPP_E22 : [] ==> USB_C0_AUX_DC_P */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), @@ -240,13 +240,13 @@ static const struct pad_config gpio_table[] = { /* GPP_F06 : [] ==> WLAN_COEX3 */ PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* GPP_F07 : net NC is not present in the given design */ - PAD_NC(GPP_F07, UP_20K), + PAD_NC(GPP_F07, NONE), /* GPP_F08 : [] ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_F08, 1, DEEP), /* GPP_F09 : net NC is not present in the given design */ - PAD_NC(GPP_F09, UP_20K), + PAD_NC(GPP_F09, NONE), /* GPP_F10 : net NC is not present in the given design */ - PAD_NC(GPP_F10, UP_20K), + PAD_NC(GPP_F10, NONE), /* GPP_F11 : [] ==> AV_GPIO_P0 */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* GPP_F12 : [] ==> AV_GPIO_P1 */ @@ -264,30 +264,30 @@ static const struct pad_config gpio_table[] = { /* GPP_F18 : [] ==> AV_GPIO_P7 */ PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPP_F19 : [GPP_F19_STRAP] ==> Component NC */ - PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F19, NONE), /* GPP_F20 : [GPP_F20_STRAP] ==> Component NC */ - PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F20, NONE), /* GPP_F21 : [GPP_F21_STRAP] ==> Component NC */ - PAD_NC(GPP_F21, UP_20K), + PAD_NC(GPP_F21, NONE), /* GPP_F22 : [] ==> GPP_F22_ISH_GP8A */ - PAD_NC(GPP_F22, UP_20K), + PAD_NC(GPP_F22, NONE), /* GPP_F23 : [] ==> GPP_F23_ISH_GP9A */ - PAD_NC(GPP_F23, UP_20K), + PAD_NC(GPP_F23, NONE), /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ - PAD_NC(GPP_H00, UP_20K), + PAD_NC(GPP_H00, NONE), /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ - PAD_NC(GPP_H01, UP_20K), + PAD_NC(GPP_H01, NONE), /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ - PAD_NC(GPP_H02, UP_20K), + PAD_NC(GPP_H02, NONE), /* GPP_H04 : [] ==> WLAN_COEX1 */ PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* GPP_H05 : [] ==> WLAN_COEX2 */ PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), /* GPP_H06 : net NC is not present in the given design */ - PAD_NC(GPP_H06, UP_20K), + PAD_NC(GPP_H06, NONE), /* GPP_H07 : net NC is not present in the given design */ - PAD_NC(GPP_H07, UP_20K), + PAD_NC(GPP_H07, NONE), /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ @@ -295,42 +295,42 @@ static const struct pad_config gpio_table[] = { /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), /* GPP_H11 : net NC is not present in the given design */ - PAD_NC(GPP_H11, UP_20K), + PAD_NC(GPP_H11, NONE), /* GPP_H13 : [] ==> CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* GPP_H14 : [] ==> SLP_S0_GATE_R */ PAD_CFG_GPO(GPP_H14, 1, PLTRST), /* GPP_H15 : net NC is not present in the given design */ - PAD_NC(GPP_H15, UP_20K), + PAD_NC(GPP_H15, NONE), /* GPP_H16 : net NC is not present in the given design */ - PAD_NC(GPP_H16, UP_20K), + PAD_NC(GPP_H16, NONE), /* GPP_H17 : net NC is not present in the given design */ - PAD_NC(GPP_H17, UP_20K), + PAD_NC(GPP_H17, NONE), /* GPP_H19 : net NC is not present in the given design */ - PAD_NC(GPP_H19, UP_20K), + PAD_NC(GPP_H19, NONE), /* GPP_H20 : net NC is not present in the given design */ - PAD_NC(GPP_H20, UP_20K), + PAD_NC(GPP_H20, NONE), /* GPP_H21 : net NC is not present in the given design */ - PAD_NC(GPP_H21, UP_20K), + PAD_NC(GPP_H21, NONE), /* GPP_H22 : net NC is not present in the given design */ - PAD_NC(GPP_H22, UP_20K), + PAD_NC(GPP_H22, NONE), /* GPP_S00 : net NC is not present in the given design */ - PAD_NC(GPP_S00, UP_20K), + PAD_NC(GPP_S00, NONE), /* GPP_S01 : net NC is not present in the given design */ - PAD_NC(GPP_S01, UP_20K), + PAD_NC(GPP_S01, NONE), /* GPP_S02 : net NC is not present in the given design */ - PAD_NC(GPP_S02, UP_20K), + PAD_NC(GPP_S02, NONE), /* GPP_S03 : net NC is not present in the given design */ - PAD_NC(GPP_S03, UP_20K), + PAD_NC(GPP_S03, NONE), /* GPP_S04 : net NC is not present in the given design */ - PAD_NC(GPP_S04, UP_20K), + PAD_NC(GPP_S04, NONE), /* GPP_S05 : net NC is not present in the given design */ - PAD_NC(GPP_S05, UP_20K), + PAD_NC(GPP_S05, NONE), /* GPP_S06 : net NC is not present in the given design */ - PAD_NC(GPP_S06, UP_20K), + PAD_NC(GPP_S06, NONE), /* GPP_S07 : net NC is not present in the given design */ - PAD_NC(GPP_S07, UP_20K), + PAD_NC(GPP_S07, NONE), /* GPP_V00 : [] ==> BATLOW_L */ PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), @@ -359,9 +359,9 @@ static const struct pad_config gpio_table[] = { /* GPP_V14 : [] ==> SOC_WAKE_L */ PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* GPP_V22 : net NC is not present in the given design */ - PAD_NC(GPP_V22, UP_20K), + PAD_NC(GPP_V22, NONE), /* GPP_V23 : net NC is not present in the given design */ - PAD_NC(GPP_V23, UP_20K), + PAD_NC(GPP_V23, NONE), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 070f596d3d05..fcacbead862d 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -27,6 +27,15 @@ chip soc/intel/meteorlake [DDI_PORT_4] = DDI_ENABLE_HPD, }" + # Temporary setting TCC of 105C = Tj max (110) - TCC_Offset (5) + register "tcc_offset" = "5" + + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 33, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + }" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -54,9 +63,57 @@ chip soc/intel/meteorlake }, }" + register "psys_pmax_watts" = "180" + register "psys_pl2_watts" = "178" + + # As per doc 640982, Intel MTL-U 28W CPU supports FVM on GT and SA + # The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A + # For GT VR configuration + register "enable_fast_vmode[VR_DOMAIN_GT]" = "1" + register "cep_enable[VR_DOMAIN_GT]" = "1" + register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "216" # 54A + # For SA VR configuration + register "enable_fast_vmode[VR_DOMAIN_SA]" = "1" + register "cep_enable[VR_DOMAIN_SA]" = "1" + register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "108" # 27A + device domain 0 on device ref dtt on chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""IMVP_SOC"" + register "options.tsr[3].desc" = ""NVME"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 65, 1000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 28000, + .max_power = 28000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 64000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 alias dptf_policy on end end end diff --git a/src/mainboard/google/rex/variants/deku/ramstage.c b/src/mainboard/google/rex/variants/deku/ramstage.c new file mode 100644 index 000000000000..7cb324dd6793 --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/ramstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ +const struct cpu_tdp_power_limits variant_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_1, + .cpu_tdp = 28, + .pl1_min_power = 19000, + .pl1_max_power = 28000, + .pl2_min_power = 64000, + .pl2_max_power = 64000, + .pl4_power = 120000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_3, + .cpu_tdp = 28, + .pl1_min_power = 19000, + .pl1_max_power = 28000, + .pl2_min_power = 64000, + .pl2_max_power = 64000, + .pl4_power = 120000 + }, +}; + +void variant_devtree_update(void) +{ + struct soc_power_limits_config *soc_config; + struct soc_intel_meteorlake_config *config = config_of_soc(); + + soc_config = variant_get_soc_power_limit_config(); + if (soc_config == NULL) + return; + + if (config->psys_pl2_watts) { + soc_config->tdp_psyspl2 = config->psys_pl2_watts; + printk(BIOS_INFO, "Overriding PsysPL2 (%u)\n", soc_config->tdp_psyspl2); + } + + const struct cpu_tdp_power_limits *limits = variant_limits; + size_t total_entries = ARRAY_SIZE(variant_limits); + variant_update_cpu_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index c65493322d55..c74b51c69b16 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -34,10 +34,6 @@ fw_config option DISABLE 0 option ENABLE 1 end - field VPU 22 - option VPU_DIS 0 - option VPU_EN 1 - end end chip soc/intel/meteorlake @@ -585,8 +581,5 @@ chip soc/intel/meteorlake end end device ref hda on end - device ref vpu on - probe VPU VPU_EN - end end end diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 9d8f9ff75b77..d492bd17a757 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -45,6 +45,8 @@ static const struct pad_config gpio_table[] = { /* GPP_A18 : [] ==> CAM_PSW_L */ PAD_CFG_GPI_INT_LOCK(GPP_A18, NONE, EDGE_BOTH, LOCK_CONFIG), + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_A19, 1, LOCK_CONFIG), /* GPP_A21 : [] ==> WWAN_CONFIG2 */ PAD_CFG_GPI(GPP_A21, NONE, DEEP), diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 12068ce1dd88..1d1957a692c3 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -52,10 +52,6 @@ fw_config option ISH_DISABLE 0 option ISH_ENABLE 1 end - field VPU 22 - option VPU_DIS 0 - option VPU_EN 1 - end end chip soc/intel/meteorlake @@ -323,9 +319,6 @@ chip soc/intel/meteorlake end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp2 on end - device ref vpu on - probe VPU VPU_EN - end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index fdfe9843cf11..c66b5cb2b923 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -30,10 +30,6 @@ fw_config option WIFI_SAR_ID_0 0 option WIFI_SAR_ID_1 1 end - field VPU 22 - option VPU_DIS 0 - option VPU_EN 1 - end end chip soc/intel/meteorlake @@ -602,8 +598,5 @@ chip soc/intel/meteorlake end end end - device ref vpu on - probe VPU VPU_EN - end end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93ec7cf9ca79..fcaa73024030 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -208,21 +208,17 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""arcada_ish.bin"" device generic 0 on end end end - device pci 14.0 on + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -296,16 +292,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" @@ -319,8 +313,8 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x1" device i2c 0A on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -336,65 +330,38 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x20" device i2c 2a on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on + end + device ref sata on end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on + end + device ref uart2 on end + device ref pcie_rp10 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[9]" = "1" - end # PCI Express Port 10 - device pci 1d.2 on # PCI Express Port 11 + end + device ref pcie_rp11 on register "PcieRpSlotImplemented[10]" = "1" end - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + device ref pcie_rp13 on + # x4 lanes chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/google/sarien/variants/arcada/hda_verb.c b/src/mainboard/google/sarien/variants/arcada/hda_verb.c index 2ddb8acfe7a3..810ca8b815a8 100644 --- a/src/mainboard/google/sarien/variants/arcada/hda_verb.c +++ b/src/mainboard/google/sarien/variants/arcada/hda_verb.c @@ -15,14 +15,14 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x12, 0xb7a60130), - AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x16, 0x40000000), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40c00001), AZALIA_PIN_CFG(0, 0x1e, 0x421212f2), AZALIA_PIN_CFG(0, 0x21, 0x04211020), diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b21623555012..589ea1c3aa62 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -213,16 +213,11 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -308,16 +303,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" @@ -349,8 +342,8 @@ chip soc/intel/cannonlake register "device_present_gpio_invert" = "1" device i2c 34 on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -358,73 +351,50 @@ chip soc/intel/cannonlake register "detect" = "1" device i2c 2c on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on + end + device ref sata on end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 on # PCI Express Port 1 (USB) + end + device ref uart2 on end + device ref pcie_rp1 on + # USB register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 + device ref pcie_rp8 on register "PcieRpSlotImplemented[7]" = "1" end - device pci 1d.0 on + device ref pcie_rp9 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" - end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 + end + device ref pcie_rp10 on register "PcieRpSlotImplemented[9]" = "1" end - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + device ref pcie_rp13 on + # x4 lanes chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + end + device ref hda on end + device ref smbus on end + device ref gbe on end end end diff --git a/src/mainboard/google/sarien/variants/sarien/hda_verb.c b/src/mainboard/google/sarien/variants/sarien/hda_verb.c index 0972a11b8f58..feea154b662e 100644 --- a/src/mainboard/google/sarien/variants/sarien/hda_verb.c +++ b/src/mainboard/google/sarien/variants/sarien/hda_verb.c @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40700001), AZALIA_PIN_CFG(0, 0x1e, 0x421212f2), AZALIA_PIN_CFG(0, 0x21, 0x04211020), diff --git a/src/mainboard/google/slippy/variants/falco/hda_verb.c b/src/mainboard/google/slippy/variants/falco/hda_verb.c index b64c2dbe3b06..f79300c35028 100644 --- a/src/mainboard/google/slippy/variants/falco/hda_verb.c +++ b/src/mainboard/google/slippy/variants/falco/hda_verb.c @@ -29,10 +29,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -42,10 +42,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -55,7 +55,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/slippy/variants/leon/hda_verb.c b/src/mainboard/google/slippy/variants/leon/hda_verb.c index 633ccdc7419b..b71bb7592f18 100644 --- a/src/mainboard/google/slippy/variants/leon/hda_verb.c +++ b/src/mainboard/google/slippy/variants/leon/hda_verb.c @@ -29,10 +29,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -42,10 +42,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -55,7 +55,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/slippy/variants/peppy/hda_verb.c b/src/mainboard/google/slippy/variants/peppy/hda_verb.c index 575ac77573a5..36fd80bc7a14 100644 --- a/src/mainboard/google/slippy/variants/peppy/hda_verb.c +++ b/src/mainboard/google/slippy/variants/peppy/hda_verb.c @@ -19,7 +19,7 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ // group 1, cap 0 @@ -29,10 +29,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -49,7 +49,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1a, 0x90a70111), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c index 53d19d2c0c26..f4c5606000cf 100644 --- a/src/mainboard/google/slippy/variants/wolf/hda_verb.c +++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c @@ -34,10 +34,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -47,10 +47,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -60,7 +60,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 8fd19fce5876..0211921c387d 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 1, 0x0000 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 1, 0x0000 }, - { 0, 1, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 5, 0x0040 },}" - register "usb3.mode" = "2" # Auto register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1 register "usb3.preboot_support" = "0" # No PreOS boot support @@ -79,6 +63,23 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, 0, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {0, 0, 0}, /* P8: Empty */ + {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, /* P10: Empty */ + {0, 0, 0}, /* P11: Empty */ + {0, 0, 0}, /* P12: Empty */ + {1, 0, -1}, /* P13: Bluetooth (no OC) */ + }" + device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index e6e62276465e..178d270da71d 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -90,21 +90,3 @@ void mainboard_early_init(int s3resume) early_ec_init(); } } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled USB oc pin length */ - {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ - {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, /* P2: Empty */ - {1, 0, -1}, /* P3: Camera (no OC) */ - {1, 0, -1}, /* P4: WLAN (no OC) */ - {1, 0, -1}, /* P5: WWAN (no OC) */ - {0, 0, 0}, /* P6: Empty */ - {0, 0, 0}, /* P7: Empty */ - {0, 0, 0}, /* P8: Empty */ - {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ - {0, 0, 0}, /* P10: Empty */ - {0, 0, 0}, /* P11: Empty */ - {0, 0, 0}, /* P12: Empty */ - {1, 0, -1}, /* P13: Bluetooth (no OC) */ -}; diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index fba96644e56f..ae7519e10e25 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -12,6 +12,7 @@ #include <intelblocks/tcss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <stdio.h> #include <variant/gpio.h> #include <vb2_api.h> diff --git a/src/mainboard/google/volteer/variants/drobit/data.vbt b/src/mainboard/google/volteer/variants/drobit/data.vbt Binary files differindex f066fbdb2a46..de72dddce2b1 100644 --- a/src/mainboard/google/volteer/variants/drobit/data.vbt +++ b/src/mainboard/google/volteer/variants/drobit/data.vbt |