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-rw-r--r--src/mainboard/intel/d945gclf/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 4007e7ecc4f6..70a3819c4b9c 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -34,7 +34,7 @@ chip northbridge/intel/i945
register "ide_enable_primary" = "true"
register "ide_enable_secondary" = "false"
register "c3_latency" = "85"
- register "p_cnt_throttling_supported" = "0"
+ register "p_cnt_throttling_supported" = "false"
register "gen1_dec" = "0x0007c0681" # SuperIO Power Management