diff options
Diffstat (limited to 'src/mainboard/intel')
54 files changed, 576 insertions, 167 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 1083ce2b9c41..5ee091bc8be5 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -135,9 +135,6 @@ config DEVICETREE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config DIMM_SPD_SIZE - default 512 - choice prompt "ON BOARD EC" default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index 9ac480d4866b..c02cbf9a58db 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -11,7 +11,7 @@ #include <smbios.h> #include <soc/gpio.h> #include <stdint.h> -#include <string.h> +#include <stdio.h> #include "board_id.h" diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c index 6e4bd8e11ef9..9189099df9c7 100644 --- a/src/mainboard/intel/archercity_crb/romstage.c +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -11,7 +11,8 @@ void mainboard_ewl_check(void) { - get_ewl(); + if (CONFIG(OCP_EWL)) + get_ewl(); } static void mainboard_config_iio(FSPM_UPD *mupd) @@ -35,15 +36,23 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; + /* Setup FSP log */ + if (CONFIG(OCP_VPD)) { + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } + } - /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", - FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); } /* Set Rank Margin Tool to disable. */ diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig b/src/mainboard/intel/avenuecity_crb/Kconfig new file mode 100644 index 000000000000..fff244e92eb7 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_AVENUECITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select OCP_VPD + select MEMORY_MAPPED_TPM + +config CARDBUS_PLUGIN_SUPPORT + bool + default n + +config MAINBOARD_DIR + string + default "intel/avenuecity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Avenue City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig.name b/src/mainboard/intel/avenuecity_crb/Kconfig.name new file mode 100644 index 000000000000..f73d1d936ff3 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_AVENUECITY_CRB + bool "Avenue City CRB" diff --git a/src/mainboard/intel/avenuecity_crb/Makefile.mk b/src/mainboard/intel/avenuecity_crb/Makefile.mk new file mode 100644 index 000000000000..2e1a74a45a59 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +romstage-y += config/iio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/avenuecity_crb/board.fmd b/src/mainboard/intel/avenuecity_crb/board.fmd new file mode 100644 index 000000000000..df5bc059f414 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board.fmd @@ -0,0 +1,12 @@ +FLASH@0xfc000000 64M { + SI_ALL 48M { + SI_DESC@0x0 0x1000 + } + SI_BIOS 16M { + RW_MRC_CACHE 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/intel/avenuecity_crb/board_info.txt b/src/mainboard/intel/avenuecity_crb/board_info.txt new file mode 100644 index 000000000000..2c502cfdf2b6 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Avenue City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/avenuecity_crb/bootblock.c b/src/mainboard/intel/avenuecity_crb/bootblock.c new file mode 100644 index 000000000000..e68d874c900e --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/bootblock.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/avenuecity_crb/config/iio.c b/src/mainboard/intel/avenuecity_crb/config/iio.c new file mode 100644 index 000000000000..117d604a2dc0 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/config/iio.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/iio.h> + +static const struct iio_pe_config iio_config_table[] = { + /* + * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated + * then port settings are listed accordingly. The minimal port elements are x2. + * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be + * disabled. + */ + {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { + /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ + _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5), + }}, +}; + +const struct iio_pe_config *get_iio_config_table(int *size) +{ + *size = ARRAY_SIZE(iio_config_table); + return iio_config_table; +} diff --git a/src/mainboard/intel/avenuecity_crb/devicetree.cb b/src/mainboard/intel/avenuecity_crb/devicetree.cb new file mode 100644 index 000000000000..0754916c393e --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/devicetree.cb @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE + + device domain 0 on + device pci 1f.0 on + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + end +end diff --git a/src/mainboard/intel/avenuecity_crb/dsdt.asl b/src/mainboard/intel/avenuecity_crb/dsdt.asl new file mode 100644 index 000000000000..34c29374faff --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/avenuecity_crb/ramstage.c b/src/mainboard/intel/avenuecity_crb/ramstage.c new file mode 100644 index 000000000000..a09016d46114 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + +} diff --git a/src/mainboard/intel/avenuecity_crb/romstage.c b/src/mainboard/intel/avenuecity_crb/romstage.c new file mode 100644 index 000000000000..f0e67af21efb --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/romstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/ocp/include/vpd.h> +#include <drivers/vpd/vpd.h> +#include <fmap_config.h> +#include <device/device.h> +#include <soc/ddr.h> +#include <soc/iio.h> +#include <soc/romstage.h> + +#include "chip.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + /* FSP log outputs */ + const config_t *config = config_of_soc(); + m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base; + m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT); + m_cfg->DebugPrintLevel = config->debug_print_level; + m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL, + FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ + m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START; + m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE; + printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase); + printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize); + + /* IIO init */ + int size; + const struct iio_pe_config *iio_config_table = get_iio_config_table(&size); + soc_config_iio_pe_ports(mupd, iio_config_table, size); +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + //TODO: not implemented yet + return false; +} diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig b/src/mainboard/intel/beechnutcity_crb/Kconfig new file mode 100644 index 000000000000..3c2f02a9ea70 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_BEECHNUTCITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select OCP_VPD + select MEMORY_MAPPED_TPM + +config CARDBUS_PLUGIN_SUPPORT + bool + default n + +config MAINBOARD_DIR + string + default "intel/beechnutcity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Beechnut City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig.name b/src/mainboard/intel/beechnutcity_crb/Kconfig.name new file mode 100644 index 000000000000..083fbf033527 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_BEECHNUTCITY_CRB + bool "Beechnut City CRB" diff --git a/src/mainboard/intel/beechnutcity_crb/Makefile.mk b/src/mainboard/intel/beechnutcity_crb/Makefile.mk new file mode 100644 index 000000000000..2e1a74a45a59 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +romstage-y += config/iio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/beechnutcity_crb/board.fmd b/src/mainboard/intel/beechnutcity_crb/board.fmd new file mode 100644 index 000000000000..df5bc059f414 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board.fmd @@ -0,0 +1,12 @@ +FLASH@0xfc000000 64M { + SI_ALL 48M { + SI_DESC@0x0 0x1000 + } + SI_BIOS 16M { + RW_MRC_CACHE 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/intel/beechnutcity_crb/board_info.txt b/src/mainboard/intel/beechnutcity_crb/board_info.txt new file mode 100644 index 000000000000..1de903ec8a36 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Beechnut City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/beechnutcity_crb/bootblock.c b/src/mainboard/intel/beechnutcity_crb/bootblock.c new file mode 100644 index 000000000000..e68d874c900e --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/bootblock.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/beechnutcity_crb/config/iio.c b/src/mainboard/intel/beechnutcity_crb/config/iio.c new file mode 100644 index 000000000000..117d604a2dc0 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/config/iio.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/iio.h> + +static const struct iio_pe_config iio_config_table[] = { + /* + * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated + * then port settings are listed accordingly. The minimal port elements are x2. + * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be + * disabled. + */ + {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { + /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ + _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5), + }}, +}; + +const struct iio_pe_config *get_iio_config_table(int *size) +{ + *size = ARRAY_SIZE(iio_config_table); + return iio_config_table; +} diff --git a/src/mainboard/intel/beechnutcity_crb/devicetree.cb b/src/mainboard/intel/beechnutcity_crb/devicetree.cb new file mode 100644 index 000000000000..0754916c393e --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/devicetree.cb @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE + + device domain 0 on + device pci 1f.0 on + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + end +end diff --git a/src/mainboard/intel/beechnutcity_crb/dsdt.asl b/src/mainboard/intel/beechnutcity_crb/dsdt.asl new file mode 100644 index 000000000000..34c29374faff --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/beechnutcity_crb/ramstage.c b/src/mainboard/intel/beechnutcity_crb/ramstage.c new file mode 100644 index 000000000000..a09016d46114 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + +} diff --git a/src/mainboard/intel/beechnutcity_crb/romstage.c b/src/mainboard/intel/beechnutcity_crb/romstage.c new file mode 100644 index 000000000000..f0e67af21efb --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/romstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/ocp/include/vpd.h> +#include <drivers/vpd/vpd.h> +#include <fmap_config.h> +#include <device/device.h> +#include <soc/ddr.h> +#include <soc/iio.h> +#include <soc/romstage.h> + +#include "chip.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + /* FSP log outputs */ + const config_t *config = config_of_soc(); + m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base; + m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT); + m_cfg->DebugPrintLevel = config->debug_print_level; + m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL, + FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ + m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START; + m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE; + printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase); + printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize); + + /* IIO init */ + int size; + const struct iio_pe_config *iio_config_table = get_iio_config_table(&size); + soc_config_iio_pe_ports(mupd, iio_config_table, size); +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + //TODO: not implemented yet + return false; +} diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 3d8321793c7a..59ce66c8d72d 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock( { Device (PCI0) { - #include <soc/intel/xeon_sp/acpi/southcluster.asl> + #include <soc/intel/xeon_sp/acpi/gen1/southcluster.asl> #include <soc/intel/common/block/acpi/acpi/lpc.asl> } diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c index 90833269e400..df30c471f816 100644 --- a/src/mainboard/intel/coffeelake_rvp/bootblock.c +++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c @@ -2,7 +2,7 @@ #include <baseboard/variants.h> #include <bootblock_common.h> -#include <soc/gpio.h> +#include <gpio.h> void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index eb9a316a34b6..481f71562439 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <device/device.h> #include <nhlt.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/nhlt.h> static void mainboard_init(void *chip_info) diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h index 102f5e12eba2..848024ec10fc 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -3,6 +3,6 @@ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ -#include <soc/gpio.h> +#include <gpio.h> #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index 6ae25d4d8487..d93c446f1343 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -4,7 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/cnl_memcfg_init.h> -#include <soc/gpio.h> +#include <gpio.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c index 7a5215508285..2ec1e7e28757 100644 --- a/src/mainboard/intel/d510mo/hda_verb.c +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -10,13 +10,13 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014410), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19841), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214420), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4015c603), AZALIA_PIN_CFG(0, 0x1e, 0x99430130), }; diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index f4e948f76c1c..954f572b312e 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -15,22 +15,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "666" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - register "usb_port_config" = "{ - {1, 0, 0x0040}, - {1, 0, 0x0040}, - {1, 1, 0x0040}, - {1, 1, 0x0040}, - {1, 2, 0x0040}, - {1, 2, 0x0040}, - {1, 3, 0x0040}, - {0, 3, 0x0040}, - {0, 4, 0x0040}, - {0, 4, 0x0040}, - {0, 5, 0x0040}, - {0, 5, 0x0040}, - {0, 6, 0x0040}, - {0, 6, 0x0040}, }" - device domain 0 on device ref host_bridge on end # Host bridge device ref peg10 off end # PCIe Bridge for discrete graphics @@ -43,6 +27,23 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + register "usb_port_config" = "{ + {1, 1, 0}, /* back, towards HDMI plugs */ + {1, 1, 0}, /* back, towards power plug */ + {1, 1, 1}, /* half-width miniPCIe */ + {1, 1, 1}, /* full-width miniPCIe */ + {1, 1, 2}, /* front-panel header */ + {1, 1, 2}, /* front-panel header */ + {1, 1, 3}, /* front connector */ + {0, 1, 3}, /* not available x7 */ + {0, 1, 4}, + {0, 1, 4}, + {0, 1, 5}, + {0, 1, 5}, + {0, 1, 6}, + {0, 1, 6} + }" + device ref xhci off end # USB xHCI device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index e0f27bab51f0..a137e35d4227 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -124,8 +124,3 @@ void bootblock_mainboard_early_init(void) superio_init(); hwm_init(); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { -#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin } -#include "usb.h" -}; diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h deleted file mode 100644 index 24693098a690..000000000000 --- a/src/mainboard/intel/dcp847ske/usb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DCP847SKE_USB_H -#define DCP847SKE_USB_H - -USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */ -USB_CONFIG(1, 1, 0), /* back, towards power plug */ -USB_CONFIG(1, 1, 1), /* half-width miniPCIe */ -USB_CONFIG(1, 1, 1), /* full-width miniPCIe */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 3), /* front connector */ -USB_CONFIG(0, 1, 3), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ - -#endif diff --git a/src/mainboard/intel/dg41wv/hda_verb.c b/src/mainboard/intel/dg41wv/hda_verb.c index 700953675da5..5bef966e75a4 100644 --- a/src/mainboard/intel/dg41wv/hda_verb.c +++ b/src/mainboard/intel/dg41wv/hda_verb.c @@ -12,8 +12,8 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), diff --git a/src/mainboard/intel/dg43gt/hda_verb.c b/src/mainboard/intel/dg43gt/hda_verb.c index 235ed285428d..00ec79cfef0c 100644 --- a/src/mainboard/intel/dg43gt/hda_verb.c +++ b/src/mainboard/intel/dg43gt/hda_verb.c @@ -11,19 +11,19 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x11, 0x01452140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014410), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19850), AZALIA_PIN_CFG(0, 0x19, 0x02a19960), AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), AZALIA_PIN_CFG(0, 0x1b, 0x02214520), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4006f601), AZALIA_PIN_CFG(0, 0x1e, 0x99430130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* HDMI */ 0x80862803, diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb index f29b772e8a43..6a28bcc1bf0a 100644 --- a/src/mainboard/intel/dq67sw/devicetree.cb +++ b/src/mainboard/intel/dq67sw/devicetree.cb @@ -14,6 +14,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref mei1 on end # Management Engine Interface 1 device ref me_ide_r on end # Management Engine IDE-R device ref me_kt on end # Management Engine KT diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c index 14317a69e0b6..f7515a540c4f 100644 --- a/src/mainboard/intel/dq67sw/early_init.c +++ b/src/mainboard/intel/dq67sw/early_init.c @@ -1,29 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 4 }, - { 0, 0, 5 }, - { 0, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/intel/dq67sw/hda_verb.c b/src/mainboard/intel/dq67sw/hda_verb.c index 81794c15ad15..8fbd95858d85 100644 --- a/src/mainboard/intel/dq67sw/hda_verb.c +++ b/src/mainboard/intel/dq67sw/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x80862008, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x80862008), - AZALIA_PIN_CFG(2, 0x11, 0x411111f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x17, 0x99130140), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19960), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214120), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), AZALIA_PIN_CFG(2, 0x1e, 0x99430130), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80862008, /* Subsystem ID */ diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index e75505e270c2..e547ff111f09 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -14,22 +14,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 2, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 6, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end @@ -58,6 +42,22 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x000c0181" # SuperIO range is 0x700-0x73f register "gen3_dec" = "0x003c0701" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 0, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ + }" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 19747135208a..329f13d2c160 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -47,21 +47,3 @@ void bootblock_mainboard_early_init(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, 0 }, /* P0: Front port (OC0) */ - { 1, 0, 1 }, /* P1: Back port (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 1, 0, 2 }, /* P4: Front port (OC2) */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, 4 }, /* P8: Back port (OC4) */ - { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 1, 0, 6 }, /* P12: Back port (OC6) */ - { 1, 0, 5 }, /* P13: Back port (OC5) */ -}; diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 35dcc4b29d49..ba2f879047ce 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -2,7 +2,6 @@ #include <baseboard/variants.h> #include <boardid.h> -#include <stddef.h> #include <ec/acpi/ec.h> #define BOARD_ID_GLK_RVP1_DDR4 0x5 /* RVP1 - DDR4 */ diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index e3912ec91efd..d3cefa6b20f3 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -2,6 +2,8 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr4.h> +#include <spd.h> #include "spd.h" @@ -19,17 +21,17 @@ uint8_t *mainboard_find_spd_data(void) if (!spd_file) die("SPD data not found."); - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR4)) { printk(BIOS_ERR, "SPD index override to 0 due to incorrect SPD index.\n"); spd_index = 0; } - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR4) die("Missing SPD data."); /* Assume same memory in both channels */ - spd_index *= SPD_LEN; + spd_index *= SPD_SIZE_MAX_DDR4; spd_data = (uint8_t *)(spd_file + spd_index); /* Make sure a valid SPD was found */ diff --git a/src/mainboard/intel/harcuvar/spd/spd.h b/src/mainboard/intel/harcuvar/spd/spd.h index 44eec02a6b97..92377fd9ac88 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.h +++ b/src/mainboard/intel/harcuvar/spd/spd.h @@ -5,18 +5,6 @@ #include <stdint.h> -#define SPD_LEN 512 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - uint8_t *mainboard_find_spd_data(void); #endif diff --git a/src/mainboard/intel/kblrvp/board_id.c b/src/mainboard/intel/kblrvp/board_id.c index 4305295d9bcd..23c93350c677 100644 --- a/src/mainboard/intel/kblrvp/board_id.c +++ b/src/mainboard/intel/kblrvp/board_id.c @@ -2,7 +2,6 @@ #include "board_id.h" #include <ec/acpi/ec.h> #include <stdint.h> -#include <stddef.h> /* * Get Board info via EC I/O port write/read diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 56c86115ccd8..156c626b6082 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -4,6 +4,9 @@ #include <gpio.h> #include "gpio.h" #include <soc/romstage.h> +#include <device/dram/ddr3.h> +#include <spd.h> + #include "spd/spd.h" void mainboard_memory_init_params(FSPM_UPD *mupd) @@ -20,5 +23,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); if (mainboard_has_dual_channel_mem()) mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3; } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index c53c6e4379a0..0b4d0e26effc 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -8,19 +8,6 @@ #define MAINBOARD_SPD_H -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 - #define HYNIX_SINGLE_CHAN 0x1 #define SAMSUNG_SINGLE_CHAN 0x4 #define MIC_SINGLE_CHAN 0x5 diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 8c1407adc6da..e79759cced56 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> +#include <spd.h> #include <stdint.h> #include <string.h> + #include "boardid.h" #include "spd.h" @@ -72,16 +75,16 @@ uintptr_t mainboard_get_spd_data(void) die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - spd_span = spd_index * SPD_LEN; + spd_span = spd_index * SPD_SIZE_MAX_DDR3; return (uintptr_t)(spd_file + spd_span); } diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 36842b577a3a..bbff4aa7c564 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -79,7 +79,9 @@ config GBB_HWID config MAINBOARD_PART_NUMBER string - default "mtlrvp" + default "Mtlrvp_P_Ext_Ec" if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP4ES_P_EXT_EC + default "Mtlrvp_P_Mchp" if BOARD_INTEL_MTLRVP_P_MCHP + default "Mtlrvp" if BOARD_INTEL_MTLRVP_P config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP diff --git a/src/mainboard/intel/mtlrvp/Makefile.mk b/src/mainboard/intel/mtlrvp/Makefile.mk index d8144c861458..6c93add77b0e 100644 --- a/src/mainboard/intel/mtlrvp/Makefile.mk +++ b/src/mainboard/intel/mtlrvp/Makefile.mk @@ -8,6 +8,7 @@ romstage-y += romstage.c ramstage-y += ec.c ramstage-y += mainboard.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/mtlrvp/mainboard.c b/src/mainboard/intel/mtlrvp/mainboard.c index 2e515f713773..93cec476f679 100644 --- a/src/mainboard/intel/mtlrvp/mainboard.c +++ b/src/mainboard/intel/mtlrvp/mainboard.c @@ -8,7 +8,7 @@ #include <soc/ramstage.h> #include <smbios.h> #include <stdint.h> -#include <string.h> +#include <stdio.h> const char *smbios_system_sku(void) { diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h index 402c9c17f8ed..44f9b43dcf53 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h @@ -59,6 +59,9 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 17c0014b4bc3..f01479bcaa39 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -42,9 +42,6 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select VBOOT_EARLY_EC_SYNC -config DIMM_SPD_SIZE - default 512 - config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index bbce9278df67..b15f2c14b61d 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -6,7 +6,7 @@ #include <ec/ec.h> #include <soc/gpio.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> const char *smbios_system_sku(void) { |