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-rw-r--r--src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index 30260b0c13ad..cbf1141aec8e 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -57,7 +57,7 @@ chip northbridge/intel/sandybridge
register "xhci_overcurrent_mapping" = "0x4000201"
# Enable zero-based linear PCIe root port functions
- register "pcie_port_coalesce" = "1"
+ register "pcie_port_coalesce" = "true"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"