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-rw-r--r--src/mainboard/lenovo/l520/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/s230u/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t420/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t420s/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t430/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t430s/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t520/variants/t520/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t520/variants/w520/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t530/variants/t530/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/t530/variants/w530/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/x131e/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/x201/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/x220/devicetree.cb1
-rw-r--r--src/mainboard/lenovo/x230/devicetree.cb1
15 files changed, 0 insertions, 15 deletions
diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb
index 48c2ea010e60..024b8f8dd1f0 100644
--- a/src/mainboard/lenovo/l520/devicetree.cb
+++ b/src/mainboard/lenovo/l520/devicetree.cb
@@ -46,7 +46,6 @@ chip northbridge/intel/sandybridge
register "gen4_dec" = "0x00000000"
register "gpi13_routing" = "2"
register "gpi6_routing" = "2"
- register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 1, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb
index a9e8babe6e73..15d323d8b95b 100644
--- a/src/mainboard/lenovo/s230u/devicetree.cb
+++ b/src/mainboard/lenovo/s230u/devicetree.cb
@@ -44,7 +44,6 @@ chip northbridge/intel/sandybridge
register "gen4_dec" = "0x000c06a1"
register "gpi13_routing" = "2"
register "gpi7_routing" = "2"
- register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 1, 0, 1, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb
index c4092fe901ac..6deff6039cdd 100644
--- a/src/mainboard/lenovo/t420/devicetree.cb
+++ b/src/mainboard/lenovo/t420/devicetree.cb
@@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
# device specific SPI configuration
register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index d1e3f754994a..aa6cc6815425 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -68,7 +68,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb
index 2731b69ec0c5..f7e04367c6cd 100644
--- a/src/mainboard/lenovo/t430/devicetree.cb
+++ b/src/mainboard/lenovo/t430/devicetree.cb
@@ -39,7 +39,6 @@ chip northbridge/intel/sandybridge
register "gen3_dec" = "0x000c06a1"
register "gpi13_routing" = "2"
register "gpi1_routing" = "2"
- register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb
index 21d54acf113d..0c2f66889722 100644
--- a/src/mainboard/lenovo/t430s/devicetree.cb
+++ b/src/mainboard/lenovo/t430s/devicetree.cb
@@ -71,7 +71,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "docking_supported" = "1"
register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
index eff2d6930455..7893daf9ec32 100644
--- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb
@@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb
index ceca46ea841f..8716046410ce 100644
--- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/variants/w520/devicetree.cb
@@ -63,7 +63,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb
index 335543a8f79d..190539ac1f80 100644
--- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb
@@ -62,7 +62,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb
index 0a80fa1d8c4d..0844124f0e79 100644
--- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb
@@ -51,7 +51,6 @@ chip northbridge/intel/sandybridge
register "gen1_dec" = "0x007c1601"
register "gen2_dec" = "0x000c15e1"
register "gen4_dec" = "0x000c06a1"
- register "p_cnt_throttling_supported" = "1"
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb
index 21d38f5ab24f..2a98a60cac03 100644
--- a/src/mainboard/lenovo/x131e/devicetree.cb
+++ b/src/mainboard/lenovo/x131e/devicetree.cb
@@ -66,7 +66,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "0x0065"
- register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index 8caa0d1a2fcb..288870f81df7 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -70,7 +70,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
index 6ece08bee64c..bf74d710bbe0 100644
--- a/src/mainboard/lenovo/x201/devicetree.cb
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -68,7 +68,6 @@ chip northbridge/intel/nehalem
register "gen3_dec" = "0x1c1681"
register "gen4_dec" = "0x040069"
- register "p_cnt_throttling_supported" = "1"
register "c2_latency" = "1"
register "docking_supported" = "1"
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 360de049435c..26fa1a4d1f74 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -69,7 +69,6 @@ chip northbridge/intel/sandybridge
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb
index 4687e9ccc3ee..61a5468a7851 100644
--- a/src/mainboard/lenovo/x230/devicetree.cb
+++ b/src/mainboard/lenovo/x230/devicetree.cb
@@ -72,7 +72,6 @@ chip northbridge/intel/sandybridge
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
register "c2_latency" = "101" # c2 not supported
- register "p_cnt_throttling_supported" = "1"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-14 13:07:54 +0000