diff options
Diffstat (limited to 'src/mainboard/lenovo')
-rw-r--r-- | src/mainboard/lenovo/l520/devicetree.cb | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/s230u/devicetree.cb | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/t420/devicetree.cb | 2 | ||||
-rw-r--r-- | src/mainboard/lenovo/t420s/devicetree.cb | 2 | ||||
-rw-r--r-- | src/mainboard/lenovo/t430/devicetree.cb | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/t430s/devicetree.cb | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/t520/devicetree.cb | 2 | ||||
-rw-r--r-- | src/mainboard/lenovo/t530/devicetree.cb | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/x131e/devicetree.cb | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb | 1 | ||||
-rw-r--r-- | src/mainboard/lenovo/x220/devicetree.cb | 2 | ||||
-rw-r--r-- | src/mainboard/lenovo/x230/devicetree.cb | 1 |
12 files changed, 0 insertions, 16 deletions
diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 4655baa81ded..86205f8f8481 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -30,7 +30,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x007c1611" register "gen2_dec" = "0x00040069" diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index fbf54d45fa06..3c1fc9e07383 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -28,7 +28,6 @@ chip northbridge/intel/sandybridge device pci 02.0 on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x00000000" register "gen2_dec" = "0x000c0701" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 3ba3a2d5cae8..e42e519f87b2 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index cfe89295a417..ab98ca0bd0b6 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - # device specific SPI configuration register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 950e83d77a52..112dfe71e79d 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -28,7 +28,6 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21f3 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - register "c2_latency" = "0x0065" register "docking_supported" = "1" register "gen1_dec" = "0x000c15e1" register "gen2_dec" = "0x007c1601" diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 7f95170ba6d3..75a65f900002 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -59,7 +59,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "docking_supported" = "1" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 40b005deb64b..a1e24d525b6a 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index b179f4f54fec..ffa0b93e530c 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -53,7 +53,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index dc9e0372e38e..abe40b19dc44 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -56,7 +56,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "0x0065" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 2707197d38cc..30260b0c13ad 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -58,7 +58,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index a41cfeaebb64..53eb23a1bd51 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index a774d84c14ce..1f813116851e 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -59,7 +59,6 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" |