diff options
Diffstat (limited to 'src/mainboard/lenovo')
44 files changed, 329 insertions, 212 deletions
diff --git a/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c b/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c index 60b21be1e4f3..9d3692fe6086 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c +++ b/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c @@ -12,13 +12,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x0321101f), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738105), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x05350000, 0x0534601a, 0x05450000, 0x05442000, 0x05350003, 0x05341ef8, 0x05450003, 0x05441ef8, diff --git a/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c b/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c index f99c3938c309..f92731ca1eca 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c +++ b/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c @@ -12,13 +12,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x0321101f), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738105), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x05350000, 0x0534601a, 0x05450000, 0x05442000, 0x05350003, 0x05341ef8, 0x05450003, 0x05441ef8, diff --git a/src/mainboard/lenovo/haswell/variants/w541/romstage.c b/src/mainboard/lenovo/haswell/variants/w541/romstage.c index 4a189d42b837..a410f5620179 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/romstage.c +++ b/src/mainboard/lenovo/haswell/variants/w541/romstage.c @@ -4,7 +4,6 @@ #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <option.h> #include <ec/lenovo/pmh7/pmh7.h> #include <device/pci_ops.h> diff --git a/src/mainboard/lenovo/l520/Makefile.mk b/src/mainboard/lenovo/l520/Makefile.mk index e4b6fbf0f0a5..761119433905 100644 --- a/src/mainboard/lenovo/l520/Makefile.mk +++ b/src/mainboard/lenovo/l520/Makefile.mk @@ -4,5 +4,3 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ead7e0bb871f..e398e78e317e 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -12,7 +12,14 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21dd inherit @@ -36,6 +43,23 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 } + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c deleted file mode 100644 index ebcd639e6a2f..000000000000 --- a/src/mainboard/lenovo/l520/early_init.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c index 3d48a8b86b4f..33da0b1ff2bb 100644 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -9,13 +9,13 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0, 0x17aa21de), AZALIA_PIN_CFG(0, 0x12, 0x99a30920), AZALIA_PIN_CFG(0, 0x14, 0x99130110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40079a2d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0321101f), 0x80862805, /* Codec Vendor / Device ID: Intel */ diff --git a/src/mainboard/lenovo/m900_tiny/devicetree.cb b/src/mainboard/lenovo/m900_tiny/devicetree.cb index e9f15d6c7134..e6655b536aab 100644 --- a/src/mainboard/lenovo/m900_tiny/devicetree.cb +++ b/src/mainboard/lenovo/m900_tiny/devicetree.cb @@ -117,7 +117,6 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - device cpu_cluster 0 on end device domain 0 on subsystemid 0x17aa 0x30d0 inherit device ref igpu on diff --git a/src/mainboard/lenovo/m900_tiny/hda_verb.c b/src/mainboard/lenovo/m900_tiny/hda_verb.c index b545df48cf5a..6c1f5456c2d1 100644 --- a/src/mainboard/lenovo/m900_tiny/hda_verb.c +++ b/src/mainboard/lenovo/m900_tiny/hda_verb.c @@ -9,13 +9,13 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(1, 0x17aa30d0), AZALIA_PIN_CFG(1, 0x12, 0x40000000), AZALIA_PIN_CFG(1, 0x14, 0x90170110), - AZALIA_PIN_CFG(1, 0x17, 0x411111f0), - AZALIA_PIN_CFG(1, 0x18, 0x411111f0), + AZALIA_PIN_CFG(1, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(1, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x19, 0x02a11030), AZALIA_PIN_CFG(1, 0x1a, 0x02a11040), AZALIA_PIN_CFG(1, 0x1b, 0x01011020), AZALIA_PIN_CFG(1, 0x1d, 0x40400001), - AZALIA_PIN_CFG(1, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x21, 0x0221101f), 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 47add6f39a90..6e66f3a7cc79 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -5,7 +5,6 @@ #include <drivers/intel/gma/int15.h> #include <gpio.h> #include <mainboard/gpio.h> -#include <soc/gpio.h> #include <soc/ramstage.h> static void print_board_id(void) diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index eae969633678..eb832bed74bc 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -34,6 +34,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 0, 1 }, + { 1, 1, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 1, 3 }, + { 1, 0, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 1, 6 } + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 58e95932b80d..f4396cb617e2 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -20,23 +20,6 @@ void mainboard_pch_lpc_setup(void) ec_mm_set_bit(0x3b, 4); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 0, 1 }, - { 1, 1, 2 }, - { 1, 0, 2 }, - { 0, 0, 3 }, - { 0, 1, 3 }, - { 1, 0, 4 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, -}; - static const char *mainboard_spd_names[9] = { "ELPIDA 4GB", "SAMSUNG 4GB", diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c index ab28cf9506ea..1d0586318530 100644 --- a/src/mainboard/lenovo/s230u/hda_verb.c +++ b/src/mainboard/lenovo/s230u/hda_verb.c @@ -56,25 +56,25 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x03211020), /* Unknown: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* MIC1 in: Location left, mic in, 1/8" jack, black */ AZALIA_PIN_CFG(0, 0x18, 0x03a11830), /* MIC2 in: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), /* Line1 in: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Line2 in: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* PCBEEP */ AZALIA_PIN_CFG(0, 0x1d, 0x40148605), /* S/PDIF out: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x01470740, /* Enable output for NID 0x14 (Speaker out) */ 0x015707C0, /* Enable output & HP amp for NID 0x15 (HP out) */ diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c index b5e3b8786d5b..f51ec6705fa9 100644 --- a/src/mainboard/lenovo/s230u/mainboard.c +++ b/src/mainboard/lenovo/s230u/mainboard.c @@ -5,6 +5,7 @@ #include <drivers/intel/gma/int15.h> #include <ec/acpi/ec.h> #include <southbridge/intel/common/gpio.h> +#include <stdio.h> #include <string.h> #include <smbios.h> #include "ec.h" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index d4b31afe88b7..6b721f3f74d5 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21ce inherit @@ -51,6 +58,24 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + # OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 + register "usb_port_config" = "{ + {1, 1, 0}, /* P0: system port 4, OC0 */ + {1, 1, 1}, /* P1: system port 2 (EHCI debug), OC 1 */ + {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */ + {1, 0, -1}, /* P3: WWAN, no OC */ + {1, 0, -1}, /* P4: smartcard, no OC */ + {1, 1, -1}, /* P5: ExpressCard, no OC */ + {0, 0, -1}, /* P6: empty */ + {0, 0, -1}, /* P7: empty */ + {1, 1, 4}, /* P8: system port 3, OC4*/ + {1, 1, 5}, /* P9: system port 1 (EHCI debug), OC 5 */ + {1, 0, -1}, /* P10: fingerprint reader, no OC */ + {1, 0, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: docking, no OC */ + {1, 1, -1} /* P13: camera (LCD), no OC */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index c90221ed67cd..79e3cf7f5ac0 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -31,24 +31,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index fb309170fe75..b35888506958 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21d2 inherit @@ -53,6 +60,23 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {0, 1, -1}, /* P0: empty */ + {1, 1, 1}, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */ + {1, 0, -1}, /* P3: WWAN, no OC */ + {1, 1, -1}, /* P4: smartcard, no OC */ + {1, 1, -1}, /* P5: ExpressCard, no OC */ + {0, 0, -1}, /* P6: empty */ + {0, 0, -1}, /* P7: empty */ + {0, 1, -1}, /* P8: empty (touch panel) */ + {1, 0, 5}, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + {1, 0, -1}, /* P10: fingerprint reader, no OC */ + {1, 1, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: docking, no OC */ + {1, 1, -1} /* P13: camera (LCD), no OC */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index e5e95b218a11..79e3cf7f5ac0 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -31,23 +31,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 649254290619..f0f7975117c4 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -35,6 +35,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x7" register "xhci_switchable_ports" = "0x7" register "xhci_overcurrent_mapping" = "0x04000201" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 2, 3 }, + { 1, 1, -1 }, + { 1, 1, 2 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 1, 2, -1 }, + { 1, 0, -1 }, + { 1, 1, 5 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 3, -1 }, + { 1, 1, -1 } + }" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 5e397ab7c433..86fcda8b37f0 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -33,24 +33,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -/* FIXME: used T530 values here */ -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 2, 3 }, - { 1, 1, -1 }, - { 1, 1, 2 }, - { 1, 0, -1 }, - { 0, 0, -1 }, - { 1, 2, -1 }, - { 1, 0, -1 }, - { 1, 1, 5 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 3, -1 }, - { 1, 1, -1 }, -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c index ea0f13f6df06..6ece6954fded 100644 --- a/src/mainboard/lenovo/t430/hda_verb.c +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -10,13 +10,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c index 8a663286f9a8..b891e854834c 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c @@ -31,19 +31,19 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), 0x01970804, 0x01870803, 0x01470740, 0x00970600, - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Misc entries */ 0x00370600, diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index 5677a8729a85..a9da73081511 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -2,6 +2,22 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P0:, OC 0 */ + { 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */ + { 1, 1, 3 }, /* P2: OC 3 */ + { 1, 0, -1 }, /* P3: no OC */ + { 1, 2, -1 }, /* P4: no OC */ + { 1, 1, -1 }, /* P5: no OC */ + { 1, 1, -1 }, /* P6: no OC */ + { 0, 1, -1 }, /* P7: empty, no OC */ + { 1, 1, -1 }, /* P8: smart card reader, no OC */ + { 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 0, 0, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" # Enable hotplug on Port 5 for Thunderbolt controller register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" device ref pcie_rp5 on end # Thunderbolt controller diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c index ec7683ab1d1a..e801e9ce4675 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x17, 0x40008000), AZALIA_PIN_CFG(0, 0x18, 0x03a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f38205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e839358ddf23..15712f941d85 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -23,6 +23,23 @@ chip northbridge/intel/sandybridge # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* SSP1: right */ + { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ + { 1, 1, 3 }, /* SSP3: dock USB3 */ + { 1, 1, -1 }, /* B0P4: wwan USB */ + { 1, 1, 2 }, /* B0P5: dock USB2 */ + { 0, 0, -1 }, /* B0P6 */ + { 0, 0, -1 }, /* B0P7 */ + { 1, 2, -1 }, /* B0P8: unknown */ + { 1, 0, -1 }, /* B1P1: smart card reader */ + { 0, 2, 5 }, /* B1P2 */ + { 1, 1, -1 }, /* B1P3: fingerprint reader */ + { 0, 0, -1 }, /* B1P4 */ + { 1, 1, -1 }, /* B1P5: wlan USB */ + { 1, 1, -1 }, /* B1P6: Camera */ + }" + device ref pcie_rp1 on chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a2e12c34d7f8..5edb63e95d35 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,6 +15,14 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 05d62213cf51..564aff2d778f 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -34,16 +34,16 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), 0x01970804, 0x01870803, 0x01470740, 0x00970600, - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Misc entries */ 0x00370600, diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb index b574f367db56..3f058e385456 100644 --- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -2,6 +2,22 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ + { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ + { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ + { 1, 1, -1 }, /* P3: WWAN slot, no OC */ + { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ + { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 1, 2, -1 }, /* P7: docking, no OC */ + { 1, 0, -1 }, /* P8: smart card reader, no OC */ + { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb index 6b8638772649..a54db1efe2a4 100644 --- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -5,6 +5,22 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21f5 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ + { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ + { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ + { 1, 1, -1 }, /* P3: WWAN slot, no OC */ + { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ + { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ + { 1, 0, -1 }, /* P6: color sensor, no OC */ + { 1, 2, -1 }, /* P7: docking, no OC */ + { 1, 0, -1 }, /* P8: smart card reader, no OC */ + { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" device ref me_kt on end device ref pcie_rp1 on chip drivers/ricoh/rce822 # Ricoh cardreader diff --git a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c index c1cf92baa400..594b9d7ea9a9 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c +++ b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c @@ -13,14 +13,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x99130120), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19830), AZALIA_PIN_CFG(0, 0x19, 0x02a19831), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb index aa1f9b2a6dad..f4f51b76ee9c 100644 --- a/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_m710s/devicetree.cb @@ -3,7 +3,6 @@ chip soc/intel/skylake register "eist_enable" = "true" - device cpu_cluster 0 on end device domain 0 on device ref peg0 on # PCIE16X # These configurations are technically for PCIe root diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 96385ed2cdf3..b74e78f6c09e 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -43,6 +43,18 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x00000c03" + register "usb_port_config" = "{ + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, + {1, 0, -1} /* P13: Bluetooth (no OC) */ + }" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index a4232460519b..4abc9c0cd16f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -43,6 +43,22 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" + register "usb_port_config" = "{ + {0, 3, 0 }, /* P00 disconnected */ + {1, 1, 1 }, /* P01 left or right */ + {0, 1, 3 }, /* P02 disconnected */ + {1, 3, -1}, /* P03 WWAN */ + {0, 1, 2 }, /* P04 disconnected */ + {0, 1, -1}, /* P05 disconnected */ + {0, 1, -1}, /* P06 disconnected */ + {0, 2, -1}, /* P07 disconnected */ + {0, 1, -1}, /* P08 disconnected */ + {1, 2, 5 }, /* P09 left or right */ + {1, 3, -1}, /* P10 FPR */ + {1, 3, -1}, /* P11 Bluetooth */ + {1, 1, -1}, /* P12 WLAN */ + {1, 1, -1} /* P13 Camera */ + }" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c index 288d673bdf5f..069d483411d9 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c @@ -10,13 +10,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk index b104bb52a98b..7e597079158a 100644 --- a/src/mainboard/lenovo/x220/Makefile.mk +++ b/src/mainboard/lenovo/x220/Makefile.mk @@ -2,7 +2,6 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index dc2f4a58586b..aaeecc824653 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -19,22 +19,6 @@ chip northbridge/intel/sandybridge register "ec_present" = "1" # I have an embedded controller register "max_mem_clock_mhz" = "666" # So DDR3 freq = 1333 - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 2, 0x0040 }, - { 1, 2, 0x0040 }, - { 1, 6, 0x0080 }, - { 1, 5, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 7, 0x0080 }, - { 1, 6, 0x0080 },}" - chip cpu/intel/model_206ax # Values obtained from vendor BIOS v1.46 # schematics say 33Amps for 17W TDP, 53Amps for 35W TDP diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index bf8815004422..cb1d12535954 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -16,6 +16,22 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21e8 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 3 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 0, 7 }, + { 1, 1, 7 }, + { 1, 1, 7 }, + { 1, 0, 7 } + }" # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap) register "sata_port_map" = "0x1d" # X1 does not have ExpressCard slot diff --git a/src/mainboard/lenovo/x220/variants/x1/romstage.c b/src/mainboard/lenovo/x220/variants/x1/romstage.c deleted file mode 100644 index 593b7b2008d3..000000000000 --- a/src/mainboard/lenovo/x220/variants/x1/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 3 }, - { 0, 0, 3 }, - { 0, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 0, 7 }, - { 1, 1, 7 }, - { 1, 1, 7 }, - { 1, 0, 7 }, -}; diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index b9caa255de7c..626f7eb3a677 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,6 +1,23 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + {1, 0, 0 }, + {1, 1, 1 }, + {1, 1, 3 }, + {1, 1, 3 }, + {1, 1, -1}, + {1, 1, -1}, + {1, 0, 2 }, + {1, 0, 2 }, + {1, 1, 6 }, + {1, 1, 5 }, + {1, 1, 6 }, + {1, 1, 6 }, + {1, 1, 7 }, + {1, 1, 6 }, + }" + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy diff --git a/src/mainboard/lenovo/x220/variants/x220/romstage.c b/src/mainboard/lenovo/x220/variants/x220/romstage.c deleted file mode 100644 index bd33cef65f3d..000000000000 --- a/src/mainboard/lenovo/x220/variants/x220/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 1, 3 }, - { 1, 1, -1 }, - { 1, 1, -1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 1, 6 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, - { 1, 1, 7 }, - { 1, 1, 6 }, -}; diff --git a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c index 05fb3fd775e7..153d08e3d8d2 100644 --- a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c @@ -35,10 +35,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Misc entries */ 0x01970804, diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index d82faae94fd8..e7b06b6b2b42 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -3,6 +3,22 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "usb_port_config" = "{ + {1, 0, 0 }, /* P0 (left, fan side), OC 0 */ + {1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ + {1, 1, 3 }, /* P2: dock, OC 3 */ + {1, 1, -1}, /* P3: wwan, no OC */ + {1, 1, -1}, /* P4: Wacom tablet on X230t, otherwise empty */ + {1, 1, -1}, /* P5: Expresscard, no OC */ + {0, 0, -1}, /* P6: Empty */ + {1, 2, -1}, /* P7: dock, no OC */ + {0, 0, -1}, /* P8: Empty */ + {1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ + {1, 1, -1}, /* P10: fingerprint reader, no OC */ + {1, 1, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: wlan, no OC */ + {1, 1, -1}, /* P13: webcam, no OC */ + }" device ref pcie_rp3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end diff --git a/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c index 77919041e55b..bbc93d29ac22 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c +++ b/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x17, 0x40008000), AZALIA_PIN_CFG(0, 0x18, 0x03a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f38205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 09e7f9289c8c..a84b5f3bdd15 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -18,7 +18,22 @@ chip northbridge/intel/sandybridge # X230s does not support docking # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) register "sata_port_map" = "0x3" - + register "usb_port_config" = "{ + {1, 3, 0}, /* SSP1: Right */ + {1, 3, 1}, /* SSP2: Left, EHCI Debug */ + {0, 1, 3}, /* SSP3 */ + {1, 3, -1}, /* B0P4: WWAN USB */ + {0, 1, 2}, /* B0P5 */ + {0, 1, -1}, /* B0P6 */ + {0, 1, -1}, /* B0P7 */ + {0, 1, -1}, /* B0P8 */ + {0, 1, -1}, /* B1P1 */ + {0, 1, 5}, /* B1P2 */ + {1, 1, -1}, /* B1P3: Fingerprint Reader */ + {0, 1, -1}, /* B1P4 */ + {1, 3, -1}, /* B1P5: WLAN USB */ + {1, 1, -1}, /* B1P6: Camera */ + }" device ref lpc on chip ec/lenovo/h8 register "config1" = "0x05" |