diff options
Diffstat (limited to 'src/mainboard')
727 files changed, 13538 insertions, 2662 deletions
diff --git a/src/mainboard/acer/g43t-am3/hda_verb.c b/src/mainboard/acer/g43t-am3/hda_verb.c index c01bf3f6808c..a47fe0386528 100644 --- a/src/mainboard/acer/g43t-am3/hda_verb.c +++ b/src/mainboard/acer/g43t-am3/hda_verb.c @@ -11,19 +11,19 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x11, 0x014b7140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), AZALIA_PIN_CFG(0, 0x17, 0x01012014), AZALIA_PIN_CFG(0, 0x18, 0x01a19850), AZALIA_PIN_CFG(0, 0x19, 0x02a19851), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), AZALIA_PIN_CFG(0, 0x1c, 0x0181305f), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1e, 0x18567130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* HDMI */ 0x80862803, diff --git a/src/mainboard/adlink/CM2-GF/board_info.txt b/src/mainboard/adlink/CM2-GF/board_info.txt deleted file mode 100644 index 4244bfc70c80..000000000000 --- a/src/mainboard/adlink/CM2-GF/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Category: half -Board name: CoreModule2-GF -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Clone of: lippert/frontrunner-af diff --git a/src/mainboard/adlink/Kconfig b/src/mainboard/adlink/Kconfig deleted file mode 100644 index 2ff99b3ef857..000000000000 --- a/src/mainboard/adlink/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -if VENDOR_ADLINK - -comment "see under vendor LiPPERT" -# any further boards will then be ADLINK - -config MAINBOARD_VENDOR - default "ADLINK" - -endif # VENDOR_ADLINK diff --git a/src/mainboard/adlink/cExpress-GFR/board_info.txt b/src/mainboard/adlink/cExpress-GFR/board_info.txt deleted file mode 100644 index 7f883dbb2cb1..000000000000 --- a/src/mainboard/adlink/cExpress-GFR/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Category: half -Board name: cExpress-GFR -Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 -ROM package: SOIC8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y -Clone of: lippert/toucan-af diff --git a/src/mainboard/amd/bilby/Kconfig b/src/mainboard/amd/bilby/Kconfig index 19fcbe5e9fd7..95732046b0a7 100644 --- a/src/mainboard/amd/bilby/Kconfig +++ b/src/mainboard/amd/bilby/Kconfig @@ -80,18 +80,6 @@ config BILBY_LPC Picasso's LPC bus signals are MUXed with some of the EMMC signals. Select this option if LPC signals are required. -#TODO: remove this hack to not break graphics in combination with SeaBIOS -config VGA_BIOS_DGPU_ID - string - default "1002,15d8" - help - The default VGA BIOS PCI vendor/device ID should be set to the - result of the map_oprom_vendev() function in northbridge.c. - -config VGA_BIOS_DGPU_FILE - string - default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" - if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 3 # Quad IO (1-1-4) diff --git a/src/mainboard/amd/bilby/hda_verb.c b/src/mainboard/amd/bilby/hda_verb.c index 0f61f3152554..b5c65e809808 100644 --- a/src/mainboard/amd/bilby/hda_verb.c +++ b/src/mainboard/amd/bilby/hda_verb.c @@ -14,18 +14,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), // Pin widget 0x12 - DMIC AZALIA_PIN_CFG(0, 0x13, 0x40000000), // Pin widget 0x13 - DMIC AZALIA_PIN_CFG(0, 0x14, 0x90170110), // Pin widget 0x14 - FRONT (Port-D) - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), // Pin widget 0x15 - I2S-OUT - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // Pin widget 0x16 - LINE3 (Port-B) - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // Pin widget 0x17 - I2S-OUT - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), // Pin widget 0x18 - I2S-IN - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // Pin widget 0x19 - MIC2 (Port-F) - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // Pin widget 0x1A - LINE1 (Port-C) + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x15 - I2S-OUT + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x16 - LINE3 (Port-B) + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x17 - I2S-OUT + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x18 - I2S-IN + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x19 - MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1A - LINE1 (Port-C) AZALIA_PIN_CFG(0, 0x1b, 0x04a11050), // Pin widget 0x1B - LINE2 (Port-E) AZALIA_PIN_CFG(0, 0x1d, 0x40600001), // Pin widget 0x1D - PC-BEEP AZALIA_PIN_CFG(0, 0x1e, 0x04451130), // Pin widget 0x1E - S/PDIF-OUT - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), // Pin widget 0x1F - S/PDIF-IN + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1F - S/PDIF-IN AZALIA_PIN_CFG(0, 0x21, 0x04211020), // Pin widget 0x21 - HP-OUT (Port-I) - AZALIA_PIN_CFG(0, 0x29, 0x411111f0), // Pin widget 0x29 - I2S-IN + AZALIA_PIN_CFG(0, 0x29, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x29 - I2S-IN 0x02050038, 0x02047901, 0x0205006b, 0x02040260, // NID 0x20 -0 Set Class-D output // power as 2.2W@4 Ohm, and // MIC2-VREFO-R is controlled by @@ -46,14 +46,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), // Pin widget 0x12 - DMIC AZALIA_PIN_CFG(0, 0x13, 0x40000000), // Pin widget 0x13 - DMIC AZALIA_PIN_CFG(0, 0x14, 0x90170110), // Pin widget 0x14 - Front (Port-D) - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // Pin widget 0x16 - NPC - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // Pin widget 0x17 - I2S OUT - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), // Pin widget 0x18 - I2S IN - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // Pin widget 0x19 - MIC2 (Port-F) - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // Pin widget 0x1A - NPC + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x16 - NPC + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x17 - I2S OUT + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x18 - I2S IN + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x19 - MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1A - NPC AZALIA_PIN_CFG(0, 0x1b, 0x04a19030), // Pin widget 0x1B - LINE2 (Port-E) AZALIA_PIN_CFG(0, 0x1d, 0x4066192d), // Pin widget 0x1D - BEEP-IN - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), // Pin widget 0x1E - S/PDIF-OUT + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1E - S/PDIF-OUT AZALIA_PIN_CFG(0, 0x21, 0x04211020), // Pin widget 0x21 - HP1-OUT (Port-I) 0x05c50011, 0x05c40003, 0x05c50011, 0x05c40003, // dis. Silence detect delay turn off 0x0205003c, 0x0204f254, 0x0205003c, 0x0204f214, // Class-D power on reset diff --git a/src/mainboard/amd/birman/Makefile.mk b/src/mainboard/amd/birman/Makefile.mk index 6c417ce54c03..a784d1a7fa4b 100644 --- a/src/mainboard/amd/birman/Makefile.mk +++ b/src/mainboard/amd/birman/Makefile.mk @@ -4,11 +4,14 @@ bootblock-y += bootblock.c bootblock-y += early_gpio.c bootblock-y += ec.c +romstage-y += display_card_type.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c ramstage-y += chromeos.c +ramstage-y += display_card_type.c ramstage-y += gpio.c +ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL) += update_devicetree_phoenix_opensil.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index 58cead583e93..58c022ec0e40 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -39,29 +39,244 @@ chip soc/amd/phoenix register "s0ix_enable" = "true" - register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works< + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + + register "usb_phy_custom" = "1" + register "usb_phy" = "{ + .Usb2PhyPort[0] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[1] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[2] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[3] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[4] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[5] = { + .compdistune = 0x1, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x3, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[6] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x6, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb2PhyPort[7] = { + .compdistune = 0x3, + .pllbtune = 0x1, + .pllitune = 0x0, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, + .txpreemppulsetune = 0x0, + .txrisetune = 0x1, + .txvreftune = 0x6, + .txhsxvtune = 0x3, + .txrestune = 0x2, + }, + .Usb3PhyPort[0] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[1] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .Usb3PhyPort[2] = { + .tx_term_ctrl = 0x2, + .rx_term_ctrl = 0x2, + .tx_vboost_lvl_en = 0x0, + .tx_vboost_lvl = 0x5, + }, + .ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C, + .ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C, + .BatteryChargerEnable = 0, + .PhyP3CpmP4Support = 0, + }" + + register "ddi[0]" = "{ + .connector_type = DDI_EDP, + .aux_index = 0, + .hdp_index = 0, + }" + register "ddi[1]" = "{ + .connector_type = DDI_HDMI, + .aux_index = 1, + .hdp_index = 1, + }" + register "ddi[2]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 2, + .hdp_index = 2, + }" + register "ddi[3]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 3, + .hdp_index = 3, + }" + register "ddi[4]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 4, + .hdp_index = 4, + }" device domain 0 on device ref iommu on end - device ref gpp_bridge_1_1 on end # MXM - device ref gpp_bridge_1_2 on - # Required so the NVMe gets placed into D3 when entering S0i3. - chip drivers/pcie/rtd3/device - register "name" = ""NVME"" - device pci 00.0 on end + chip vendorcode/amd/opensil/chip/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "0" + register "end_lane" = "7" + register "aspm" = "ASPM_L1" + register "clk_req" = "CLK_REQ0" + # register "gpio_group" is currently not used + device ref gpp_bridge_1_1 on end # MXM + end + chip vendorcode/amd/opensil/chip/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "8" + register "end_lane" = "11" + register "aspm" = "ASPM_L1" + register "clk_req" = "CLK_REQ1" + device ref gpp_bridge_1_2 on # NVMe SSD1 + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end end - end # NVMe SSD1 - device ref gpp_bridge_1_3 on end # GBE - device ref gpp_bridge_2_1 on end # SD - device ref gpp_bridge_2_2 on end # WWAN - device ref gpp_bridge_2_3 on end # WIFI - device ref gpp_bridge_2_4 on - # Required so the NVMe gets placed into D3 when entering S0i3. - chip drivers/pcie/rtd3/device - register "name" = ""NVME"" - device pci 00.0 on end + end + chip vendorcode/amd/opensil/chip/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "12" + register "end_lane" = "12" + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ6" + device ref gpp_bridge_1_3 on end # GBE + end + chip vendorcode/amd/opensil/chip/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "13" + register "end_lane" = "13" + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ5" + device ref gpp_bridge_2_1 on end # SD + end + chip vendorcode/amd/opensil/chip/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "14" + register "end_lane" = "14" + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ4" + device ref gpp_bridge_2_2 on end # WWAN + end + chip vendorcode/amd/opensil/chip/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "15" + register "end_lane" = "15" + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ3" + device ref gpp_bridge_2_3 on end # WIFI + end + chip vendorcode/amd/opensil/chip/mpio + register "type" = "IFTYPE_PCIE" + register "start_lane" = "16" + register "end_lane" = "19" + register "aspm" = "ASPM_DISABLED" + register "clk_req" = "CLK_REQ2" + device ref gpp_bridge_2_4 on # NVMe SSD0 + # Required so the NVMe gets placed into D3 when entering S0i3. + chip drivers/pcie/rtd3/device + register "name" = ""NVME"" + device pci 00.0 on end + end end - end # NVMe SSD0 + end device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gfx on end # Internal GPU (GFX) device ref gfx_hda on end # Display HD Audio Controller (GFXAZ) diff --git a/src/mainboard/amd/birman/display_card_type.c b/src/mainboard/amd/birman/display_card_type.c new file mode 100644 index 000000000000..21f536ff4cfa --- /dev/null +++ b/src/mainboard/amd/birman/display_card_type.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/i2c_simple.h> +#if CONFIG(PLATFORM_USES_FSP2_0) +#include <soc/platform_descriptors.h> +#else +#include <soc/amd/phoenix/chip_opensil.h> +#endif +#include <types.h> +#include "display_card_type.h" + +uint8_t get_ddi1_type(void) +{ + const uint8_t eeprom_i2c_bus = 2; + const uint8_t eeprom_i2c_address = 0x55; + const uint16_t eeprom_connector_type_offset = 2; + uint8_t eeprom_connector_type_data[2]; + uint16_t connector_type; + + if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, + eeprom_connector_type_offset, eeprom_connector_type_data, + sizeof(eeprom_connector_type_data))) { + printk(BIOS_NOTICE, + "Display connector type couldn't be determined. Disabling DDI1.\n"); + return DDI_UNUSED_TYPE; + } + + connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; + + switch (connector_type) { + case 0x0c: + printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); + return DDI_HDMI; + case 0x13: + printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); + return DDI_DP; + case 0x14: + printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); + return DDI_EDP; + case 0x17: + printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); + return DDI_DP_W_TYPEC; + default: + printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", + connector_type); + return DDI_UNUSED_TYPE; + } +} diff --git a/src/mainboard/amd/birman/display_card_type.h b/src/mainboard/amd/birman/display_card_type.h new file mode 100644 index 000000000000..1ffb278dabd6 --- /dev/null +++ b/src/mainboard/amd/birman/display_card_type.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_DISPLAY_CARD_TYPE_H +#define MAINBOARD_DISPLAY_CARD_TYPE_H + +#include <types.h> + +uint8_t get_ddi1_type(void); + +#endif /* MAINBOARD_DISPLAY_CARD_TYPE_H */ diff --git a/src/mainboard/amd/birman/mainboard.c b/src/mainboard/amd/birman/mainboard.c index 0deba6710f44..f2d3ef9e5337 100644 --- a/src/mainboard/amd/birman/mainboard.c +++ b/src/mainboard/amd/birman/mainboard.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <types.h> #include "gpio.h" +#include "update_devicetree.h" /* TODO: Update for birman */ @@ -58,6 +59,9 @@ const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) static void mainboard_init(void *chip_info) { mainboard_program_gpios(); + + if (CONFIG(BOARD_AMD_BIRMAN_PHOENIX_OPENSIL)) + mainboard_update_devicetree_opensil(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/birman/port_descriptors_glinda.c b/src/mainboard/amd/birman/port_descriptors_glinda.c index a0dbd17b3487..2af7d26de343 100644 --- a/src/mainboard/amd/birman/port_descriptors_glinda.c +++ b/src/mainboard/amd/birman/port_descriptors_glinda.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <device/i2c_simple.h> #include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> +#include "display_card_type.h" /* TODO: Update for birman */ @@ -79,44 +78,6 @@ static fsp_ddi_descriptor birman_ddi_descriptors[] = { } }; -static uint8_t get_ddi1_type(void) -{ - const uint8_t eeprom_i2c_bus = 2; - const uint8_t eeprom_i2c_address = 0x55; - const uint16_t eeprom_connector_type_offset = 2; - uint8_t eeprom_connector_type_data[2]; - uint16_t connector_type; - - if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, - eeprom_connector_type_offset, eeprom_connector_type_data, - sizeof(eeprom_connector_type_data))) { - printk(BIOS_NOTICE, - "Display connector type couldn't be determined. Disabling DDI1.\n"); - return DDI_UNUSED_TYPE; - } - - connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; - - switch (connector_type) { - case 0x0c: - printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); - return DDI_HDMI; - case 0x13: - printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); - return DDI_DP; - case 0x14: - printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); - return DDI_EDP; - case 0x17: - printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); - return DDI_DP_W_TYPEC; - default: - printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", - connector_type); - return DDI_UNUSED_TYPE; - } -} - void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) diff --git a/src/mainboard/amd/birman/port_descriptors_phoenix.c b/src/mainboard/amd/birman/port_descriptors_phoenix.c index 8ab7417d2a91..da07e312f2f7 100644 --- a/src/mainboard/amd/birman/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman/port_descriptors_phoenix.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <device/i2c_simple.h> #include <gpio.h> #include <soc/platform_descriptors.h> #include <soc/soc_util.h> #include <types.h> +#include "display_card_type.h" #define phx_mxm_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ @@ -163,44 +163,6 @@ static fsp_ddi_descriptor birman_ddi_descriptors[] = { } }; -static uint8_t get_ddi1_type(void) -{ - const uint8_t eeprom_i2c_bus = 2; - const uint8_t eeprom_i2c_address = 0x55; - const uint16_t eeprom_connector_type_offset = 2; - uint8_t eeprom_connector_type_data[2]; - uint16_t connector_type; - - if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, - eeprom_connector_type_offset, eeprom_connector_type_data, - sizeof(eeprom_connector_type_data))) { - printk(BIOS_NOTICE, - "Display connector type couldn't be determined. Disabling DDI1.\n"); - return DDI_UNUSED_TYPE; - } - - connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; - - switch (connector_type) { - case 0x0c: - printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); - return DDI_HDMI; - case 0x13: - printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); - return DDI_DP; - case 0x14: - printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); - return DDI_EDP; - case 0x17: - printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); - return DDI_DP_W_TYPEC; - default: - printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", - connector_type); - return DDI_UNUSED_TYPE; - } -} - void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) diff --git a/src/mainboard/amd/birman/update_devicetree.h b/src/mainboard/amd/birman/update_devicetree.h new file mode 100644 index 000000000000..6f98dbd0ef46 --- /dev/null +++ b/src/mainboard/amd/birman/update_devicetree.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_UPDATE_DEVICETREE_H +#define MAINBOARD_UPDATE_DEVICETREE_H + +void mainboard_update_devicetree_opensil(void); + +#endif /* MAINBOARD_UPDATE_DEVICETREE_H */ diff --git a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c new file mode 100644 index 000000000000..f0060b8a63f2 --- /dev/null +++ b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/amd/phoenix/chip.h> +#include <soc/soc_util.h> +#include <vendorcode/amd/opensil/chip/mpio/chip.h> +#include "display_card_type.h" +#include "update_devicetree.h" + +static void mainboard_update_mpio(void) +{ + struct device *mxm_bridge = DEV_PTR(gpp_bridge_1_1); + struct device *ssd1_bridge = DEV_PTR(gpp_bridge_1_2); + struct device *wwan_bridge = DEV_PTR(gpp_bridge_2_2); + struct device *wlan_bridge = DEV_PTR(gpp_bridge_2_3); + struct vendorcode_amd_opensil_chip_mpio_config *mxm_bridge_cfg = config_of(mxm_bridge); + struct vendorcode_amd_opensil_chip_mpio_config *ssd1_bridge_cfg = config_of(ssd1_bridge); + struct vendorcode_amd_opensil_chip_mpio_config *wwan_bridge_cfg = config_of(wwan_bridge); + struct vendorcode_amd_opensil_chip_mpio_config *wlan_bridge_cfg = config_of(wlan_bridge); + + /* Phoenix 2 has less PCIe lanes than Phoenix */ + if (get_soc_type() == SOC_PHOENIX2) { + mxm_bridge_cfg->end_lane = 3; + ssd1_bridge_cfg->end_lane = 9; + } + if (!CONFIG(ENABLE_EVAL_CARD)) { + mxm_bridge->enabled = false; + } + if (CONFIG(DISABLE_DT_M2)) { + ssd1_bridge->enabled = false; + } + /* When the WLAN card uses 2 lanes, the WWAN card can't be used */ + if (CONFIG(WLAN01)) { + wwan_bridge->enabled = false; + wlan_bridge_cfg->end_lane = 14; + } + /* When the WWAN card uses 2 lanes, the WLAN card can't be used */ + if (CONFIG(WWAN01)) { + wlan_bridge->enabled = false; + wwan_bridge_cfg->end_lane = 15; + } +} + +static void mainboard_update_ddi(void) +{ + struct soc_amd_phoenix_config *cfg = config_of_soc(); + cfg->ddi[1].connector_type = get_ddi1_type(); +} + +void mainboard_update_devicetree_opensil(void) +{ + mainboard_update_mpio(); + mainboard_update_ddi(); +} diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 252404bb5376..ce3af3ba74c4 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -106,19 +106,6 @@ config MANDOLIN_LPC Picasso's LPC bus signals are MUXed with some of the EMMC signals. Select this option if LPC signals are required. -#TODO: remove this hack to not break graphics in combination with SeaBIOS -config VGA_BIOS_DGPU_ID - string - default "1002,15d8" - help - The default VGA BIOS PCI vendor/device ID should be set to the - result of the map_oprom_vendev() function in northbridge.c. - -config VGA_BIOS_DGPU_FILE - string - default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN - default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME - if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 3 # Quad IO (1-1-4) diff --git a/src/mainboard/amd/mandolin/hda_verb.c b/src/mainboard/amd/mandolin/hda_verb.c index 0f61f3152554..b5c65e809808 100644 --- a/src/mainboard/amd/mandolin/hda_verb.c +++ b/src/mainboard/amd/mandolin/hda_verb.c @@ -14,18 +14,18 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), // Pin widget 0x12 - DMIC AZALIA_PIN_CFG(0, 0x13, 0x40000000), // Pin widget 0x13 - DMIC AZALIA_PIN_CFG(0, 0x14, 0x90170110), // Pin widget 0x14 - FRONT (Port-D) - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), // Pin widget 0x15 - I2S-OUT - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // Pin widget 0x16 - LINE3 (Port-B) - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // Pin widget 0x17 - I2S-OUT - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), // Pin widget 0x18 - I2S-IN - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // Pin widget 0x19 - MIC2 (Port-F) - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // Pin widget 0x1A - LINE1 (Port-C) + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x15 - I2S-OUT + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x16 - LINE3 (Port-B) + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x17 - I2S-OUT + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x18 - I2S-IN + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x19 - MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1A - LINE1 (Port-C) AZALIA_PIN_CFG(0, 0x1b, 0x04a11050), // Pin widget 0x1B - LINE2 (Port-E) AZALIA_PIN_CFG(0, 0x1d, 0x40600001), // Pin widget 0x1D - PC-BEEP AZALIA_PIN_CFG(0, 0x1e, 0x04451130), // Pin widget 0x1E - S/PDIF-OUT - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), // Pin widget 0x1F - S/PDIF-IN + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1F - S/PDIF-IN AZALIA_PIN_CFG(0, 0x21, 0x04211020), // Pin widget 0x21 - HP-OUT (Port-I) - AZALIA_PIN_CFG(0, 0x29, 0x411111f0), // Pin widget 0x29 - I2S-IN + AZALIA_PIN_CFG(0, 0x29, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x29 - I2S-IN 0x02050038, 0x02047901, 0x0205006b, 0x02040260, // NID 0x20 -0 Set Class-D output // power as 2.2W@4 Ohm, and // MIC2-VREFO-R is controlled by @@ -46,14 +46,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), // Pin widget 0x12 - DMIC AZALIA_PIN_CFG(0, 0x13, 0x40000000), // Pin widget 0x13 - DMIC AZALIA_PIN_CFG(0, 0x14, 0x90170110), // Pin widget 0x14 - Front (Port-D) - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // Pin widget 0x16 - NPC - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // Pin widget 0x17 - I2S OUT - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), // Pin widget 0x18 - I2S IN - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // Pin widget 0x19 - MIC2 (Port-F) - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // Pin widget 0x1A - NPC + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x16 - NPC + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x17 - I2S OUT + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x18 - I2S IN + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x19 - MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1A - NPC AZALIA_PIN_CFG(0, 0x1b, 0x04a19030), // Pin widget 0x1B - LINE2 (Port-E) AZALIA_PIN_CFG(0, 0x1d, 0x4066192d), // Pin widget 0x1D - BEEP-IN - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), // Pin widget 0x1E - S/PDIF-OUT + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), // Pin widget 0x1E - S/PDIF-OUT AZALIA_PIN_CFG(0, 0x21, 0x04211020), // Pin widget 0x21 - HP1-OUT (Port-I) 0x05c50011, 0x05c40003, 0x05c50011, 0x05c40003, // dis. Silence detect delay turn off 0x0205003c, 0x0204f254, 0x0205003c, 0x0204f214, // Class-D power on reset diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index c1b2f5c28c1c..f3c0be4561e7 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -55,7 +55,7 @@ chip soc/amd/genoa_poc device domain 0 on device ref iommu_0 on end device ref rcec_0 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P2 + chip vendorcode/amd/opensil/chip/mpio # P2 register "type" = "IFTYPE_PCIE" register "start_lane" = "48" register "end_lane" = "63" @@ -63,7 +63,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_0_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G2 + chip vendorcode/amd/opensil/chip/mpio # G2 register "type" = "IFTYPE_PCIE" register "start_lane" = "112" register "end_lane" = "127" @@ -72,7 +72,7 @@ chip soc/amd/genoa_poc register "hotplug" = "ServerExpress" device ref gpp_bridge_0_0_b on end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "128" register "end_lane" = "131" @@ -93,7 +93,7 @@ chip soc/amd/genoa_poc device domain 1 on device ref iommu_1 on end device ref rcec_1 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P3 + chip vendorcode/amd/opensil/chip/mpio # P3 register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "31" @@ -101,7 +101,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_1_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G3 + chip vendorcode/amd/opensil/chip/mpio # G3 register "type" = "IFTYPE_PCIE" register "start_lane" = "80" register "end_lane" = "95" @@ -114,7 +114,7 @@ chip soc/amd/genoa_poc device domain 2 on device ref iommu_2 on end device ref rcec_2 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P1 + chip vendorcode/amd/opensil/chip/mpio # P1 register "type" = "IFTYPE_PCIE" register "start_lane" = "32" register "end_lane" = "47" @@ -123,7 +123,7 @@ chip soc/amd/genoa_poc register "hotplug" = "ServerExpress" device ref gpp_bridge_2_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G1 + chip vendorcode/amd/opensil/chip/mpio # G1 register "type" = "IFTYPE_PCIE" register "start_lane" = "64" register "end_lane" = "79" @@ -137,7 +137,7 @@ chip soc/amd/genoa_poc device domain 3 on device ref iommu_3 on end device ref rcec_3 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P0 + chip vendorcode/amd/opensil/chip/mpio # P0 register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "15" @@ -145,7 +145,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_3_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G0 + chip vendorcode/amd/opensil/chip/mpio # G0 register "type" = "IFTYPE_PCIE" register "start_lane" = "96" register "end_lane" = "111" @@ -153,7 +153,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_3_0_b on end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "132" register "end_lane" = "133" @@ -161,7 +161,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_3_0_c on end # WAFL end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "134" register "end_lane" = "134" @@ -170,7 +170,7 @@ chip soc/amd/genoa_poc register "bmc" = "1" device ref gpp_bridge_3_1_c on end # BMC end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "135" register "end_lane" = "135" diff --git a/src/mainboard/amd/pademelon/hda_verb.c b/src/mainboard/amd/pademelon/hda_verb.c index 700953675da5..5bef966e75a4 100644 --- a/src/mainboard/amd/pademelon/hda_verb.c +++ b/src/mainboard/amd/pademelon/hda_verb.c @@ -12,8 +12,8 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), diff --git a/src/mainboard/aoostar/Kconfig b/src/mainboard/aoostar/Kconfig new file mode 100644 index 000000000000..170ea8820683 --- /dev/null +++ b/src/mainboard/aoostar/Kconfig @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_AOOSTAR + +choice + prompt "Mainboard model" + +source "src/mainboard/aoostar/*/Kconfig.name" + +endchoice + +source "src/mainboard/aoostar/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "AOOSTAR" + +endif # VENDOR_AOOSTAR diff --git a/src/mainboard/adlink/Kconfig.name b/src/mainboard/aoostar/Kconfig.name index 2781c4fc888a..e763b3fba9de 100644 --- a/src/mainboard/adlink/Kconfig.name +++ b/src/mainboard/aoostar/Kconfig.name @@ -1,4 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only -config VENDOR_ADLINK - bool "ADLINK" +config VENDOR_AOOSTAR + bool "AOOSTAR" diff --git a/src/mainboard/aoostar/wtr_r1/Kconfig b/src/mainboard/aoostar/wtr_r1/Kconfig new file mode 100644 index 000000000000..20c54b1484e0 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/Kconfig @@ -0,0 +1,48 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_AOOSTAR_WTR_R1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_DPTF + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SUPERIO_ITE_IT8613E + select DRIVERS_UART_8250IO + select USE_LEGACY_8254_TIMER + select SOC_INTEL_ALDERLAKE_PCH_N + +config MAINBOARD_DIR + default "aoostar/wtr_r1" + +config MAINBOARD_PART_NUMBER + default "WTR R1" + +config MAINBOARD_FAMILY + string + default "AOOSTAR_WTR_R1" + +config PCIEXP_ASPM + default y + +# Setting this makes NVMe SSD not work +config PCIEXP_L1_SUB_STATE + default n + +# Setting this makes 2.5Gb NICs not work +config PCIEXP_CLK_PM + default n + +# This platform has limited means to display POST codes +config NO_POST + default y + +endif #BOARD_AOOSTAR_WTR_R1 diff --git a/src/mainboard/aoostar/wtr_r1/Kconfig.name b/src/mainboard/aoostar/wtr_r1/Kconfig.name new file mode 100644 index 000000000000..45bfdecf752c --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_AOOSTAR_WTR_R1 + bool "WTR R1" diff --git a/src/mainboard/aoostar/wtr_r1/Makefile.mk b/src/mainboard/aoostar/wtr_r1/Makefile.mk new file mode 100644 index 000000000000..72915efea8da --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c diff --git a/src/mainboard/aoostar/wtr_r1/board_info.txt b/src/mainboard/aoostar/wtr_r1/board_info.txt new file mode 100644 index 000000000000..363cd5352fec --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: AOOSTAR +Board name: WTR R1 +Board URL: https://aoostar.com/products/aoostar-r1-2bay-nas-intel-n100-mini-pc-with-w11-pro-lpddr4-16gb-ram-512gb-ssd +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2023 diff --git a/src/mainboard/aoostar/wtr_r1/bootblock.c b/src/mainboard/aoostar/wtr_r1/bootblock.c new file mode 100644 index 000000000000..d494f9ad17ad --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/bootblock.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10 + ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31 + ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40 + ite_reg_write(GPIO_DEV, 0x29, 0x01); // Enable Pin GP50 + ite_reg_write(GPIO_DEV, 0x2c, 0x41); // Internal Voltage Divider for ACC3 + ite_reg_write(GPIO_DEV, 0xbc, 0xc0); // GP56, GP57 Internal pullup + ite_reg_write(GPIO_DEV, 0xbd, 0x03); // GP60, GP61 Internal pullup + ite_reg_write(GPIO_DEV, 0xc3, 0x41); // GP40, GP46 Simple I/O function + ite_set_3vsbsw(GPIO_DEV, true); + ite_delay_pwrgd3(GPIO_DEV); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/aoostar/wtr_r1/data.vbt b/src/mainboard/aoostar/wtr_r1/data.vbt Binary files differnew file mode 100644 index 000000000000..f25d9d9e0f00 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/data.vbt diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb new file mode 100644 index 000000000000..101bb99f5256 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -0,0 +1,212 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + register "sagv" = "SaGv_Enabled" + + register "dptf_enable" = "1" + + register "s0ix_enable" = "1" + + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + device domain 0 on + device ref igpu on + register "ddi_portA_config" = "1" + register "ddi_portB_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref dtt on end + device ref crashlog off end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" # USB3/2 Type A upper + end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), /* Type-C */ + [1] = USB2_PORT_MID(OC_SKIP), /* microSD card reader */ + [2] = USB2_PORT_MID(OC3), /* USB2 Type A upper */ + [3] = USB2_PORT_MID(OC3), /* USB2 Type A lower */ + [4] = USB2_PORT_MID(OC3), /* USB3/2 Type A upper */ + [5] = USB2_PORT_MID(OC3), /* USB3/2 Type A lower */ + [7] = USB2_PORT_MID(OC_SKIP), /* M.2 WLAN */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* Type-C */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* microSD card reader */ + [5] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A lower */ + [6] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A upper */ + }" + end + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c2 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref i2c3 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + }" + register "sata_ports_dev_slp" = "{ + [0] = 1, + [1] = 1, + }" + end + device ref i2c5 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + end + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X" + end + device ref pcie_rp7 on # LAN1 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + end + device ref pcie_rp9 on # LAN2 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + end + device ref pcie_rp10 on + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X" + end + device ref pch_espi on + # Needed for ITE SuperIO + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + chip superio/ite/it8613e + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "ec.vin_mask" = "VIN_ALL" + # CPU_FAN1 + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = " 1" + register "FAN2.smart.tmp_off" = "32" # Vendor default: 30 + register "FAN2.smart.tmp_start" = "35" + register "FAN2.smart.tmp_full" = "96" + register "FAN2.smart.tmp_delta" = " 1" # Vendor default: 2 + register "FAN2.smart.pwm_start" = "30" # Vendor default: 40 + register "FAN2.smart.slope" = " 1" + # SYSFANCN1 + register "FAN3.mode" = "FAN_SMART_SOFTWARE" + register "FAN3.smart.pwm_start" = "80" + # SYS_FAN1 + register "FAN4.mode" = "FAN_SMART_SOFTWARE" + register "FAN4.smart.pwm_start" = "127" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM 1 + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0x000 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0x71 = 0x01 + end + device pnp 2e.a off end # CIR + end + end + device ref uart0 on + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + end + device ref gspi0 on + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + }" + end + device ref ish on end + device ref hda on + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + end + device ref smbus on end + end +end diff --git a/src/mainboard/aoostar/wtr_r1/dsdt.asl b/src/mainboard/aoostar/wtr_r1/dsdt.asl new file mode 100644 index 000000000000..58c147e56c70 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/aoostar/wtr_r1/gpio.h b/src/mainboard/aoostar/wtr_r1/gpio.h new file mode 100644 index 000000000000..067b9cebb321 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/gpio.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), /* GSPI1_CLK_LOOPBK */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T0, NONE), + PAD_NC(GPP_T1, NONE), + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_EN */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_MODE */ + PAD_NC(GPP_T4, NONE), + PAD_NC(GPP_T5, NONE), + PAD_NC(GPP_T6, NONE), + PAD_NC(GPP_T7, NONE), + PAD_NC(GPP_T8, NONE), + PAD_NC(GPP_T9, NONE), + PAD_NC(GPP_T10, NONE), + PAD_NC(GPP_T11, NONE), + PAD_NC(GPP_T12, NONE), + PAD_NC(GPP_T13, NONE), + PAD_NC(GPP_T14, NONE), + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* ESPI_ALERT1# */ + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* USB_OC3# */ + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), + PAD_CFG_GPO(GPP_A21, 1, PLTRST), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* ESPI_CS1# */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_ESPI_CLK_LOOPBK */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + PAD_NC(GPP_I1, NONE), + PAD_NC(GPP_I2, NONE), + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_NC(GPP_I11, NONE), + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_NC(GPP_I18, NONE), + PAD_NC(GPP_I19, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + PAD_CFG_GPO(GPP_H1, 0, DEEP), + PAD_CFG_GPO(GPP_H2, 0, DEEP), + PAD_CFG_GPO(GPP_H3, 1, PLTRST), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* n/a */ + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_NC(GPP_H16, NONE), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* UART1_TXD */ + PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_GSPI2_CLK_LOOPBK */ + + /* ------- GPIO Group vGPIO ------- */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), /* GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), /* GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), /* GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), /* GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), /* GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), /* GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), /* GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), /* GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), /* GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), /* GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), /* GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), /* GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), /* GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), /* GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), /* GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), /* GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), /* GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), /* GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), /* GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), /* GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* GPP_VGPIO_37 */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* ACPRESENT */ + PAD_CFG_GPO(GPD2, 1, PLTRST), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 0, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), /* GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), /* GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), /* GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), /* GPD_WAKEB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), /* GPD_DRAM_RESETB */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* SMBALERT# */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_TERM_GPO(GPP_C5, 1, DN_20K, PLTRST), + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_PA_BLANKING */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* BOOTMPC */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* Reserved */ + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), /* SATAXPCIE0 */ + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_TERM_GPO(GPP_E6, 1, DN_20K, PLTRST), + PAD_NC(GPP_E7, NONE), + PAD_CFG_GPO(GPP_E8, 0, PLTRST), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), /* Reserved */ + PAD_CFG_GPO(GPP_E16, 0, PLTRST), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NATIVE), + PAD_NC(GPP_E19, NATIVE), + PAD_CFG_NF(GPP_E20, NATIVE, DEEP, NF5), /* BSSB_LS1_RX */ + PAD_CFG_NF(GPP_E21, NATIVE, DEEP, NF5), /* BSSB_LS1_TX */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c b/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c new file mode 100644 index 000000000000..1477bc038a46 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +#include "gpio.h" + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + /* According to DOC #573387 rcomp values no longer have to be provided */ + /* DDR DIMM configuration does not need to set DQ/DQS maps */ + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus[0] = { .addr_dimm[0] = 0x50, }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* + * Alder Lake common meminit block driver considers bus width to be 128-bit and + * populates the meminit data accordingly. Alder Lake-N has single memory controller + * with 64-bit bus width. By setting half_populated to true, only the bottom half is + * populated. + * TODO: Implement __weak variant_is_half_populated(void) function. + */ + const bool half_populated = true; + + memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, half_populated); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index c408d5a4f65c..176e2b8688ec 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -26,6 +26,14 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" + register "usb_port_config" = "{ + {1, 0, -1}, /* USB HUB 1 */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, /* Unused x7 */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, + {1, 0, -1}, /* USB HUB 2 */ + {1, 0, -1}, /* Camera */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, {0, 0, -1} /* Unused x4 */ + }" device ref mei1 on # Management Engine Interface 1 subsystemid 0x8086 0x7270 end diff --git a/src/mainboard/apple/macbookair4_2/early_init.c b/src/mainboard/apple/macbookair4_2/early_init.c index fc4b21534463..8eeb48291a90 100644 --- a/src/mainboard/apple/macbookair4_2/early_init.c +++ b/src/mainboard/apple/macbookair4_2/early_init.c @@ -1,24 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <northbridge/intel/sandybridge/raminit.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, /* USB HUB 1 */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 1, 0, -1 }, /* USB HUB 2 */ - { 1, 0, -1 }, /* Camera */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ - { 0, 0, -1 }, /* Unused */ -}; void mb_get_spd_map(struct spd_info *spdi) { diff --git a/src/mainboard/asrock/b75m-itx/Makefile.mk b/src/mainboard/asrock/b75m-itx/Makefile.mk index d1b484d2175a..ae57dabd07c3 100644 --- a/src/mainboard/asrock/b75m-itx/Makefile.mk +++ b/src/mainboard/asrock/b75m-itx/Makefile.mk @@ -3,6 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c -bootblock-y += early_init.c -romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb index 59645f04f2f8..8ecae251f6f3 100644 --- a/src/mainboard/asrock/b75m-itx/devicetree.cb +++ b/src/mainboard/asrock/b75m-itx/devicetree.cb @@ -27,6 +27,12 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, + {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, {1, 0, 3}, + {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, + {1, 1, 5}, {1, 1, 5}, {1, 0, 6} + }" device ref xhci on subsystemid 0x1849 0x1e31 diff --git a/src/mainboard/asrock/b75m-itx/early_init.c b/src/mainboard/asrock/b75m-itx/early_init.c deleted file mode 100644 index b70794aebace..000000000000 --- a/src/mainboard/asrock/b75m-itx/early_init.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, {1, 1, 2}, {1, 1, 2}, {1, 0, 3}, - {1, 0, 3}, {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, {1, 1, 5}, {1, 1, 5}, {1, 0, 6}, -}; diff --git a/src/mainboard/asrock/b75m-itx/hda_verb.c b/src/mainboard/asrock/b75m-itx/hda_verb.c index f770512a1b59..37f763ed65b0 100644 --- a/src/mainboard/asrock/b75m-itx/hda_verb.c +++ b/src/mainboard/asrock/b75m-itx/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x18498892, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x18498892), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19850), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01452130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index e2c898d0b86c..1cf501549e64 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -39,6 +39,22 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 } + }" device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 diff --git a/src/mainboard/asrock/b75pro3-m/early_init.c b/src/mainboard/asrock/b75pro3-m/early_init.c index 4052b6f22dd3..1ffd896e2657 100644 --- a/src/mainboard/asrock/b75pro3-m/early_init.c +++ b/src/mainboard/asrock/b75pro3-m/early_init.c @@ -8,23 +8,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ diff --git a/src/mainboard/asrock/b75pro3-m/hda_verb.c b/src/mainboard/asrock/b75pro3-m/hda_verb.c index 0cd7ad47ea65..a3d894d6a1cd 100644 --- a/src/mainboard/asrock/b75pro3-m/hda_verb.c +++ b/src/mainboard/asrock/b75pro3-m/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x18498892, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x18498892), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19950), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214120), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01452130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c index dc3c1408570f..8b908c516cf3 100644 --- a/src/mainboard/asrock/b85m_pro4/hda_verb.c +++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c @@ -7,15 +7,15 @@ const u32 cim_verb_data[] = { 0x1849c892, /* Subsystem ID */ 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x1849c892), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014020), AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), AZALIA_PIN_CFG(0, 0x1d, 0x598301f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221102f), 0x10ec0887, /* Codec Vendor / Device ID: Realtek ALC887 */ @@ -23,18 +23,18 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x1458a002), AZALIA_PIN_CFG(2, 0x11, 0x411110f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1f, 0x41c46060), 0x80862806, /* Codec Vendor / Device ID: Intel Haswell HDMI */ diff --git a/src/mainboard/asrock/g41c-gs/hda_verb.c b/src/mainboard/asrock/g41c-gs/hda_verb.c index 5fce4333c889..134c34092f16 100644 --- a/src/mainboard/asrock/g41c-gs/hda_verb.c +++ b/src/mainboard/asrock/g41c-gs/hda_verb.c @@ -12,15 +12,15 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19830), AZALIA_PIN_CFG(0, 0x19, 0x02a19940), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x02214120), AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* coreboot specific header */ /* Intel Eaglelake HDMI */ @@ -40,15 +40,15 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c30), AZALIA_PIN_CFG(2, 0x19, 0x02a19c40), AZALIA_PIN_CFG(2, 0x1a, 0x0181343f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asrock/h110m/Makefile.mk b/src/mainboard/asrock/h110m/Makefile.mk index e8ff53e6e8f0..65ac73386c65 100644 --- a/src/mainboard/asrock/h110m/Makefile.mk +++ b/src/mainboard/asrock/h110m/Makefile.mk @@ -1,6 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -subdirs-y += spd bootblock-y += bootblock.c ramstage-y += mainboard.c diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c index 82cf54523b19..a19634e6f4f3 100644 --- a/src/mainboard/asrock/h110m/hda_verb.c +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -8,19 +8,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10438445), AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014020), AZALIA_PIN_CFG(0, 0x15, 0x90170110), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19040), AZALIA_PIN_CFG(0, 0x19, 0x02a19050), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214030), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4026c629), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 2624c38ebe46..05cb87050bb0 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -21,6 +21,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 0, 6 } + }" device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 end diff --git a/src/mainboard/asrock/h77pro4-m/early_init.c b/src/mainboard/asrock/h77pro4-m/early_init.c index 4637378456a4..df8f0436573a 100644 --- a/src/mainboard/asrock/h77pro4-m/early_init.c +++ b/src/mainboard/asrock/h77pro4-m/early_init.c @@ -21,23 +21,6 @@ enum cpu_fan_tach_src { CPU_FAN_HEADER_BOTH }; -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 0, 6 }, -}; - /* * The tachometer signal that goes to CPUFANIN of the Super I/O is set via * GPIOs. diff --git a/src/mainboard/asrock/h77pro4-m/hda_verb.c b/src/mainboard/asrock/h77pro4-m/hda_verb.c index 51133e7c7c4b..7fbb3310a820 100644 --- a/src/mainboard/asrock/h77pro4-m/hda_verb.c +++ b/src/mainboard/asrock/h77pro4-m/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x18498892, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x18498892), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19950), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214120), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01452130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asrock/h81m-hds/hda_verb.c b/src/mainboard/asrock/h81m-hds/hda_verb.c index 5b372bf35048..eea210d1d097 100644 --- a/src/mainboard/asrock/h81m-hds/hda_verb.c +++ b/src/mainboard/asrock/h81m-hds/hda_verb.c @@ -10,14 +10,14 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(1, 0x18497662), AZALIA_PIN_CFG(1, 0x14, 0x01014010), AZALIA_PIN_CFG(1, 0x15, 0x40000000), - AZALIA_PIN_CFG(1, 0x16, 0x411111f0), + AZALIA_PIN_CFG(1, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x18, 0x01a19040), AZALIA_PIN_CFG(1, 0x19, 0x02a19050), AZALIA_PIN_CFG(1, 0x1a, 0x0181304f), AZALIA_PIN_CFG(1, 0x1b, 0x02214020), - AZALIA_PIN_CFG(1, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x1d, 0x40a4c601), - AZALIA_PIN_CFG(1, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/asrock/z87e-itx/Kconfig b/src/mainboard/asrock/z87e-itx/Kconfig new file mode 100644 index 000000000000..9eebc90e68bf --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z87E_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select GFX_GMA_ANALOG_I2C_HDMI_B + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87e-itx" + +config MAINBOARD_PART_NUMBER + default "Z87E-ITX" + +config USBDEBUG_HCD_INDEX + default 1 # This is the top most of the USB-2.0-only ports +endif diff --git a/src/mainboard/asrock/z87e-itx/Kconfig.name b/src/mainboard/asrock/z87e-itx/Kconfig.name new file mode 100644 index 000000000000..f152649b5c99 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z87E_ITX + bool "Z87E-ITX" diff --git a/src/mainboard/asrock/z87e-itx/Makefile.mk b/src/mainboard/asrock/z87e-itx/Makefile.mk new file mode 100644 index 000000000000..058a390189aa --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87e-itx/acpi/ec.asl b/src/mainboard/asrock/z87e-itx/acpi/ec.asl new file mode 100644 index 000000000000..16990d45f428 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87e-itx/acpi/platform.asl b/src/mainboard/asrock/z87e-itx/acpi/platform.asl new file mode 100644 index 000000000000..aff432b6f47a --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87e-itx/acpi/superio.asl b/src/mainboard/asrock/z87e-itx/acpi/superio.asl new file mode 100644 index 000000000000..ee2eabeb756e --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z87e-itx/board_info.txt b/src/mainboard/asrock/z87e-itx/board_info.txt new file mode 100644 index 000000000000..4b2f887d5e79 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z87e-itx/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87e-itx/bootblock.c b/src/mainboard/asrock/z87e-itx/bootblock.c new file mode 100644 index 000000000000..a64cdfb72384 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/z87e-itx/data.vbt b/src/mainboard/asrock/z87e-itx/data.vbt Binary files differnew file mode 100644 index 000000000000..4bb86662ce3f --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/data.vbt diff --git a/src/mainboard/asrock/z87e-itx/devicetree.cb b/src/mainboard/asrock/z87e-itx/devicetree.cb new file mode 100644 index 000000000000..32883e4144f0 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/devicetree.cb @@ -0,0 +1,132 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1849 0x0412 + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "gpe0_en_1" = "0x46" + + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1150 + end + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO8 + irq 0xe4 = 0xef # + GPIO8 direction + irq 0xe5 = 0 # + GPIO8 value + end + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 on end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # + GPIO2 direction + end + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on # GPIO5 + irq 0xf4 = 0x7f # + GPIO5 direction + irq 0xf5 = 0x80 # + GPIO5 value + end + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe6 = 0x4c + irq 0xf0 = 0x40 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + irq 0xf7 = 0 # + Front Panel Green LED + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0 # + GPIOA direction + irq 0xe1 = 0 # + GPIOA value + end + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87e-itx/dsdt.asl b/src/mainboard/asrock/z87e-itx/dsdt.asl new file mode 100644 index 000000000000..b62c922dc252 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87e-itx/gma-mainboard.ads b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads new file mode 100644 index 000000000000..cd05ae2fb817 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI1, -- DVI-I + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- DVI-I + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87e-itx/gpio.c b/src/mainboard/asrock/z87e-itx/gpio.c new file mode 100644 index 000000000000..ff9a21db35e7 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87e-itx/hda_verb.c b/src/mainboard/asrock/z87e-itx/hda_verb.c new file mode 100644 index 000000000000..7164c57149f2 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491150, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491150), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87e-itx/romstage.c b/src/mainboard/asrock/z87e-itx/romstage.c new file mode 100644 index 000000000000..b50390e67c53 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig b/src/mainboard/asrock/z97_extreme6/Kconfig new file mode 100644 index 000000000000..d47e3a204797 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z97_EXTREME6 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6791D + select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT + +config CBFS_SIZE + default 0x200000 + +config MAINBOARD_DIR + default "asrock/z97_extreme6" + +config MAINBOARD_PART_NUMBER + default "Z97 Extreme6" + +endif diff --git a/src/mainboard/asrock/z97_extreme6/Kconfig.name b/src/mainboard/asrock/z97_extreme6/Kconfig.name new file mode 100644 index 000000000000..24435876406b --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z97_EXTREME6 + bool "Z97 Extreme6" diff --git a/src/mainboard/asrock/z97_extreme6/Makefile.mk b/src/mainboard/asrock/z97_extreme6/Makefile.mk new file mode 100644 index 000000000000..513c347cbdad --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z97_extreme6/acpi/ec.asl b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl new file mode 100644 index 000000000000..16990d45f428 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z97_extreme6/acpi/platform.asl b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl new file mode 100644 index 000000000000..7da03bfddd02 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_PTS, 1) +{ +} + +Method(_WAK, 1) +{ + Return(Package(){0, 0}) +} diff --git a/src/mainboard/asrock/z97_extreme6/acpi/superio.asl b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl new file mode 100644 index 000000000000..ee2eabeb756e --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z97_extreme6/board_info.txt b/src/mainboard/asrock/z97_extreme6/board_info.txt new file mode 100644 index 000000000000..bd0147425432 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z97%20extreme6/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/asrock/z97_extreme6/bootblock.c b/src/mainboard/asrock/z97_extreme6/bootblock.c new file mode 100644 index 000000000000..318cc034f201 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/bootblock.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +#define GLOBAL_DEV PNP_DEV(0x2e, 0) +#define SERIAL_DEV PNP_DEV(0x2e, NCT6791D_SP1) +#define ACPI_DEV PNP_DEV(0x2e, NCT6791D_ACPI) +#define GPIO_PP_OD_DEV PNP_DEV(0x2e, NCT6791D_GPIO_PP_OD) + +/* + * Asrock Z97 Extreme6 Super I/O GPIOs + * + * +------+-----+---------------------------+ + * | GPIO | Pin | Description | + * +------+-----+---------------------------+ + * | GP00 | 121 | N/C | + * | GP01 | 122 | CHA_FAN2 PWM output | + * | GP02 | 123 | CHA_FAN3 PWM output | + * | GP03 | 2 | N/C | + * | GP04 | 3 | CHA_FAN3 tach input | + * | GP05 | 4 | CHA_FAN2 tach input | + * | GP06 | 5 | PWR_FAN tach input | + * | GP07 | 6 | N/C (SE_IFDET) | + * +------+-----+---------------------------+ + * | GP10 | 14 | HDD Saver power switch | + * | GP11 | 13 | Assert HDA_SDO (SIO_GP11) | + * | GP12 | 12 | CPU_FAN2 FON# | + * | GP13 | 11 | SATA_SEL (for eSATA) | + * | GP14 | 10 | N/C | + * | GP15 | 9 | N/C (UARTP80_EN) | + * | GP16 | 8 | OTP for VCORE (OTE_GATE1) | + * | GP17 | 7 | LED_EN# | + * +------+-----+---------------------------+ + * | GP20 | 59 | KDAT | + * | GP21 | 58 | KCLK | + * | GP22 | 57 | MDAT | + * | GP23 | 56 | MCLK | + * | GP24 | 95 | SE_DEVSLP (SATA Express) | + * | GP25 | 96 | N/C (SIO_GP25) | + * | GP26 | 53 | N/C | + * | GP27 | 98 | M2_2_SE_IFDET | + * +------+-----+---------------------------+ + * | GP30 | 83 | N/C (RESETCON#) | + * | GP31 | 76 | BIOS_A (or SML1DAT) | + * | GP32 | 75 | BIOS_B (or SML1CLK) | + * | GP33 | 71 | 3VSBSW# | + * | GP34 | 55 | VCORE_OFFSET# | + * | GP35 | 54 | N/C | + * | GP36 | 53 | N/C | + * | GP37 | 7 | LED_EN# | + * +------+-----+---------------------------+ + * | GP40 | 62 | N/C (TEST_EN) | + * | GP41 | 52 | N/C | + * | GP42 | 51 | WLAN1_ON/OFF# | + * | GP43 | 41 | Port 80 display - DGL_0# | + * | GP44 | 40 | PWR_LED gate | + * | GP45 | 39 | HDD_LED gate | + * | GP46 | 38 | CHA_FAN3 FON# | + * | GP47 | 37 | CHA_FAN2 FON# | + * +------+-----+---------------------------+ + * | GP50 | 93 | N/C (SUSWARN#) | + * | GP51 | 92 | CPU_FAN2 tach input | + * | GP52 | 91 | N/C (SUSACK#) | + * | GP53 | 90 | SUSWARN_5VDUAL | + * | GP54 | 89 | SLP_SUS# | + * | GP55 | 88 | SLP_SUS_FET | + * | GP56 | 87 | PEG12V_DET (Molex conn) | + * | GP57 | 86 | PCIE4_SEL (PCIE3 / mPCIe) | + * +------+-----+---------------------------+ + * | GP70 | 69 | N/C (DSW_EN) | + * | GP71 | 68 | N/C | + * | GP72 | 67 | N/C | + * | GP73 | 66 | M.2 / SATA Express select | + * | GP74 | 79 | RESET# of long PCIe ports | + * | GP75 | 78 | RESET# for on-board chips | + * | GP76 | 77 | RESET# SATA Express / M.2 | + * | GP77 | 86 | HDD_LED gate | + * +------+-----+---------------------------+ + * + * HWM voltage inputs + * + * +------+-----+---------------------------+ + * | Name | Pin | Voltage (resistor values) | + * +------+-----+---------------------------+ + * | VIN0 | 104 | +12V (110K / 10K) | + * | VIN1 | 105 | +5V (20K / 10K) | + * | VIN2 | 106 | CPU_VRING | + * | VIN3 | 107 | CPU_VSA | + * | VIN4 | 111 | CPU_VCORE0 | + * | VIN5 | 114 | CPU_VGFX | + * | VIN6 | 115 | V_VCCIOA_LOAD | + * | VIN7 | 116 | N/C | + * | VIN8 | 103 | CPU_VIO | + * +------+-----+---------------------------+ + */ + +void mainboard_config_superio(void) +{ + nuvoton_pnp_enter_conf_state(GLOBAL_DEV); + + /* Select SIO pin mux states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0xe6); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x10); + pnp_write_config(GLOBAL_DEV, 0x24, 0xfc); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x40); + pnp_write_config(GLOBAL_DEV, 0x2b, 0x20); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x00); + pnp_write_config(GLOBAL_DEV, 0x2d, 0x02); + + /* Select push-pull vs. open-drain output */ + pnp_set_logical_device(GPIO_PP_OD_DEV); + pnp_write_config(GPIO_PP_OD_DEV, 0xe0, 0xfe); + pnp_write_config(GPIO_PP_OD_DEV, 0xe2, 0x79); + pnp_write_config(GPIO_PP_OD_DEV, 0xe6, 0x6f); + + /* Power RAM in S3 */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x10); + + nuvoton_pnp_exit_conf_state(GLOBAL_DEV); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z97_extreme6/data.vbt b/src/mainboard/asrock/z97_extreme6/data.vbt Binary files differnew file mode 100644 index 000000000000..6a73a2662626 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/data.vbt diff --git a/src/mainboard/asrock/z97_extreme6/devicetree.cb b/src/mainboard/asrock/z97_extreme6/devicetree.cb new file mode 100644 index 000000000000..2258a1bfd142 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/devicetree.cb @@ -0,0 +1,130 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + + # This mainboard has DVI-I + register "gpu_ddi_e_connected" = "1" + + # This mainboard has a DP output + register "gpu_dp_c_hotplug" = "7" + + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + + device domain 0 on + ops haswell_pci_domain_ops + subsystemid 0x1849 0x0c00 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # Bifurcated PEG: PCIE2 slot + device pci 01.1 on end # Bifurcated PEG: PCIE4 slot + device pci 01.2 on end # Bifurcated PEG: M2_1 slot + device pci 02.0 on end # iGPU + device pci 03.0 on end # Mini-HD + + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" # Super I/O HWM + register "sata_port_map" = "0x3f" + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # MEI #1 + device pci 16.1 off end # MEI #2 + device pci 19.0 on end # Intel GbE through I218-V PHY + device pci 1a.0 on end # EHCI #2 + device pci 1b.0 on end # HD Audio + device pci 1c.0 on end # RP #1: muxed M2_2 slot, SATA Express + device pci 1c.1 off end # RP #2 + device pci 1c.2 on # RP #3: Realtek RTL8111E GbE NIC + device pci 00.0 on end + end + device pci 1c.3 on end # RP #4: ASM1184E 4-Port PCIe switch + device pci 1c.4 on end # RP #5: PCIE5 slot + device pci 1c.5 off end # RP #6 + device pci 1c.6 on end # RP #7: ASM1042A USB 3.0 + device pci 1c.7 off end # RP #8 + device pci 1d.0 on end # EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.0 on + chip superio/nuvoton/nct6791d + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 on # GPIO7 + irq 0xe0 = 0x6f + irq 0xe1 = 0x10 + end + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 on # GPIO1 + irq 0xf0 = 0xbe + irq 0xf1 = 0x01 + end + device pnp 2e.9 on # GPIO2 + irq 0xe0 = 0xff + irq 0xe1 = 0x00 + end + device pnp 2e.109 on # GPIO3 + irq 0xe4 = 0x6f + irq 0xe5 = 0x72 + end + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0x0f + irq 0xf1 = 0x00 + end + device pnp 2e.309 on # GPIO5 + irq 0xf4 = 0xdf + irq 0xf5 = 0x00 + end + device pnp 2e.a on # ACPI + # Power RAM in S3 + irq 0xe4 = 0x10 + irq 0xe5 = 0x12 + irq 0xed = 0x01 + irq 0xf0 = 0x30 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 on end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end # TPM + end + end + device pci 1f.2 on end # SATA (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA (Legacy) + end + end +end diff --git a/src/mainboard/asrock/z97_extreme6/dsdt.asl b/src/mainboard/asrock/z97_extreme6/dsdt.asl new file mode 100644 index 000000000000..17c44b652330 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads new file mode 100644 index 000000000000..cd05ae2fb817 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI1, -- DVI-I + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- DVI-I + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z97_extreme6/gpio.c b/src/mainboard/asrock/z97_extreme6/gpio.c new file mode 100644 index 000000000000..1dee18cc7e76 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/gpio.c @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z97_extreme6/hda_verb.c b/src/mainboard/asrock/z97_extreme6/hda_verb.c new file mode 100644 index 000000000000..db4364c4e3a0 --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek ALC1150 */ + 0x18491151, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491151), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z97_extreme6/romstage.c b/src/mainboard/asrock/z97_extreme6/romstage.c new file mode 100644 index 000000000000..a344dee1a58c --- /dev/null +++ b/src/mainboard/asrock/z97_extreme6/romstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB3_6_7 */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, /* ASM1074 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB2_3 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL }, /* USB4_5 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* USB1 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* MINI_PCIE1 */ + { 0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Can be used if ASM1042 */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* has not been installed */ +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_4_5 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */ + { 1, USB_OC_PIN_SKIP }, /* USB3_6_7 */ + { 1, USB_OC_PIN_SKIP }, /* ASM1074 */ + { 0, USB_OC_PIN_SKIP }, /* N/A, GbE */ +}; diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index 7f37acc7cad8..365b5ed4e95c 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -11,6 +11,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref mei1 on end device ref mei2 off end diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c index 50e225a0d45e..bec2f6d5f6ec 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/early_init.c @@ -10,23 +10,6 @@ #define SIO_DEV PNP_DEV(SIO_PORT, 0) #define ACPI_DEV PNP_DEV(SIO_PORT, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(SIO_DEV); diff --git a/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c index 0a3a75c5dbc3..05c9b296d4b3 100644 --- a/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c +++ b/src/mainboard/asus/h61-series/variants/h61m-cs/hda_verb.c @@ -9,19 +9,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10438445), AZALIA_PIN_CFG(0, 0x11, 0x40330000), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19030), AZALIA_PIN_CFG(0, 0x19, 0x02a19040), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4024c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c index 5f5c684aa2f3..2217a6c73560 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/early_init.c @@ -7,23 +7,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c index 3b707c2cd468..dbd4a5af0929 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx/hda_verb.c @@ -9,19 +9,19 @@ const u32 cim_verb_data[] = { 15, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x10438445), AZALIA_PIN_CFG(0, 0x11, 0x99430130), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c index 404a8503bf71..8f716dae35d3 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/early_init.c @@ -9,23 +9,6 @@ #define GLOBAL_DEV PNP_DEV(0x2e, 0) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c index 1c8d84442b7f..d7cd486b4364 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* Enable UART */ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c index 9f77ac7f9eff..7b6e06899224 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro/hda_verb.c @@ -8,7 +8,7 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10438444), AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01456130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c index e76e1094cb5e..dc00ec37fa91 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c index 129797b6c181..87a6cd6e5ce6 100644 --- a/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c +++ b/src/mainboard/asus/h61-series/variants/p8h61-m_pro_cm6630/hda_verb.c @@ -8,7 +8,7 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10438444), AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01456130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862805, /* Codec Vendor / Device ID: Intel HDMI */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 2642fbd68b65..79213c41a0c0 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -15,6 +15,23 @@ chip northbridge/intel/sandybridge register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" + device ref mei1 on end device ref mei2 off end device ref me_ide_r off end diff --git a/src/mainboard/asus/maximus_iv_gene-z/early_init.c b/src/mainboard/asus/maximus_iv_gene-z/early_init.c index ed593f65f592..bd741c35717d 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/early_init.c +++ b/src/mainboard/asus/maximus_iv_gene-z/early_init.c @@ -6,23 +6,6 @@ #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); diff --git a/src/mainboard/asus/p5gc-mx/hda_verb.c b/src/mainboard/asus/p5gc-mx/hda_verb.c index f1fc9f6fab13..9da73841b9b4 100644 --- a/src/mainboard/asus/p5gc-mx/hda_verb.c +++ b/src/mainboard/asus/p5gc-mx/hda_verb.c @@ -10,9 +10,9 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19850), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), @@ -20,7 +20,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), AZALIA_PIN_CFG(0, 0x1e, 0x18561130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asus/p5qc/hda_verb.c b/src/mainboard/asus/p5qc/hda_verb.c index 289443a24d5f..9fc478fcf13b 100644 --- a/src/mainboard/asus/p5qc/hda_verb.c +++ b/src/mainboard/asus/p5qc/hda_verb.c @@ -22,7 +22,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), AZALIA_PIN_CFG(0, 0x1e, 0x01447130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asus/p5ql-em/hda_verb.c b/src/mainboard/asus/p5ql-em/hda_verb.c index 984e583d41c4..861b6595275a 100644 --- a/src/mainboard/asus/p5ql-em/hda_verb.c +++ b/src/mainboard/asus/p5ql-em/hda_verb.c @@ -20,8 +20,8 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* HDMI audio */ 0x80862803, diff --git a/src/mainboard/asus/p5qpl-am/hda_verb.c b/src/mainboard/asus/p5qpl-am/hda_verb.c index 81f55bf16c17..525aab2c53ce 100644 --- a/src/mainboard/asus/p5qpl-am/hda_verb.c +++ b/src/mainboard/asus/p5qpl-am/hda_verb.c @@ -11,12 +11,12 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19850), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), @@ -24,7 +24,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), AZALIA_PIN_CFG(0, 0x1e, 0x99430130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 4052cf43ad2c..e9b97bc7ba94 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -7,11 +7,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} - }" # 4 bit switch mask. 0=not switchable, 1=switchable # Means once it's loaded the OS, it can swap ports # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c index 79b67f07f17c..1e21f2062bff 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c index 574da72fe006..03430f1c352c 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/hda_verb.c @@ -8,7 +8,7 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x104384fb), AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x014b6130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 4b7bb1c75eff..1e8d80766946 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -7,6 +7,22 @@ chip northbridge/intel/sandybridge subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" device ref pcie_rp1 on end # PCIEX16_4 (electrical x4) device ref pcie_rp2 off end device ref pcie_rp3 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c index 89f9eee10634..056dfd467dbb 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index dbf1f359b5e1..138930467161 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -4,6 +4,22 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) device ref pcie_rp2 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default index 3cc854d6c3b1..79ea5604660d 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.default @@ -9,3 +9,4 @@ sata_mode=AHCI usb3_mode=Enable usb3_drv=Enable usb3_streams=Enable +audio_panel_type=HDA diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout index 3053b8d91306..86bd35a907cc 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/cmos.layout @@ -51,6 +51,11 @@ entries # 424 1 e 1 usb3_streams +# audio_panel_type +# HD Audio or AC'97 +# +425 1 e 9 audio_panel_type + # ----------------------------------------------------------------- # Sandy/Ivy Bridge MRC Scrambler Seed values # note: MUST NOT be covered by checksum! @@ -128,6 +133,10 @@ enumerations 8 2 Auto 8 3 SmartAuto +# audio_panel_type +9 0 HDA +9 1 AC97 + # ----------------------------------------------------------------- # <startBit[must be byte-aligned]> <endBit[must be byte aligned]> # <bit where to start storing checksum[must be 16bits-aligned]> diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index 47c5cb302dab..6897658ad53d 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -12,24 +12,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* {enable, current, oc_pin} */ - {1, 2, 0}, /* Port 0: USB3 front internal header, top */ - {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ - {1, 2, 1}, /* Port 2: USB3 rear, top */ - {1, 2, 1}, /* Port 3: USB3 rear, bottom */ - {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ - {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ - {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ - {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ - {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ - {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ - {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ - {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ - {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ - {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c index 738ba535695f..b553b17a84e8 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/hda_verb.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <device/azalia_device.h> +#include <stdint.h> + +#include <option.h> const u32 cim_verb_data[] = { 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ @@ -34,3 +37,32 @@ const u32 cim_verb_data[] = { const u32 pc_beep_verbs[0] = {}; AZALIA_ARRAY_SIZES; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + unsigned int ac97 = get_uint_option("audio_panel_type", 0) & 0x1; + + /* + * The verbs above are for a HD Audio front panel. + * With vendor firmware, if audio front panel type is set as AC97, line out 2 + * (0x1b) and mic 2 (0x19) pins of ALC887 are configured differently. + * + * The differences are all in the "Misc" fields of configuration defaults (in byte 2) + * as shown below. ALC887 datasheet did not offer details on what those bits + * (listed as reserved in HDA spec) are, so we'll have to take their word for it. + * + * Pin | 0x19 | 0x1b + * -----+------+----- + * HDA | 1100 | 1100 + * AC97 | 1001 | 0001 + */ + + const u32 verbs[] = { + AZALIA_VERB_12B(0, 0x19, 0x71d, 0x99), + AZALIA_VERB_12B(0, 0x1b, 0x71d, 0x41) + }; + + if ((viddid == 0x10ec0887) && ac97) { + azalia_program_verb_table(base, verbs, ARRAY_SIZE(verbs)); + } +} diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index b3d05fe3ec54..6232c9be8374 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -1,15 +1,26 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} - }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + {1, 8, 0}, /* Port 0: USB3 front internal header, top */ + {1, 8, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 2, 1}, /* Port 2: USB3 rear, top */ + {1, 2, 1}, /* Port 3: USB3 rear, bottom */ + {1, 2, 2}, /* Port 4: USB2 rear PS2, top */ + {1, 2, 2}, /* Port 5: USB2 rear PS2, bottom */ + {1, 2, 3}, /* Port 6: USB2 rear LAN, top */ + {1, 2, 3}, /* Port 7: USB2 rear LAN, bottom */ + {1, 9, 4}, /* Port 8: USB2 internal header USB910, top */ + {1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */ + {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ + {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ + {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ + {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ + }" device ref pcie_rp1 on end # PCIe x4 slot device ref pcie_rp2 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c index cec5070a1046..4940b54eb9fd 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c @@ -14,24 +14,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2) -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* {enable, current, oc_pin} */ - { 1, 2, 0 }, /* Port 0: USB3 front internal header, top */ - { 1, 2, 0 }, /* Port 1: USB3 front internal header, bottom */ - { 1, 2, 1 }, /* Port 2: USB3 rear, ETH top */ - { 1, 2, 1 }, /* Port 3: USB3 rear, ETH bottom */ - { 1, 2, 2 }, /* Port 4: USB2 rear, PS2 top */ - { 1, 2, 2 }, /* Port 5: USB2 rear, PS2 bottom */ - { 1, 2, 3 }, /* Port 6: USB2 internal header USB78, top */ - { 1, 2, 3 }, /* Port 7: USB2 internal header USB78, bottom */ - { 1, 2, 4 }, /* Port 8: USB2 internal header USB910, top */ - { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ - { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ - { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ - { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ - { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ -}; - void bootblock_mainboard_early_init(void) { nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c index a4a7a3e091d8..696134b00a44 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/hda_verb.c @@ -8,7 +8,7 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10438436), AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01456130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb index da34af3b12eb..4613c128e2ef 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/overridetree.cb @@ -1,17 +1,28 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/sandybridge - register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {0, 5, 0x0080}, {0, 6, 0x0080} - }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" register "gen4_dec" = "0x0000ff29" register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, 2, 0}, + {1, 2, 0}, + {1, 2, 1}, + {1, 2, 1}, + {1, 2, 2}, + {1, 2, 2}, + {1, 2, 3}, + {1, 2, 3}, + {1, 2, 4}, + {1, 2, 4}, + {1, 2, 6}, + {1, 2, 5}, + {0, 2, 5}, + {0, 2, 6} + }" device ref pcie_rp1 on end # PCIEX_16_3 device ref pcie_rp2 on end # RTL8111F diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c index c16b055aa4de..290523f5fdfd 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c @@ -11,23 +11,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 2, 0 }, - { 1, 2, 0 }, - { 1, 2, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 2, 2 }, - { 1, 2, 3 }, - { 1, 2, 3 }, - { 1, 2, 4 }, - { 1, 0, 4 }, - { 1, 2, 6 }, - { 1, 2, 5 }, - { 1, 2, 5 }, - { 1, 2, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c index e431593ab4ac..efbf7bf979e7 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/hda_verb.c @@ -8,7 +8,7 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x104384fb), AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181305f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005e601), AZALIA_PIN_CFG(0, 0x1e, 0x01456130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb index 043be06a24bb..adbb10a3b647 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb @@ -5,6 +5,22 @@ chip northbridge/intel/sandybridge subsystemid 0x1043 0x84ca inherit device ref peg11 on end # PCIEX_16_2 chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 2, 0 }, + { 1, 2, 0 }, + { 1, 2, 1 }, + { 1, 9, 1 }, + { 1, 9, 2 }, + { 1, 2, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 2, 4 }, + { 1, 9, 4 }, + { 1, 2, 6 }, + { 1, 2, 5 }, + { 1, 2, 5 }, + { 1, 2, 6 } + }" register "gen1_dec" = "0x000c0291" device ref gbe on end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c index 89f9eee10634..056dfd467dbb 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/early_init.c @@ -10,23 +10,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6779D_ACPI) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c index 650cd7c99095..a474a7562c34 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/hda_verb.c @@ -8,19 +8,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10438445), AZALIA_PIN_CFG(0, 0x11, 0x99430130), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel HDMI */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 0ae41b3accd4..66bc5bb18061 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -4,6 +4,23 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } +}" + register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) diff --git a/src/mainboard/biostar/th61-itx/Makefile.mk b/src/mainboard/biostar/th61-itx/Makefile.mk index 33b55d2d4ff0..51125d39e949 100644 --- a/src/mainboard/biostar/th61-itx/Makefile.mk +++ b/src/mainboard/biostar/th61-itx/Makefile.mk @@ -5,5 +5,3 @@ romstage-y += gpio.c ramstage-y += hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index af9f9b593786..b75c92e451ef 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -15,6 +15,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" device ref mei1 on end # MEI #1 device ref ehci2 on end # EHCI #2 diff --git a/src/mainboard/biostar/th61-itx/hda_verb.c b/src/mainboard/biostar/th61-itx/hda_verb.c index 2b6d27604d0a..b8b407ab094c 100644 --- a/src/mainboard/biostar/th61-itx/hda_verb.c +++ b/src/mainboard/biostar/th61-itx/hda_verb.c @@ -8,19 +8,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x15658229), AZALIA_PIN_CFG(2, 0x11, 0x01452130), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), AZALIA_PIN_CFG(2, 0x15, 0x01011412), AZALIA_PIN_CFG(2, 0x16, 0x01016411), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c40), AZALIA_PIN_CFG(2, 0x19, 0x02a19850), AZALIA_PIN_CFG(2, 0x1a, 0x0181344f), AZALIA_PIN_CFG(2, 0x1b, 0x02214020), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4005e601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c b/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c index 7bb073698d1a..79030252d306 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/hda_verb.c @@ -12,13 +12,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x01a1913c), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41748245), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Intel GPU HDMI */ 0x8086280b, /* Vendor ID */ diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c index 05bb273a7403..68f4159dcae0 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/hda_verb.c @@ -13,11 +13,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x02211010), AZALIA_PIN_CFG(0, 0x17, 0x40000000), AZALIA_PIN_CFG(0, 0x18, 0x02a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Intel iGPU HDMI */ 0x8086280b, diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index d09c9e0b1f4d..0c793095632b 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -48,6 +48,22 @@ chip northbridge/intel/sandybridge # FIXME: check gfx register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref xhci on end # USB 3.0 Controller device ref mei1 off end # Management Engine Interface 1 diff --git a/src/mainboard/compulab/intense_pc/early_init.c b/src/mainboard/compulab/intense_pc/early_init.c index f5859e99d6da..4a4308e92a53 100644 --- a/src/mainboard/compulab/intense_pc/early_init.c +++ b/src/mainboard/compulab/intense_pc/early_init.c @@ -8,23 +8,6 @@ #define SIO_PORT 0x164e -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 4 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { const u16 port = SIO_PORT; diff --git a/src/mainboard/compulab/intense_pc/hda_verb.c b/src/mainboard/compulab/intense_pc/hda_verb.c index 8ec2616894b0..c16f73b9c0ec 100644 --- a/src/mainboard/compulab/intense_pc/hda_verb.c +++ b/src/mainboard/compulab/intense_pc/hda_verb.c @@ -8,17 +8,17 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10ec0888), AZALIA_PIN_CFG(0, 0x11, 0x411110f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01214120), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19131), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1e, 0x014421f0), AZALIA_PIN_CFG(0, 0x1f, 0x01c421f0), diff --git a/src/mainboard/cwwk/Kconfig b/src/mainboard/cwwk/Kconfig new file mode 100644 index 000000000000..47c80d9879b7 --- /dev/null +++ b/src/mainboard/cwwk/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if VENDOR_CWWK + +choice + prompt "Mainboard model" + +source "src/mainboard/cwwk/*/Kconfig.name" + +endchoice + +source "src/mainboard/cwwk/*/Kconfig" + +config MAINBOARD_VENDOR + default "CWWK" + +endif # VENDOR_CWWK diff --git a/src/mainboard/cwwk/Kconfig.name b/src/mainboard/cwwk/Kconfig.name new file mode 100644 index 000000000000..51e3dd4601e9 --- /dev/null +++ b/src/mainboard/cwwk/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config VENDOR_CWWK + bool "CWWK" diff --git a/src/mainboard/cwwk/adl/Kconfig b/src/mainboard/cwwk/adl/Kconfig new file mode 100644 index 000000000000..c6c0aa3187e8 --- /dev/null +++ b/src/mainboard/cwwk/adl/Kconfig @@ -0,0 +1,28 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_CWWK_ADL_N + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_UART_8250IO + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_ALDERLAKE_PCH_N + select SUPERIO_ITE_IT8613E + +config MAINBOARD_DIR + default "cwwk/adl" + +config MAINBOARD_PART_NUMBER + default "CW-AL-4L-V1.0" + +config DIMM_MAX + default 2 + +config NO_POST + default y + +endif diff --git a/src/mainboard/cwwk/adl/Kconfig.name b/src/mainboard/cwwk/adl/Kconfig.name new file mode 100644 index 000000000000..7faa8e483113 --- /dev/null +++ b/src/mainboard/cwwk/adl/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_CWWK_ADL_N + bool "CW-ADL-4L-V1.0" diff --git a/src/mainboard/cwwk/adl/Makefile.mk b/src/mainboard/cwwk/adl/Makefile.mk new file mode 100644 index 000000000000..89eb072db256 --- /dev/null +++ b/src/mainboard/cwwk/adl/Makefile.mk @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/cwwk/adl/board_info.txt b/src/mainboard/cwwk/adl/board_info.txt new file mode 100644 index 000000000000..b53863c87cb2 --- /dev/null +++ b/src/mainboard/cwwk/adl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: CWWK +Board name: CW-ADL-4L-V1.0 +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/cwwk/adl/bootblock.c b/src/mainboard/cwwk/adl/bootblock.c new file mode 100644 index 000000000000..f19b3839070a --- /dev/null +++ b/src/mainboard/cwwk/adl/bootblock.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/cwwk/adl/data.vbt b/src/mainboard/cwwk/adl/data.vbt Binary files differnew file mode 100644 index 000000000000..2a6c2076e344 --- /dev/null +++ b/src/mainboard/cwwk/adl/data.vbt diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb new file mode 100644 index 000000000000..15ec3b2c1bb8 --- /dev/null +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -0,0 +1,80 @@ +chip soc/intel/alderlake + + register "s0ix_enable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader + + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 4, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, + .pcie_rp_aspm = ASPM_DISABLE, + }" + + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + + # Enable EDP in PortA + register "ddi_portA_config" = "1" + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref crashlog off end + device ref xhci on end + device ref shared_sram on end + device ref pcie_rp1 on end + device ref pcie_rp7 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end + device ref pcie_rp12 on end # M.2 E key port + device ref pch_espi on + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 0x4 + irq 0xf0 = 0x1 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + device pnp 2e.a off end # CIR + end + end + device ref hda on end + device ref smbus on end + end +end diff --git a/src/mainboard/cwwk/adl/dsdt.asl b/src/mainboard/cwwk/adl/dsdt.asl new file mode 100644 index 000000000000..132ed3758138 --- /dev/null +++ b/src/mainboard/cwwk/adl/dsdt.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/cwwk/adl/gpio.h b/src/mainboard/cwwk/adl/gpio.h new file mode 100644 index 000000000000..fc3d7ead1526 --- /dev/null +++ b/src/mainboard/cwwk/adl/gpio.h @@ -0,0 +1,297 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), /* GPIO */ + PAD_NC(GPP_B4, NONE), /* GPIO */ + PAD_NC(GPP_B5, NONE), /* GPIO */ + PAD_NC(GPP_B6, NONE), /* GPIO */ + PAD_NC(GPP_B7, NONE), /* GPIO */ + PAD_NC(GPP_B8, NONE), /* GPIO */ + PAD_NC(GPP_B9, NONE), /* GPIO */ + PAD_NC(GPP_B10, NONE), /* GPIO */ + //PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B15, NONE), /* GPIO */ + PAD_NC(GPP_B16, NONE), /* GPIO */ + PAD_NC(GPP_B17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_B19, NONE), /* GPIO */ + PAD_NC(GPP_B20, NONE), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_NC(GPP_B22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), /* GSPI1_CLK_LOOPBK */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T0, NONE), /* GPIO */ + PAD_NC(GPP_T1, NONE), /* GPIO */ + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_EN */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_MODE */ + PAD_NC(GPP_T4, NONE), /* GPIO */ + PAD_NC(GPP_T5, NONE), /* GPIO */ + PAD_NC(GPP_T6, NONE), /* GPIO */ + PAD_NC(GPP_T7, NONE), /* GPIO */ + PAD_NC(GPP_T8, NONE), /* GPIO */ + PAD_NC(GPP_T9, NONE), /* GPIO */ + PAD_NC(GPP_T10, NONE), /* GPIO */ + PAD_NC(GPP_T11, NONE), /* GPIO */ + PAD_NC(GPP_T12, NONE), /* GPIO */ + PAD_NC(GPP_T13, NONE), /* GPIO */ + PAD_NC(GPP_T14, NONE), /* GPIO */ + PAD_NC(GPP_T15, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A6, UP_20K, DEEP, NF1), /* ESPI_ALERT1# */ + PAD_CFG_GPO(GPP_A7, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_NC(GPP_A11, NONE), /* GPIO */ + PAD_NC(GPP_A12, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPIO */ + PAD_NC(GPP_A14, NONE), /* GPIO */ + PAD_NC(GPP_A15, NONE), /* GPIO */ + PAD_NC(GPP_A16, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_A21, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* ESPI_CS1# */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_ESPI_CLK_LOOPBK */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), /* GPIO */ + PAD_NC(GPP_S1, NONE), /* GPIO */ + PAD_NC(GPP_S2, NONE), /* GPIO */ + PAD_NC(GPP_S3, NONE), /* GPIO */ + PAD_NC(GPP_S4, NONE), /* GPIO */ + PAD_NC(GPP_S5, NONE), /* GPIO */ + PAD_NC(GPP_S6, NONE), /* GPIO */ + PAD_NC(GPP_S7, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), /* GPIO */ + PAD_NC(GPP_I1, NONE), /* GPIO */ + PAD_NC(GPP_I2, NONE), /* GPIO */ + PAD_NC(GPP_I3, NONE), /* GPIO */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_NC(GPP_I5, NONE), /* GPIO */ + PAD_NC(GPP_I6, NONE), /* GPIO */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA0 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA1 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA2 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA3 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA4 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA5 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA6 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA7 */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */ + PAD_NC(GPP_I19, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H2, 1, RSMRST), /* GPIO */ + PAD_NC(GPP_H3, NONE), /* GPIO */ + PAD_NC(GPP_H4, NONE), /* GPIO */ + PAD_NC(GPP_H5, NONE), /* GPIO */ + PAD_NC(GPP_H6, NONE), /* GPIO */ + PAD_NC(GPP_H7, NONE), /* GPIO */ + PAD_NC(GPP_H8, NONE), /* GPIO */ + PAD_NC(GPP_H9, NONE), /* GPIO */ + PAD_NC(GPP_H10, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + PAD_NC(GPP_H12, NONE), /* GPIO */ + PAD_NC(GPP_H13, NONE), /* GPIO */ + PAD_NC(GPP_H14, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_NC(GPP_H16, NONE), /* GPIO */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_H20, NONE), /* GPIO */ + PAD_NC(GPP_H21, NONE), /* GPIO */ + PAD_NC(GPP_H22, NONE), /* GPIO */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, PLTRST, OFF, ACPI), /* GPIO */ + PAD_NC(GPP_D2, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_NC(GPP_D4, NONE), /* GPIO */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ + PAD_NC(GPP_D13, NONE), /* GPIO */ + PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_D17, NONE), /* GPIO */ + PAD_NC(GPP_D18, NONE), /* GPIO */ + PAD_NC(GPP_D19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_GSPI2_CLK_LOOPBK */ + + /* ------- GPIO Group vGPIO ------- */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* ACPRESENT */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* LAN_WAKE# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), /* GPIO */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), /* GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), /* GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), /* GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), /* GPD_WAKEB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), /* GPD_DRAM_RESETB */ + + /* ------- GPIO Group PCIe vGPIO ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_NC(GPP_C8, NONE), /* GPIO */ + PAD_NC(GPP_C9, NONE), /* GPIO */ + PAD_NC(GPP_C10, NONE), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_NC(GPP_C12, NONE), /* GPIO */ + PAD_NC(GPP_C13, NONE), /* GPIO */ + PAD_NC(GPP_C14, NONE), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_NC(GPP_C19, NONE), /* GPIO */ + PAD_NC(GPP_C20, NONE), /* GPIO */ + PAD_NC(GPP_C21, NONE), /* GPIO */ + PAD_NC(GPP_C22, NONE), /* GPIO */ + PAD_NC(GPP_C23, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), /* MODEM_CLKREQ */ + PAD_NC(GPP_F6, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), /* GPIO */ + PAD_NC(GPP_F8, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* BOOTMPC */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_F11, NONE), /* GPIO */ + PAD_NC(GPP_F12, NONE), /* GPIO */ + PAD_NC(GPP_F13, NONE), /* GPIO */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_NC(GPP_F15, NONE), /* GPIO */ + PAD_NC(GPP_F16, NONE), /* GPIO */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* Reserved */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_NC(GPP_F23, NONE), /* GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Group GPP_HVCMOS ------- */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), /* GPIO */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), /* GPIO */ + PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), /* GPIO */ + PAD_NC(GPP_E7, NONE), /* GPIO */ + PAD_NC(GPP_E8, NONE), /* GPIO */ + PAD_NC(GPP_E9, NONE), /* GPIO */ + PAD_NC(GPP_E10, NONE), /* GPIO */ + PAD_NC(GPP_E11, NONE), /* GPIO */ + PAD_NC(GPP_E12, NONE), /* GPIO */ + PAD_NC(GPP_E13, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E16, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_E17, NONE), /* GPIO */ + PAD_CFG_NF(GPP_E18, NATIVE, DEEP, NF5), /* BSSB_LS0_RX */ + PAD_CFG_NF(GPP_E19, NATIVE, DEEP, NF5), /* BSSB_LS0_TX */ + PAD_CFG_GPO(GPP_E20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_E21, 0, PLTRST), /* GPIO */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), /* GPIO */ + PAD_NC(GPP_R6, NONE), /* GPIO */ + PAD_NC(GPP_R7, NONE), /* GPIO */ +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/cwwk/adl/mainboard.c b/src/mainboard/cwwk/adl/mainboard.c new file mode 100644 index 000000000000..b15d01728b6e --- /dev/null +++ b/src/mainboard/cwwk/adl/mainboard.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> +#include "gpio.h" + +static void mainboard_init(void *chip_info) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/cwwk/adl/romstage_fsp_params.c b/src/mainboard/cwwk/adl/romstage_fsp_params.c new file mode 100644 index 000000000000..ac50fb096544 --- /dev/null +++ b/src/mainboard/cwwk/adl/romstage_fsp_params.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fsp/api.h> +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + }; + + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + }, + }; + + const bool half_populated = false; + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); +} diff --git a/src/mainboard/dell/e7240/Kconfig b/src/mainboard/dell/e7240/Kconfig new file mode 100644 index 000000000000..4f24cf93ed3a --- /dev/null +++ b/src/mainboard/dell/e7240/Kconfig @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_DELL_LATITUDE_E7240 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_DELL_MEC5035 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + default "dell/e7240" + +config MAINBOARD_PART_NUMBER + default "Latitude E7240" + +config VGA_BIOS_ID + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + default 1 + +endif diff --git a/src/mainboard/dell/e7240/Kconfig.name b/src/mainboard/dell/e7240/Kconfig.name new file mode 100644 index 000000000000..499f783a101d --- /dev/null +++ b/src/mainboard/dell/e7240/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_LATITUDE_E7240 + bool "Latitude E7240" diff --git a/src/mainboard/dell/e7240/Makefile.mk b/src/mainboard/dell/e7240/Makefile.mk new file mode 100644 index 000000000000..c3dd6194218d --- /dev/null +++ b/src/mainboard/dell/e7240/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/dell/e7240/acpi/ec.asl b/src/mainboard/dell/e7240/acpi/ec.asl new file mode 100644 index 000000000000..24915c22ef27 --- /dev/null +++ b/src/mainboard/dell/e7240/acpi/ec.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* FIXME: not working yet */ +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 39) + + Method (_Q66, 0, NotSerialized) + { + Store ("EC: _Q66", Debug) + } +} diff --git a/src/mainboard/dell/e7240/acpi/platform.asl b/src/mainboard/dell/e7240/acpi/platform.asl new file mode 100644 index 000000000000..2d24bbd9b9a8 --- /dev/null +++ b/src/mainboard/dell/e7240/acpi/platform.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/dell/e7240/acpi/superio.asl b/src/mainboard/dell/e7240/acpi/superio.asl new file mode 100644 index 000000000000..55b1db5b1137 --- /dev/null +++ b/src/mainboard/dell/e7240/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/e7240/board_info.txt b/src/mainboard/dell/e7240/board_info.txt new file mode 100644 index 000000000000..accdf52791d6 --- /dev/null +++ b/src/mainboard/dell/e7240/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://www.dell.com/support/home/en-us/product-support/product/latitude-e7240-ultrabook/docs +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/dell/e7240/bootblock.c b/src/mainboard/dell/e7240/bootblock.c new file mode 100644 index 000000000000..2f6090a40fcc --- /dev/null +++ b/src/mainboard/dell/e7240/bootblock.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + mec5035_early_init(); +} diff --git a/src/mainboard/dell/e7240/devicetree.cb b/src/mainboard/dell/e7240/devicetree.cb new file mode 100644 index 000000000000..c408383c7099 --- /dev/null +++ b/src/mainboard/dell/e7240/devicetree.cb @@ -0,0 +1,82 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell + register "ec_present" = "true" + + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + + device domain 0x0 on + ops haswell_pci_domain_ops + subsystemid 0x1028 0x05ca inherit + + device pci 00.0 on end # Host bridge + device pci 02.0 on # Internal graphics VGA controller + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "0" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 1, + .backlight_pwm_hz = 200, + }" + end + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "alt_gp_smi_en" = "0x00002000" + register "gpe0_en_1" = "0x00000100" + register "gpe0_en_2" = "0x00000080" + register "gpe0_en_4" = "0x00000042" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4, WLAN + device pci 1c.4 on end # PCIe Port #5, SD/MMC Card Reader + # PCIe Port #6 Can be muxed between PCIe and SATA + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x005c0921" + register "gen3_dec" = "0x003c07e1" + # Enable 0x910 and 0x911 for early init and EC driver + register "gen4_dec" = "0x007c0901" + + chip ec/dell/mec5035 + device pnp ff.0 on end + end + end + device pci 1f.2 on # SATA Controller (AHCI) + # 0(eSATA on dock), 1(mSATA near the fan), 3(mSATA near WLAN) + register "sata_port_map" = "0x0b" + end + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/dell/e7240/dsdt.asl b/src/mainboard/dell/e7240/dsdt.asl new file mode 100644 index 000000000000..b1d4c7912780 --- /dev/null +++ b/src/mainboard/dell/e7240/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/e7240/gma-mainboard.ads b/src/mainboard/dell/e7240/gma-mainboard.ads new file mode 100644 index 000000000000..cdc7f1868015 --- /dev/null +++ b/src/mainboard/dell/e7240/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, + HDMI1, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/e7240/gpio.c b/src/mainboard/dell/e7240/gpio.c new file mode 100644 index 000000000000..166502505f4d --- /dev/null +++ b/src/mainboard/dell/e7240/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { + [0] = LP_GPIO_OUT_LOW, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [3] = LP_GPIO_OUT_LOW, + [4] = LP_GPIO_NATIVE, + [5] = LP_GPIO_NATIVE, + [6] = LP_GPIO_NATIVE, + [7] = LP_GPIO_NATIVE, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [10] = LP_GPIO_OUT_LOW, + [11] = LP_GPIO_NATIVE, + [12] = LP_GPIO_NATIVE, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [14] = LP_GPIO_OUT_LOW, + [15] = LP_GPIO_OUT_LOW, + [16] = LP_GPIO_OUT_HIGH, + [17] = LP_GPIO_OUT_LOW, + [18] = LP_GPIO_NATIVE, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_NATIVE, + [23] = LP_GPIO_NATIVE, + [24] = LP_GPIO_OUT_LOW, + [25] = LP_GPIO_OUT_LOW, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_LOW, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = LP_GPIO_OUT_LOW, + [37] = LP_GPIO_NATIVE, + [38] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [46] = LP_GPIO_OUT_LOW, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_LOW, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_LOW, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .pirq = GPIO_PIRQ_APIC_ROUTE }, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_HIGH, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_LOW, + [61] = LP_GPIO_NATIVE, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [66] = LP_GPIO_OUT_LOW, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = LP_GPIO_OUT_LOW, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = LP_GPIO_OUT_HIGH, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [79] = LP_GPIO_OUT_LOW, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [87] = LP_GPIO_OUT_LOW, + [88] = LP_GPIO_OUT_LOW, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [93] = LP_GPIO_OUT_LOW, + [94] = LP_GPIO_OUT_LOW, + LP_GPIO_END +}; diff --git a/src/mainboard/dell/e7240/hda_verb.c b/src/mainboard/dell/e7240/hda_verb.c new file mode 100644 index 000000000000..b052e15ead80 --- /dev/null +++ b/src/mainboard/dell/e7240/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0292, /* Codec Vendor / Device ID: Realtek */ + 0x102805ca, /* Subsystem ID */ + 12, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x102805ca), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0221401f), + AZALIA_PIN_CFG(0, 0x16, 0x01014020), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, 0x01a19030), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x40700001), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/e7240/romstage.c b/src/mainboard/dell/e7240/romstage.c new file mode 100644 index 000000000000..6b2cb7a80c70 --- /dev/null +++ b/src/mainboard/dell/e7240/romstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, /* dock left */ + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, /* right, EHCI debug */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, /* WLAN + BT */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* USH / Smart Card */ + { 0x0110, 1, 2, USB_PORT_BACK_PANEL }, /* back right, dock back */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_DOCK }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* touchscreen */ +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 1 }, /* right */ + { 1, 0 }, /* back left */ + { 1, 2 }, /* back right, dock back */ + { 1, USB_OC_PIN_SKIP } +}; diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads index 173f2f1d0dc2..7d9506163c70 100644 --- a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads +++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads @@ -9,9 +9,10 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (DP1, - DP2, + (DP2, DP3, + HDMI2, + HDMI3, Analog, others => Disabled); diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c index df43ade3e67c..2f3ac8945128 100644 --- a/src/mainboard/dell/optiplex_9020/hda_verb.c +++ b/src/mainboard/dell/optiplex_9020/hda_verb.c @@ -9,17 +9,17 @@ const u32 cim_verb_data[] = { 13, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x102805a5), AZALIA_PIN_CFG(0, 0x12, 0x4008c000), - AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x0221401f), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a13040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x02a19030), AZALIA_PIN_CFG(0, 0x1b, 0x01014020), AZALIA_PIN_CFG(0, 0x1d, 0x40400001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig new file mode 100644 index 000000000000..be9ac37845ab --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig @@ -0,0 +1,49 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_SNB_IVB_LATITUDE_COMMON + def_bool n + select EC_ACPI + select EC_DELL_MEC5035 + select GFX_GMA_PANEL_1_ON_LVDS + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config BOARD_DELL_LATITUDE_E6430 + select BOARD_DELL_SNB_IVB_LATITUDE_COMMON + select BOARD_ROMSIZE_KB_12288 + select MAINBOARD_USES_IFD_GBE_REGION + select SOUTHBRIDGE_INTEL_C216 + +if BOARD_DELL_SNB_IVB_LATITUDE_COMMON + +config DRAM_RESET_GATE_GPIO + default 60 + +config MAINBOARD_DIR + default "dell/snb_ivb_latitude" + +config MAINBOARD_PART_NUMBER + default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430 + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config USBDEBUG_HCD_INDEX + default 2 + +config VARIANT_DIR + default "e6430" if BOARD_DELL_LATITUDE_E6430 + +config VGA_BIOS_ID + default "8086,0166" + +endif diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name new file mode 100644 index 000000000000..183252630a27 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_DELL_LATITUDE_E6430 + bool "Latitude E6430" diff --git a/src/mainboard/dell/snb_ivb_latitude/Makefile.mk b/src/mainboard/dell/snb_ivb_latitude/Makefile.mk new file mode 100644 index 000000000000..299fbb9bad8a --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += variants/$(VARIANT_DIR)/early_init.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c + +romstage-y += variants/$(VARIANT_DIR)/early_init.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl b/src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl new file mode 100644 index 000000000000..0d429410a911 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/acpi/ec.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 16) +/* FIXME: EC support */ +} diff --git a/src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl b/src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl new file mode 100644 index 000000000000..2d24bbd9b9a8 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/acpi/platform.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + /* FIXME: EC support */ + Return(Package() {0, 0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl b/src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl new file mode 100644 index 000000000000..55b1db5b1137 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/dell/snb_ivb_latitude/board_info.txt b/src/mainboard/dell/snb_ivb_latitude/board_info.txt new file mode 100644 index 000000000000..4601a4aabad1 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2012 diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default new file mode 100644 index 000000000000..2a5b30f2b70b --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default @@ -0,0 +1,9 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable +bluetooth=Enable +wwan=Enable +wlan=Enable +sata_mode=AHCI +me_state=Normal diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.layout b/src/mainboard/dell/snb_ivb_latitude/cmos.layout new file mode 100644 index 000000000000..9561c4e679e9 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/cmos.layout @@ -0,0 +1,83 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 9 sata_mode + +# coreboot config options: EC +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 wlan + +# coreboot config options: ME +424 1 e 14 me_state +425 2 h 0 me_state_prev + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +14 0 Normal +14 1 Disabled + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/dell/snb_ivb_latitude/devicetree.cb b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb new file mode 100644 index 000000000000..f00922b8c729 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/devicetree.cb @@ -0,0 +1,56 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + + device domain 0x0 on + device ref igd on + register "gfx" = "GMA_STATIC_DISPLAYS(1)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2300" + register "gpu_panel_power_backlight_on_delay" = "2300" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "400" + register "gpu_panel_power_up_delay" = "400" + end + + chip southbridge/intel/bd82x6x # Intel 6/7 Series PCH + register "docking_supported" = "1" + + register "gpi0_routing" = "2" + register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + + device ref gbe on end + device ref ehci2 on end + device ref hda on end + device ref pcie_rp1 on end # WWAN Slot + device ref pcie_rp2 on end # SLAN Slot + device ref pcie_rp3 on end # ExpressCard + device ref pcie_rp4 on end # E-Module (optical bay) + device ref pcie_rp5 on end # Extra Half Mini PCIe slot + device ref pcie_rp6 on end # SD/MMC Card Reader + device ref ehci1 on end + device ref lpc on + register "gen1_dec" = "0x007c0681" + register "gen2_dec" = "0x005c0921" + register "gen3_dec" = "0x003c07e1" + register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC + + chip ec/dell/mec5035 + device pnp ff.0 on end + end + end + device ref sata1 on + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + end + end + end +end diff --git a/src/mainboard/dell/snb_ivb_latitude/dsdt.asl b/src/mainboard/dell/snb_ivb_latitude/dsdt.asl new file mode 100644 index 000000000000..9a7d54b963fd --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads b/src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads new file mode 100644 index 000000000000..ea6dfb06edd8 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + ( + HDMI1, -- mainboard HDMI + HDMI2, -- dock DVI + HDMI3, -- dock DVI + DP2, -- dock DP + DP3, -- dock DP + Analog, -- mainboard/dock VGA (muxed) + LVDS, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/dell/snb_ivb_latitude/mainboard.c b/src/mainboard/dell/snb_ivb_latitude/mainboard.c new file mode 100644 index 000000000000..1d13a8459bbc --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/mainboard.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <pc80/keyboard.h> + +static void mainboard_enable(struct device *dev) +{ + + /* FIXME: fix these values. */ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); + pc_keyboard_init(NO_AUX_DEVICE); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt Binary files differnew file mode 100644 index 000000000000..ec5588481153 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/data.vbt diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c new file mode 100644 index 000000000000..b4fd22d3d5f9 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/early_init.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <ec/dell/mec5035/mec5035.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 1, 1, 3 }, + { 1, 1, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 2, 6 }, + { 1, 2, 6 }, +}; + +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN + | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); + mec5035_early_init(); +} diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c new file mode 100644 index 000000000000..777570765a5f --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/gpio.c @@ -0,0 +1,192 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_LOW, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c new file mode 100644 index 000000000000..f069813b67d0 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/hda_verb.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x111d76df, /* Codec Vendor / Device ID: IDT */ + 0x10280534, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x10280534), + AZALIA_PIN_CFG(0, 0x0a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x0b, 0x0321101f), + AZALIA_PIN_CFG(0, 0x0c, 0x400000f0), + AZALIA_PIN_CFG(0, 0x0d, 0x90170110), + AZALIA_PIN_CFG(0, 0x0e, 0x23011050), + AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e), + AZALIA_PIN_CFG(0, 0x10, 0x400000f3), + AZALIA_PIN_CFG(0, 0x11, 0xd5a30130), + AZALIA_PIN_CFG(0, 0x1f, 0x400000f0), + AZALIA_PIN_CFG(0, 0x20, 0x400000f0), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x18560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb new file mode 100644 index 000000000000..55df5eba1d84 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6430/overridetree.cb @@ -0,0 +1,20 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/sandybridge + device domain 0 on + subsystemid 0x1028 0x0534 inherit + + device ref igd on + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_pch_backlight" = "0x13121312" + end + + chip southbridge/intel/bd82x6x + device ref xhci on + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" + end + end + end +end diff --git a/src/mainboard/dell/snb_ivb_workstations/early_init.c b/src/mainboard/dell/snb_ivb_workstations/early_init.c index 4a381df93792..9ddbaf9924cd 100644 --- a/src/mainboard/dell/snb_ivb_workstations/early_init.c +++ b/src/mainboard/dell/snb_ivb_workstations/early_init.c @@ -9,23 +9,6 @@ #include <baseboard/sch5545_ec.h> -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 6, 0 }, - { 1, 6, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 1, 2 }, - { 1, 1, 2 }, - { 1, 6, 3 }, - { 1, 6, 3 }, - { 1, 6, 4 }, - { 1, 6, 4 }, - { 1, 6, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 6, 6 }, -}; - void bootblock_mainboard_early_init(void) { /* diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 28c8d0577c50..2ba11b436cad 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -30,6 +30,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x08040201" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 6, 0 }, + { 1, 6, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 1, 1, 2 }, + { 1, 6, 3 }, + { 1, 6, 3 }, + { 1, 6, 4 }, + { 1, 6, 4 }, + { 1, 6, 5 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 6, 6 } + }" device ref xhci on end device ref mei1 off end device ref mei2 off end diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c index eab4ba9053f2..8035f47c1332 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c +++ b/src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c @@ -9,15 +9,15 @@ const u32 cim_verb_data[] = { 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x1028052c), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x99130110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x02a19830), AZALIA_PIN_CFG(0, 0x19, 0x01a19840), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x01014020), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221402f), 0x80862806, /* Codec Vendor / Device ID: Intel */ diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c index 983b7e4f3963..6e60d548ac23 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c +++ b/src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/hda_verb.c @@ -9,15 +9,15 @@ const u32 cim_verb_data[] = { 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x1028053a), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x99130110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x02a19830), AZALIA_PIN_CFG(0, 0x19, 0x01a19840), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x01014020), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221402f), 0x80862806, /* Codec Vendor / Device ID: Intel */ diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 5f596b87c00d..1c2ab86aaff6 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -3,6 +3,7 @@ # ugly to put it in here, but unavoidable config SEPARATE_ROMSTAGE default n if BOARD_EMULATION_QEMU_RISCV + default n if BOARD_EMULATION_QEMU_SBSA if VENDOR_EMULATION diff --git a/src/mainboard/emulation/qemu-riscv/Kconfig b/src/mainboard/emulation/qemu-riscv/Kconfig index 94f9e56c5ad9..27b1b5812788 100644 --- a/src/mainboard/emulation/qemu-riscv/Kconfig +++ b/src/mainboard/emulation/qemu-riscv/Kconfig @@ -23,6 +23,7 @@ if BOARD_EMULATION_QEMU_RISCV config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_32768 + select FLATTENED_DEVICE_TREE select MISSING_BOARD_RESET select DRIVERS_UART_8250MEM select RISCV_HAS_OPENSBI diff --git a/src/mainboard/emulation/qemu-riscv/cbmem.c b/src/mainboard/emulation/qemu-riscv/cbmem.c index e4d21ccb806f..8c37957dd86f 100644 --- a/src/mainboard/emulation/qemu-riscv/cbmem.c +++ b/src/mainboard/emulation/qemu-riscv/cbmem.c @@ -3,10 +3,17 @@ #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> +#include <device_tree.h> +#include <mcall.h> uintptr_t cbmem_top_chipset(void) { - //TODO get memory range from QEMUs FDT + uint64_t top; + + top = fdt_get_memory_top((void *)HLS()->fdt); + if (top) + return MIN(top, (uint64_t)4 * GiB - 1); + size_t dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB); return (uintptr_t)_dram + dram_mb_detected * MiB; } diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig b/src/mainboard/emulation/qemu-sbsa/Kconfig new file mode 100644 index 000000000000..a28ae6229001 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Kconfig @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_EMULATION_QEMU_SBSA + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_ARMV8_64 + select ARCH_VERSTAGE_ARMV8_64 + select ARCH_ROMSTAGE_ARMV8_64 + select ARCH_RAMSTAGE_ARMV8_64 + select ARM64_USE_ARCH_TIMER + select BOARD_ROMSIZE_KB_32768 + select BOOTBLOCK_CUSTOM + select BOOT_DEVICE_NOT_SPI_FLASH + select DRIVERS_UART_PL011 + select FLATTENED_DEVICE_TREE + select HAVE_LINEAR_FRAMEBUFFER + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MISSING_BOARD_RESET + select PCI + select HAVE_ACPI_TABLES + select ACPI_GTDT + select ACPI_COMMON_MADT_GICC_V3 + select GENERATE_SMBIOS_TABLES + +config ARM64_CURRENT_EL + default 2 + +config ECAM_MMCONF_BASE_ADDRESS + default 0xf0000000 + +config ECAM_MMCONF_BUS_NUMBER + default 256 + +config FMDFILE + default "src/mainboard/emulation/qemu-sbsa/flash.fmd" + +config MAINBOARD_DIR + default "emulation/qemu-sbsa" + +config MAINBOARD_PART_NUMBER + default "QEMU sbsa" + +config MAX_CPUS + default 128 + +config MAINBOARD_VENDOR + default "QEMU" + +config DRAM_SIZE_MB + int + default 8388608 # The maximum dram size is 8192GiB. + +endif # BOARD_EMULATION_QEMU_SBSA diff --git a/src/mainboard/emulation/qemu-sbsa/Kconfig.name b/src/mainboard/emulation/qemu-sbsa/Kconfig.name new file mode 100644 index 000000000000..6fefa0c0a199 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Kconfig.name @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_EMULATION_QEMU_SBSA + bool "QEMU sbsa" diff --git a/src/mainboard/emulation/qemu-sbsa/Makefile.mk b/src/mainboard/emulation/qemu-sbsa/Makefile.mk new file mode 100644 index 000000000000..e3855bae03cc --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/Makefile.mk @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c + +romstage-y += cbmem.c + +bootblock-y += media.c +romstage-y += media.c +ramstage-y += media.c + +bootblock-y += mmio.c +romstage-y += mmio.c +ramstage-y += mmio.c + +ramstage-y += acpi.c + +bootblock-y += bootblock_custom.S + +CPPFLAGS_common += -mcmodel=large -I$(src)/mainboard/$(MAINBOARDDIR)/include + +build_complete:: + @printf "Truncating coreboot.rom to 256M\n" + truncate -s 256M $(obj)/coreboot.rom diff --git a/src/mainboard/emulation/qemu-sbsa/acpi.c b/src/mainboard/emulation/qemu-sbsa/acpi.c new file mode 100644 index 000000000000..1dae24277f12 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/acpi.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <mainboard/addressmap.h> + + +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->ARM_boot_arch |= ACPI_FADT_ARM_PSCI_COMPLIANT; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + return current; +} + +uintptr_t platform_get_gicd_base(void) +{ + return SBSA_GIC_DIST; +} + +uintptr_t platform_get_gicr_base(void) +{ + return SBSA_GIC_REDIST; +} + +#define SEC_EL1_TIMER_GISV 0x1d +#define NONSEC_EL1_TIMER_GSIV 0x1e +#define VIRTUAL_TIMER_GSIV 0x1b +#define NONSEC_EL2_TIMER_GSIV 0x1a + +#define SBSA_TIMER_FLAGS (ACPI_GTDT_INTERRUPT_POLARITY | ACPI_GTDT_ALWAYS_ON) + +void acpi_soc_fill_gtdt(acpi_gtdt_t *gtdt) +{ + /* This value is optional if the system implements EL3 (Security + Extensions). If not provided, this field must be 0xFFFFFFFFFFFFFFFF. */ + gtdt->counter_block_address = UINT64_MAX; + gtdt->secure_el1_interrupt = SEC_EL1_TIMER_GISV; + gtdt->secure_el1_flags = SBSA_TIMER_FLAGS; + gtdt->non_secure_el1_interrupt = NONSEC_EL1_TIMER_GSIV; + gtdt->non_secure_el1_flags = SBSA_TIMER_FLAGS; + gtdt->virtual_timer_interrupt = VIRTUAL_TIMER_GSIV; + gtdt->virtual_timer_flags = SBSA_TIMER_FLAGS; + gtdt->non_secure_el2_interrupt = NONSEC_EL2_TIMER_GSIV; + gtdt->non_secure_el2_flags = SBSA_TIMER_FLAGS; + /* This value is optional if the system implements EL3 + (Security Extensions). If not provided, this field must be + 0xFFFFFFFFFFFFFFF. */ + gtdt->counter_read_block_address = UINT64_MAX; +} + +#define WD_TIMER_GSIV 0x30 + +unsigned long acpi_soc_gtdt_add_timers(uint32_t *count, unsigned long current) +{ + (*count)++; + return acpi_gtdt_add_watchdog(current, SBSA_GWDT_REFRESH, SBSA_GWDT_CONTROL, + WD_TIMER_GSIV, 0); +} diff --git a/src/mainboard/emulation/qemu-sbsa/board_info.txt b/src/mainboard/emulation/qemu-sbsa/board_info.txt new file mode 100644 index 000000000000..16a92be4b3b3 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/board_info.txt @@ -0,0 +1,3 @@ +Board name: QEMU sbsa +Category: emulation +Board URL: https://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock.c b/src/mainboard/emulation/qemu-sbsa/bootblock.c new file mode 100644 index 000000000000..b38df6ec7154 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/bootblock.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmu.h> +#include <bootblock_common.h> +#include <symbols.h> + +void bootblock_mainboard_init(void) +{ + mmu_init(); + + /* Everything below DRAM is device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram, MA_DEV | MA_RW); + /* Set a dummy value for DRAM. ramstage should update the mapping. */ + mmu_config_range(_dram, ((size_t) CONFIG_DRAM_SIZE_MB) * MiB, MA_MEM | MA_RW); + + mmu_config_range(_ttb, REGION_SIZE(ttb), MA_MEM | MA_S | MA_RW); + mmu_config_range(_bootblock, REGION_SIZE(bootblock), MA_MEM | MA_S | MA_RW); + mmu_config_range(_ramstage, REGION_SIZE(ramstage), MA_MEM | MA_S | MA_RW); + mmu_config_range((void *)CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH, + MA_DEV | MA_RW); + mmu_enable(); +} diff --git a/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S b/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S new file mode 100644 index 000000000000..c05afed5ff29 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/bootblock_custom.S @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Early initialization code for sbsa-ref machine + */ + +#include <arch/asm.h> + +ENTRY(_start) + + /* TF-A arg which contains a pointer to fdt */ + ldr x1, =_fdt_pointer + str x0, [x1] + + /* Setup CPU. */ + /* bl arm64_init_cpu */ + + /* ==== stack init from arm64_init_cpu ==== */ + + msr SPSel, #0 /* use SP_EL0 */ + + ldr x2, =0xdeadbeefdeadbeef + ldr x0, =_stack + ldr x1, =_estack +1: + stp x2, x2, [x0], #16 + cmp x0, x1 + bne 1b + + sub sp, x0, #16 + + /* ==== END ==== */ + + /* Get code positions. */ + ldr x1, =_flash + ldr x0, =_bootblock + + /* Calculate bootblock size. */ + ldr x2, =_ebootblock + sub x2, x2, x0 + + /* Call memcpy in arch/arm64/memcpy.S */ + bl memcpy + dmb sy + + /* Calculate relocation offset between bootblock in flash and in DRAM. */ + ldr x0, =_flash + ldr x1, =_bootblock + sub x1, x1, x0 + + /* Jump to main() in DRAM. */ + adr x0, main + add x0, x0, x1 + blr x0 +ENDPROC(_start) diff --git a/src/mainboard/emulation/qemu-sbsa/cbmem.c b/src/mainboard/emulation/qemu-sbsa/cbmem.c new file mode 100644 index 000000000000..ebc8a78da3d3 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/cbmem.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cbmem.h> +#include <symbols.h> +#include <device_tree.h> +#include <console/console.h> + +DECLARE_REGION(fdt_pointer) +uintptr_t cbmem_top_chipset(void) +{ + const uint64_t top = fdt_get_memory_top((void *) *((uintptr_t *)_fdt_pointer)); + + if (top == 0) { + /* corrupted FDT? */ + die("Could not find top of memory in FDT!"); + } + + printk(BIOS_DEBUG, "%s: 0x%llx\n", __func__, top); + return (uintptr_t)top; +} diff --git a/src/mainboard/emulation/qemu-sbsa/chip.h b/src/mainboard/emulation/qemu-sbsa/chip.h new file mode 100644 index 000000000000..98c6c71076a5 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/chip.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EMULATION_QEMU_SBSA_CHIP_H +#define MAINBOARD_EMULATION_QEMU_SBSA_CHIP_H + +#include <types.h> + +struct mainboard_emulation_qemu_sbsa_config { + uint32_t vgic_maintenance_interrupt; + uint32_t performance_interrupt_gsiv; +}; + +#endif diff --git a/src/mainboard/emulation/qemu-sbsa/devicetree.cb b/src/mainboard/emulation/qemu-sbsa/devicetree.cb new file mode 100644 index 000000000000..2e2cf3d01e30 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/devicetree.cb @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip mainboard/emulation/qemu-sbsa + register "vgic_maintenance_interrupt" = "0x19" + register "performance_interrupt_gsiv" = "0x17" + + device cpu_cluster 0 on ops qemu_aarch64_cpu_ops end + + device domain 0 on ops qemu_aarch64_pci_domain_ops + device pci 00.0 on end + end +end diff --git a/src/mainboard/emulation/qemu-sbsa/dsdt.asl b/src/mainboard/emulation/qemu-sbsa/dsdt.asl new file mode 100644 index 000000000000..8280cb743193 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/dsdt.asl @@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LINK_DEVICE(Uid, LinkName, Irq) \ + Device (LinkName) { \ + Name (_HID, EISAID("PNP0C0F")) \ + Name (_UID, Uid) \ + Name (_CRS, ResourceTemplate() { \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { Irq } \ + }) \ + } + +#define USB_PORT(PortName, Adr) \ + Device (PortName) { \ + Name (_ADR, Adr) \ + Name (_UPC, Package() { \ + 0xFF, \ + 0x00, \ + 0x00000000, \ + 0x00000000 \ + }) \ + Name (_PLD, Package() { \ + Buffer(0x10) { \ + 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \ + 0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 \ + } \ + }) \ + } + +#define PRT_ENTRY(Address, Pin, Link) \ + Package (4) { \ + Address, Pin, Link, Zero \ + } + +#define PRT_ENTRY_GROUP(Address, Link0, Link1, Link2, Link3) \ + PRT_ENTRY (Address, 0, Link0), \ + PRT_ENTRY (Address, 1, Link1), \ + PRT_ENTRY (Address, 2, Link2), \ + PRT_ENTRY (Address, 3, Link3) + +#include <acpi/acpi.h> +#include <mainboard/addressmap.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20230621 +) +{ + #include <acpi/dsdt_top.asl> + + Scope (_SB) { + // UART PL011 + Device (COM0) { + Name (_HID, "ARMH0011") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SBSA_UART_BASE, 0x00001000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 33 } + }) + } + + // AHCI Host Controller + Device (AHC0) { + Name (_HID, "LNRO001E") + Name (_CLS, Package (3) { + 0x01, + 0x06, + 0x01, + }) + Name (_CCA, 1) + Name (_CRS, ResourceTemplate() { + Memory32Fixed (ReadWrite, SBSA_AHCI_BASE, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 42 } + }) + } + + // USB EHCI Host Controller + Device (USB0) { + Name (_HID, "LNRO0D20") + Name (_CID, "PNP0D20") + Method (_CRS, 0x0, Serialized) { + Name (RBUF, ResourceTemplate() { + Memory32Fixed (ReadWrite, SBSA_EHCI_BASE, 0x00010000) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 43 } + }) + Return (RBUF) + } + + // Root Hub + Device (RHUB) { + Name (_ADR, 0x00000000) // Address of Root Hub should be 0 as per ACPI 5.0 spec + + // Ports connected to Root Hub + Device (HUB1) { + Name (_ADR, 0x00000001) + Name (_UPC, Package() { + 0x00, // Port is NOT connectable + 0xFF, // Don't care + 0x00000000, // Reserved 0 must be zero + 0x00000000 // Reserved 1 must be zero + }) + USB_PORT (PRT1, 0x00000001) // USB0_RHUB_HUB1_PRT1 + USB_PORT (PRT2, 0x00000002) // USB0_RHUB_HUB1_PRT2 + USB_PORT (PRT3, 0x00000003) // USB0_RHUB_HUB1_PRT3 + USB_PORT (PRT4, 0x00000004) // USB0_RHUB_HUB1_PRT4 + } // USB0_RHUB_HUB1 + } // USB0_RHUB + } // USB0 + + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_UID, "PCI0") + Name (_CCA, One) // Initially mark the PCI coherent (for JunoR1) + + Method (_CBA, 0, NotSerialized) { + return (SBSA_PCIE_ECAM_BASE) + } + + LINK_DEVICE (0, GSI0, 0x23) + LINK_DEVICE (1, GSI1, 0x24) + LINK_DEVICE (2, GSI2, 0x25) + LINK_DEVICE (3, GSI3, 0x26) + + Name (_PRT, Package () { + + // _PRT: PCI Routing Table + PRT_ENTRY_GROUP (0x0000FFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x0001FFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x0002FFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x0003FFFF, GSI3, GSI0, GSI1, GSI2), + PRT_ENTRY_GROUP (0x0004FFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x0005FFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x0006FFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x0007FFFF, GSI3, GSI0, GSI1, GSI2), + PRT_ENTRY_GROUP (0x0008FFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x0009FFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x000AFFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x000BFFFF, GSI3, GSI0, GSI1, GSI2), + PRT_ENTRY_GROUP (0x000CFFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x000DFFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x000EFFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x000FFFFF, GSI3, GSI0, GSI1, GSI2), + PRT_ENTRY_GROUP (0x0010FFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x0011FFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x0012FFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x0013FFFF, GSI3, GSI0, GSI1, GSI2), + PRT_ENTRY_GROUP (0x0014FFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x0015FFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x0016FFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x0017FFFF, GSI3, GSI0, GSI1, GSI2), + PRT_ENTRY_GROUP (0x0018FFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x0019FFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x001AFFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x001BFFFF, GSI3, GSI0, GSI1, GSI2), + PRT_ENTRY_GROUP (0x001CFFFF, GSI0, GSI1, GSI2, GSI3), + PRT_ENTRY_GROUP (0x001DFFFF, GSI1, GSI2, GSI3, GSI0), + PRT_ENTRY_GROUP (0x001EFFFF, GSI2, GSI3, GSI0, GSI1), + PRT_ENTRY_GROUP (0x001FFFFF, GSI3, GSI0, GSI1, GSI2), + }) + + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SBSA_PCIE_MMIO_BASE, // Min Base Address + SBSA_PCIE_MMIO_LIMIT, // Max Base Address + 0, // Translate + SBSA_PCIE_MMIO_SIZE // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, PosDecode, + MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, // Granularity + SBSA_PCIE_MMIO_HIGH_BASE, // Min Base Address + SBSA_PCIE_MMIO_HIGH_LIMIT, // Max Base Address + 0, // Translate + SBSA_PCIE_MMIO_HIGH_SIZE // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0, // Min Base Address + 0xffff, // Max Base Address + SBSA_PCIE_PIO_BASE, // Translate + 0x10000, // Length + ,,,TypeTranslation + ) + }) // Name(RBUF) + + Return (RBUF) + } // Method(_CRS) + + // OS Control Handoff + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + * See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC,4) { + // Check for proper UUID + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3,0,CDW1) + CreateDWordField (Arg3,4,CDW2) + CreateDWordField (Arg3,8,CDW3) + + // Save Capabilities DWord2 & 3 + SUPP = CDW2 + CTRL = CDW3 + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If ((SUPP & 0x16) != 0x16) { + CTRL &= 0x1E // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + CTRL &= 0x1D + + If (Arg1 != One) { // Unknown revision + CDW1 |= 0x08 + } + + If (CDW3 != CTRL) { // Capabilities bits were masked + CDW1 |= 0x10 + } + + // Update DWORD3 in the buffer + CDW3 = CTRL + Return (Arg3) + } Else { + CDW1 |= 4 // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } + } // Scope (_SB) +} diff --git a/src/mainboard/emulation/qemu-sbsa/flash.fmd b/src/mainboard/emulation/qemu-sbsa/flash.fmd new file mode 100644 index 000000000000..fcc6e19a9935 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/flash.fmd @@ -0,0 +1,23 @@ +# +# custom fmap which takes the additional TF-A region into account +# +# +-------------+ <-- 0x0 +# | TF-A | +# +-------------+ <-- BIOS_BASE +# | bootblock | +# +-------------+ <-- BIOS_BASE + 128K +# | FMAP | +# +-------------+ <-- BIOS_BASE + 128K + FMAP_SIZE +# | CBFS | +# +-------------+ <-- ROM_SIZE +# + +FLASH@0x10000000 CONFIG_ROM_SIZE { + + BIOS { + + BOOTBLOCK 128K + FMAP 0x200 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h new file mode 100644 index 000000000000..84c2d05bcac7 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/include/mainboard/addressmap.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Base addresses for QEMU sbsa-ref machine + * [hw/arm/sbsa-ref.c, c6f3cbca32bde9ee94d9949aa63e8a7ef2d7bc5b] + */ + +#define SBSA_FLASH_BASE 0x00000000 +#define SBSA_FLASH_SIZE 0x20000000 +#define SBSA_GIC_DIST 0x40060000 +#define SBSA_GIC_REDIST 0x40080000 +#define SBSA_GWDT_REFRESH 0x50010000 +#define SBSA_GWDT_CONTROL 0x50011000 +#define SBSA_UART_BASE 0x60000000 +#define SBSA_RTC_BASE 0x60010000 +#define SBSA_GPIO_BASE 0x60020000 +#define SBSA_SECURE_UART_BASE 0x60030000 +#define SBSA_SMMU_BASE 0x60050000 +#define SBSA_AHCI_BASE 0x60100000 +#define SBSA_EHCI_BASE 0x60110000 +#define SBSA_SECMEM_BASE 0x20000000 +#define SBSA_SECMEM_SIZE 0x20000000 +#define SBSA_PCIE_MMIO_BASE 0x80000000 +#define SBSA_PCIE_MMIO_LIMIT 0xefffffff +#define SBSA_PCIE_MMIO_SIZE 0x70000000 +#define SBSA_PCIE_PIO_BASE 0x7fff0000 +#define SBSA_PCIE_ECAM_BASE 0xf0000000 +#define SBSA_PCIE_ECAM_LIMIT 0xffffffff +#define SBSA_PCIE_ECAM_SIZE 0x10000000 +#define SBSA_PCIE_MMIO_HIGH_BASE 0x100000000 +#define SBSA_PCIE_MMIO_HIGH_LIMIT 0xffffffffff +#define SBSA_PCIE_MMIO_HIGH_SIZE 0xff00000000 diff --git a/src/mainboard/emulation/qemu-sbsa/mainboard.c b/src/mainboard/emulation/qemu-sbsa/mainboard.c new file mode 100644 index 000000000000..112e1183e492 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/mainboard.c @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "chip.h" +#include <acpi/acpigen.h> +#include <arch/mmu.h> +#include <bootmem.h> +#include <cbfs.h> +#include <device/device.h> +#include <device_tree.h> +#include <bootmem.h> +#include <arch/mmu.h> +#include <mainboard/addressmap.h> +#include <stdint.h> +#include <symbols.h> + +static size_t ram_size(void) +{ + return (size_t)cbmem_top() - (uintptr_t)_dram; +} + +static void mainboard_init(void *chip_info) +{ + mmu_config_range(_dram, ram_size(), MA_MEM | MA_RW); +} + +void smbios_cpu_get_core_counts(u16 *core_count, u16 *thread_count) +{ + *core_count = 0; + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_GICC_V3))) + *core_count += 1; + + *thread_count = 1; +} + +static void qemu_aarch64_init(struct device *dev) +{ + struct memory_info *mem_info; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) + return; + + memset(mem_info, 0, sizeof(*mem_info)); + + mem_info->ecc_type = MEMORY_ARRAY_ECC_UNKNOWN; + mem_info->max_capacity_mib = 0x800000; // Fixed at 8 TiB for qemu-sbsa + mem_info->number_of_devices = mem_info->dimm_cnt = 1; + + mem_info->dimm[0].dimm_size = ram_size() / MiB; + mem_info->dimm[0].ddr_type = MEMORY_TYPE_DRAM; + mem_info->dimm[0].ddr_frequency = 0; + mem_info->dimm[0].channel_num = mem_info->dimm[0].dimm_num = 0; + mem_info->dimm[0].bank_locator = 0; + + mem_info->dimm[0].bus_width = 0x03; // 64-bit, no parity + mem_info->dimm[0].vdd_voltage = 0; + mem_info->dimm[0].max_speed_mts = mem_info->dimm[0].configured_speed_mts = 0; +} + +static unsigned long mb_write_acpi_tables(const struct device *dev, unsigned long current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "ACPI: * DBG2\n"); + return acpi_pl011_write_dbg2_uart(rsdp, current, SBSA_UART_BASE, "\\_SB.COM0"); +} + + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = qemu_aarch64_init; + dev->ops->write_acpi_tables = mb_write_acpi_tables; +} + + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, +}; + +struct chip_operations mainboard_emulation_qemu_sbsa_ops = { }; + +static void qemu_aarch64_domain_read_resources(struct device *dev) +{ + struct resource *res; + int index = 0; + + /* Initialize the system-wide I/O space constraints. */ + res = new_resource(dev, index++); + res->limit = 0xffffUL; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED; + + /* Initialize the system-wide memory resources constraints. */ + res = new_resource(dev, index++); + res->base = SBSA_PCIE_MMIO_BASE; + res->limit = SBSA_PCIE_MMIO_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + res = new_resource(dev, index++); + res->base = SBSA_PCIE_MMIO_HIGH_BASE; + res->limit = SBSA_PCIE_MMIO_HIGH_LIMIT; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; + + mmio_range(dev, index++, SBSA_PCIE_ECAM_BASE, SBSA_PCIE_ECAM_SIZE); + + ram_range(dev, index++, (uintptr_t)_dram, ram_size()); + + mmio_range(dev, index++, SBSA_FLASH_BASE, SBSA_FLASH_SIZE); + reserved_ram_range(dev, index++, SBSA_SECMEM_BASE, SBSA_SECMEM_SIZE); +} + +struct device_operations qemu_aarch64_pci_domain_ops = { + .read_resources = qemu_aarch64_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, +}; + +static void qemu_sbsa_fill_cpu_ssdt(const struct device *dev) +{ + acpigen_write_processor_device(dev->path.gicc_v3.mpidr); + acpigen_write_processor_device_end(); +} + +struct device_operations qemu_sbsa_cpu_ops = { + .acpi_fill_ssdt = qemu_sbsa_fill_cpu_ssdt, +}; + +DECLARE_REGION(fdt_pointer) +static void qemu_aarch64_scan_bus(struct device *dev) +{ + struct bus *bus = alloc_bus(dev); + uintptr_t fdt_blob = *(uintptr_t *)_fdt_pointer; + struct device_tree *tree; + struct device_tree_node *node; + char path[14]; + u16 fdt_cpu_count = 0; + struct mainboard_emulation_qemu_sbsa_config *config = dev->chip_info; + + tree = fdt_unflatten((void *)fdt_blob); + if (tree == NULL) + return; + + snprintf(path, sizeof(path), "/cpus/cpu@%d", fdt_cpu_count); + while ((node = dt_find_node_by_path(tree, path, NULL, NULL, 0)) != NULL) { + struct device_tree_property *prop; + int64_t mpidr = -1; + list_for_each(prop, node->properties, list_node) { + if (!strcmp("reg", prop->prop.name)) { + mpidr = be64toh(*(uint64_t *)prop->prop.data); + break; + } + } + if (mpidr >= 0) { + struct device_path devpath = { .type = DEVICE_PATH_GICC_V3, + .gicc_v3 = { .mpidr = mpidr, + .vgic_mi = config->vgic_maintenance_interrupt, + .pi_gsiv = config->performance_interrupt_gsiv, }, + + }; + struct device *cpu = alloc_dev(bus, &devpath); + assert(cpu); + cpu->ops = &qemu_sbsa_cpu_ops; + } + snprintf(path, sizeof(path), "/cpus/cpu@%d", ++fdt_cpu_count); + } +} + +struct device_operations qemu_aarch64_cpu_ops = { + .scan_bus = qemu_aarch64_scan_bus, +}; diff --git a/src/mainboard/emulation/qemu-sbsa/media.c b/src/mainboard/emulation/qemu-sbsa/media.c new file mode 100644 index 000000000000..00ed54c4a3b4 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/media.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <boot_device.h> + +/* Maps directly to NOR flash up to ROM size. */ +static const struct mem_region_device boot_dev = + MEM_REGION_DEV_RO_INIT((void *)0x10000000, CONFIG_ROM_SIZE); + +const struct region_device *boot_device_ro(void) +{ + return &boot_dev.rdev; +} diff --git a/src/mainboard/emulation/qemu-sbsa/memlayout.ld b/src/mainboard/emulation/qemu-sbsa/memlayout.ld new file mode 100644 index 000000000000..d178521b6ef4 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/memlayout.ld @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <memlayout.h> +#include <arch/header.ld> + +/* + * Memory map for QEMU sbsa-ref machine since + * [hw/arm/sbsa-ref.c, c6f3cbca32bde9ee94d9949aa63e8a7ef2d7bc5b] + */ +SECTIONS +{ + REGION(flash, 0x10000000, CONFIG_ROM_SIZE, 8) + + DRAM_START(0x10000000000) + BOOTBLOCK(0x10020010000, 64K) + STACK(0x10020020000, 54K) + CBFS_MCACHE(0x1002002D800, 8K) + FMAP_CACHE(0x1002002F800, 2K) + TIMESTAMP(0x10020030000, 1K) + TTB(0x10020070000, 128K) + RAMSTAGE(0x100200b0000, 16M) + REGION(fdt_pointer, 0x100210b0000, ARCH_POINTER_ALIGN_SIZE, ARCH_POINTER_ALIGN_SIZE) + + POSTRAM_CBFS_CACHE(0x10021200000, 1M) +} diff --git a/src/mainboard/emulation/qemu-sbsa/mmio.c b/src/mainboard/emulation/qemu-sbsa/mmio.c new file mode 100644 index 000000000000..6b50856b9452 --- /dev/null +++ b/src/mainboard/emulation/qemu-sbsa/mmio.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/uart.h> +#include <mainboard/addressmap.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + return SBSA_UART_BASE; +} diff --git a/src/mainboard/foxconn/d41s/hda_verb.c b/src/mainboard/foxconn/d41s/hda_verb.c index 1042876a8bf5..7a752e346615 100644 --- a/src/mainboard/foxconn/d41s/hda_verb.c +++ b/src/mainboard/foxconn/d41s/hda_verb.c @@ -10,13 +10,13 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014c10), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19c30), AZALIA_PIN_CFG(0, 0x19, 0x02a19c31), AZALIA_PIN_CFG(0, 0x1a, 0x0181343f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), AZALIA_PIN_CFG(0, 0x1e, 0x99430120), }; diff --git a/src/mainboard/foxconn/g41s-k/hda_verb.c b/src/mainboard/foxconn/g41s-k/hda_verb.c index aedbc5d1b725..40ab35d8fdaf 100644 --- a/src/mainboard/foxconn/g41s-k/hda_verb.c +++ b/src/mainboard/foxconn/g41s-k/hda_verb.c @@ -12,19 +12,19 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x11, 0x99430140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014410), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), AZALIA_PIN_CFG(0, 0x1e, 0x01441130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; #else /* CONFIG_BOARD_FOXCONN_G41M */ const u32 cim_verb_data[] = { @@ -36,7 +36,7 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(2, 0x11, 0x01441140), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), AZALIA_PIN_CFG(2, 0x15, 0x01011412), AZALIA_PIN_CFG(2, 0x16, 0x01016411), @@ -48,7 +48,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(2, 0x1c, 0x593301f0), AZALIA_PIN_CFG(2, 0x1d, 0x4007f603), AZALIA_PIN_CFG(2, 0x1e, 0x99430130), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), }; #endif diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c index fbda35d867a6..6663b160b753 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c @@ -10,8 +10,8 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19830), AZALIA_PIN_CFG(0, 0x19, 0x02a19c31), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 3b9584360b09..81e243fd99cb 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -20,7 +20,22 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" - + register "usb_port_config" = "{ + { 1, 5, 0 }, + { 1, 5, 0 }, + { 1, 5, 1 }, + { 1, 5, 1 }, + { 1, 5, 2 }, + { 1, 5, 2 }, + { 1, 5, 3 }, + { 1, 5, 3 }, + { 1, 5, 4 }, + { 1, 5, 4 }, + { 1, 5, 6 }, + { 1, 5, 5 }, + { 1, 5, 5 }, + { 1, 5, 6 } + }" device ref xhci on # USB 3.0 Controller subsystemid 0x1458 0x5007 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c index 8fd6f989ec0a..eea5b2064767 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/early_init.c @@ -39,20 +39,3 @@ void bootblock_mainboard_early_init(void) ite_reg_write(IT8728F_EC, 0x63, 0x20); ite_reg_write(IT8728F_EC, 0x30, 0x01); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 5, 0 }, - { 1, 5, 0 }, - { 1, 5, 1 }, - { 1, 5, 1 }, - { 1, 5, 2 }, - { 1, 5, 2 }, - { 1, 5, 3 }, - { 1, 5, 3 }, - { 1, 5, 4 }, - { 1, 5, 4 }, - { 1, 5, 6 }, - { 1, 5, 5 }, - { 1, 5, 5 }, - { 1, 5, 6 }, -}; diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h index 6a37e86f0b65..2de8d014d0b9 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75-d3v/include/variant/hda_verb.h @@ -14,19 +14,19 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(2, 0x11, 0x99430130), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), }; #endif diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h index 23f6ef269285..8824a7e0712f 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h +++ b/src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/include/variant/hda_verb.h @@ -10,20 +10,20 @@ const u32 cim_verb_data[] = { 0x0000000e, // Number of entries /* Pin Widget Verb Table */ - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014410), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), AZALIA_PIN_CFG(0, 0x19, 0x02a19c60), AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)) }; #endif diff --git a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c index a19839f40135..ff9e4ba97c0f 100644 --- a/src/mainboard/gigabyte/ga-d510ud/hda_verb.c +++ b/src/mainboard/gigabyte/ga-d510ud/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x1458a002, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x1458a002), - AZALIA_PIN_CFG(2, 0x11, 0x411111f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c30), AZALIA_PIN_CFG(2, 0x19, 0x02a19c50), AZALIA_PIN_CFG(2, 0x1a, 0x0181344f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), AZALIA_PIN_CFG(2, 0x1c, 0x593301f0), AZALIA_PIN_CFG(2, 0x1d, 0x4005c603), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c index a867258b223a..71e34125b4e9 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -11,11 +11,11 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x11, 0x411110f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014410), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19c40), AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), AZALIA_PIN_CFG(0, 0x1a, 0x0181344f), diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 8a29171fda89..0a0a445d5770 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -16,6 +16,23 @@ chip northbridge/intel/sandybridge register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" + device ref mei1 on end # MEI #1 device ref ehci2 on end # USB2 EHCI #2 device ref hda on end # HD Audio diff --git a/src/mainboard/gigabyte/ga-h61m-series/early_init.c b/src/mainboard/gigabyte/ga-h61m-series/early_init.c index 6f9109af0f9b..80a3f0fe2a53 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/early_init.c +++ b/src/mainboard/gigabyte/ga-h61m-series/early_init.c @@ -9,23 +9,6 @@ #define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(0x2e, 0x01) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { if (!CONFIG(NO_UART_ON_SUPERIO)) { diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c index 659d1b693b72..86bc679e3797 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/hda_verb.c @@ -8,19 +8,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x1458a002), AZALIA_PIN_CFG(2, 0x11, 0x411110f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c20), AZALIA_PIN_CFG(2, 0x19, 0x02a19c30), AZALIA_PIN_CFG(2, 0x1a, 0x0181342f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c1f), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c index 33fd9d22c5de..3856bb0ca17f 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2v/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x1458a002, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x1458a002), - AZALIA_PIN_CFG(2, 0x11, 0x411111f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c index 33fd9d22c5de..3856bb0ca17f 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2pv/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x1458a002, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x1458a002), - AZALIA_PIN_CFG(2, 0x11, 0x411111f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c index e17421fe77cc..3b00942080cf 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61ma-d3v/hda_verb.c @@ -8,18 +8,18 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x1458a002), AZALIA_PIN_CFG(2, 0x11, 0x411110f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), - AZALIA_PIN_CFG(2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19c60), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1f, 0x41c46060), }; diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h index 4d269aedafc5..4097b4a3a80d 100644 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/hda_verb.h @@ -24,7 +24,7 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ // group 1, cap 0 @@ -34,10 +34,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -54,7 +54,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1A, 0x90a70111), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -64,7 +64,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h index 538f131c2906..f8b509caca04 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/hda_verb.h @@ -37,7 +37,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x17, 0x40000008), /* Pin Complex (NID 0x18) Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -47,10 +47,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -60,7 +60,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group1 diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h index c0db8c2c9444..6cc5bf0579b5 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/gandof/include/variant/hda_verb.h @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -51,10 +51,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -64,7 +64,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack */ // group2, cap 1 diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h index 33ae19929350..3f9ec3f5e384 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h +++ b/src/mainboard/google/auron/variants/lulu/include/variant/hda_verb.h @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -51,10 +51,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -64,7 +64,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/mccloud/hda_verb.c +++ b/src/mainboard/google/beltino/variants/mccloud/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/beltino/variants/monroe/hda_verb.c b/src/mainboard/google/beltino/variants/monroe/hda_verb.c index ae2e94e4b012..064bebfeea79 100644 --- a/src/mainboard/google/beltino/variants/monroe/hda_verb.c +++ b/src/mainboard/google/beltino/variants/monroe/hda_verb.c @@ -25,19 +25,19 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled*/ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF - 3.5mm Jack*/ AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -47,10 +47,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I - Disabled */ - AZALIA_PIN_CFG(0, 0x21, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_CFG_NC(0)), /* Undocumented settings from Realtek (needed for beep_gen) */ /* Widget node 0x20 */ diff --git a/src/mainboard/google/beltino/variants/panther/hda_verb.c b/src/mainboard/google/beltino/variants/panther/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/panther/hda_verb.c +++ b/src/mainboard/google/beltino/variants/panther/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/beltino/variants/tricky/hda_verb.c b/src/mainboard/google/beltino/variants/tricky/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/tricky/hda_verb.c +++ b/src/mainboard/google/beltino/variants/tricky/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/beltino/variants/zako/hda_verb.c b/src/mainboard/google/beltino/variants/zako/hda_verb.c index 550ae829e987..51dd16966828 100644 --- a/src/mainboard/google/beltino/variants/zako/hda_verb.c +++ b/src/mainboard/google/beltino/variants/zako/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ AZALIA_PIN_CFG(0, 0x14, 0x401111f0), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 0ec52201c888..2637e8940a5a 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -16,7 +16,7 @@ config BOARD_GOOGLE_BROX_COMMON select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_SKUID - select ENABLE_TCSS_USB_DETECTION if !CHROMEOS + select ENABLE_TCSS_USB_DETECTION if !(SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION || CHROMEOS) select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION @@ -29,7 +29,7 @@ config BOARD_GOOGLE_BROX_COMMON select MAINBOARD_HAS_TPM2 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU -# select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES @@ -44,13 +44,15 @@ config BOARD_GOOGLE_BASEBOARD_BROX select DRIVERS_AUDIO_SOF select DRIVERS_GFX_GENERIC select HAVE_SLP_S0_GATE - select MEMORY_SOLDERDOWN + select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_GREENBAYUPOC select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_CRASHLOG select SOC_INTEL_RAPTORLAKE select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION select DRIVERS_INTEL_ISH + select MAINBOARD_HAS_EARLY_LIBGFXINIT select SYSTEM_TYPE_LAPTOP select TPM_GOOGLE_TI50 @@ -69,6 +71,8 @@ config BOARD_GOOGLE_LOTSO config BOARD_GOOGLE_GREENBAYUPOC select BOARD_GOOGLE_BASEBOARD_BROX + select CHROMEOS_WIFI_SAR if CHROMEOS + select MEMORY_SODIMM if BOARD_GOOGLE_BROX_COMMON @@ -131,9 +135,6 @@ config VARIANT_DIR config VBOOT select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index f901db97352f..89c714d2bfd3 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -21,6 +21,9 @@ chip soc/intel/alderlake # seen on J0 and Q0 SKUs register "disable_package_c_state_demotion" = "1" + # Disable C1 state auto-demotion for all brox baseboards + register "disable_c1_state_auto_demotion" = "1" + # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 3d87bf25c8bd..edff2be8583d 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* GPP_B2 : [NF1: VRALERT# NF6: USB_C_GPP_B2] ==> VRALERT_L (NC) */ PAD_NC(GPP_B2, NONE), /* GPP_B3 : [NF1: PROC_GP2 NF4: ISH_GP4B NF6: USB_C_GPP_B3] ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */ PAD_NC(GPP_B4, NONE), /* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */ @@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */ PAD_NC(GPP_D13, NONE), /* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */ - PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D14, DN_20K), /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> SOC_ISH_UART0_RTS_L (NC) */ PAD_NC(GPP_D15, NONE), /* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> SOC_GPP_D16 (NC) */ @@ -187,7 +187,7 @@ static const struct pad_config gpio_table[] = { /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_E3 : [NF1: PROC_GP0 NF6: USB_C_GPP_E3] ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, DEEP, LEVEL, INVERT), /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> SOC_GPP_E5 (NC) */ diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c index 512d27ed4c31..3962991325f1 100644 --- a/src/mainboard/google/brox/variants/brox/fw_config.c +++ b/src/mainboard/google/brox/variants/brox/fw_config.c @@ -24,8 +24,8 @@ static const struct pad_config ish_enable_pads[] = { /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */ - PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), - /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ + PAD_CFG_NF(GPP_D14, DN_20K, DEEP, NF1), + /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */ PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2), }; diff --git a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h index 482c0a641371..c0b0eb0733aa 100644 --- a/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h +++ b/src/mainboard/google/brox/variants/brox/include/variant/hda_verb.h @@ -110,9 +110,9 @@ const u32 cim_verb_data[] = { * To set LDO1/LDO2 as default (used for headset) */ 0x02050008, - 0x0204EA0C, + 0x02046A0C, 0x02050008, - 0x0204EA0C, + 0x02046A0C, }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 7b00098853aa..424d61c6cbde 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -28,6 +28,7 @@ fw_config end chip soc/intel/alderlake + register "platform_pmax" = "208" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -35,18 +36,42 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[1].desc" = ""Fan-Inlet"" - # TODO: below values are initial reference values only ## Active Policy register "policies.active" = "{ [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(95, 90), + TEMP_PCT(92, 80), + TEMP_PCT(89, 60), + TEMP_PCT(85, 40), + TEMP_PCT(80, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), + } + }, + [2] = { .target = DPTF_TEMP_SENSOR_1, .thresholds = { - TEMP_PCT(85, 90), - TEMP_PCT(80, 80), - TEMP_PCT(75, 70), - TEMP_PCT(70, 60), - TEMP_PCT(65, 50), - TEMP_PCT(60, 40), + TEMP_PCT(54, 95), + TEMP_PCT(52, 90), + TEMP_PCT(50, 80), + TEMP_PCT(48, 50), + TEMP_PCT(46, 30), + TEMP_PCT(44, 25), + TEMP_PCT(42, 20), + TEMP_PCT(40, 15), } } }" @@ -137,8 +162,6 @@ chip soc/intel/alderlake end # Integrated Graphics Device device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] - use conn1 as mux_conn[1] device pnp 0c09.0 on end end end @@ -148,12 +171,12 @@ chip soc/intel/alderlake chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port use tcss_usb3_port1 as usb3_port - device generic 0 alias conn0 on end + device generic 0 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port3 as usb3_port - device generic 1 alias conn1 on end + device generic 1 on end end end end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk new file mode 100644 index 000000000000..a5ee3624fd3a --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +romstage-y += memory.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/greenbayupoc/data.vbt b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt Binary files differnew file mode 100644 index 000000000000..716d09f557da --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/data.vbt diff --git a/src/mainboard/google/brox/variants/greenbayupoc/gpio.c b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c new file mode 100644 index 000000000000..f26f098e9de5 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: E3110FFB1FCDA587 + * Overrides: None + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */ + PAD_NC(GPP_A19, NONE), + /* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */ + PAD_NC(GPP_A20, NONE), + + /* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX + * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */ + PAD_NC(GPP_D9, NONE), + /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX + * NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */ + PAD_NC(GPP_D10, NONE), + + /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + + /* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */ + PAD_NC(GPP_H15, NONE), + /* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */ + PAD_NC(GPP_H17, NONE), + + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h index 482c0a641371..79c81d1315dd 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h +++ b/src/mainboard/google/brox/variants/greenbayupoc/include/variant/hda_verb.h @@ -7,13 +7,13 @@ const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 - 0x10ec12ac, // Subsystem ID + 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC236 + 0x103C8C60, // Subsystem ID 0x00000013, // Number of jacks (NID entries) AZALIA_RESET(0x1), /* NID 0x01, HDA Codec Subsystem ID Verb table */ - AZALIA_SUBVENDOR(0, 0x10ec12ac), + AZALIA_SUBVENDOR(0, 0x103C8C60), /* Pin Widget Verb Table */ @@ -30,41 +30,56 @@ const u32 cim_verb_data[] = { /* Pin widget 0x18 - NPC */ AZALIA_PIN_CFG(0, 0x18, 0x411111F0), /* Pin widget 0x19 - MIC2 (Port-F) */ - AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + AZALIA_PIN_CFG(0, 0x19, 0x03A11020), /* Pin widget 0x1A - LINE1 (Port-C) */ AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), /* Pin widget 0x1B - NPC */ AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), /* Pin widget 0x1D - BEEP-IN */ - AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + AZALIA_PIN_CFG(0, 0x1d, 0x40600001), /* Pin widget 0x1E - NPC */ AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), /* Pin widget 0x21 - HP1-OUT (Port-I) */ - AZALIA_PIN_CFG(0, 0x21, 0x04211020), + AZALIA_PIN_CFG(0, 0x21, 0x03211040), + /* - * Widget node 0x20 - 1 - * Codec hidden reset and speaker power 2W/4ohm + * ;Pin widget 0x19 - MIC2 (Port-F) */ - 0x0205001A, - 0x0204C003, - 0x02050038, - 0x02047901, + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F03, /* - * Widget node 0x20 - 2 - * Class D power on Reset + * Pin widget 0x21 - HP1-OUT (Port-I) + */ + 0x02171C40, + 0x02171D10, + 0x02171E21, + 0x02171F03, + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm */ 0x0205003C, 0x02040354, 0x0205003C, 0x02040314, /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205001B, + 0x02040A4B, + 0x0205000B, + 0x02047778, + /* * Widget node 0x20 - 3 * Disable AGC and set AGC limit to -1.5dB */ - 0x02050016, - 0x02040C50, - 0x02050012, - 0x0204EBC1, + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409A3, /* * Widget node 0x20 - 4 * Set AGC Post gain +1.5dB then Enable AGC diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory.c b/src/mainboard/google/brox/variants/greenbayupoc/memory.c new file mode 100644 index 000000000000..3cfa79e95009 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/memory.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + .resistor = 100, + .targets = {50, 20, 25, 25, 25}, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = 0, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +bool variant_is_half_populated(void) +{ + return false; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; + spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk deleted file mode 100644 index eace2e443e20..000000000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. - -SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt deleted file mode 100644 index 2e0f37a10a61..000000000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt - -DRAM Part Name ID to assign diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb index ee65135d8845..1939325e44ab 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb +++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb @@ -1,14 +1,202 @@ fw_config - field STORAGE 0 1 + field RETIMER 0 1 + option RETIMER_UNKNOWN 0 + option RETIMER_BYPASS 1 + end + field STORAGE 2 3 option STORAGE_UNKNOWN 0 - option STORAGE_UFS 1 - option STORAGE_NVME 2 + option STORAGE_NVME 1 + option STORAGE_UFS 2 + end + field WIFI 4 + option WIFI_CNVI_WIFI 0 + option WIFI_BT_PCIE 1 + end + field UFC 5 + option UFC_NONE 0 + option UFC_USB 1 + end + field AUDIO 6 7 + option AUDIO_UNKNOWN 0 + option AUDIO_REALTEK_ALC3247 1 end end chip soc/intel/alderlake + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI) device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + probe STORAGE STORAGE_UNKNOWN + end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI WIFI_BT_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI WIFI_BT_PCIE + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI WIFI_CNVI_WIFI + end + device ref smbus on end end end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c new file mode 100644 index 000000000000..b46832035632 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/variant.c b/src/mainboard/google/brox/variants/greenbayupoc/variant.c new file mode 100644 index 000000000000..9452ad0eb987 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/variant.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <baseboard/variants.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_WIFI))) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + } +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk new file mode 100644 index 000000000000..48683172d658 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += memory.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/lotso/gpio.c b/src/mainboard/google/brox/variants/lotso/gpio.c new file mode 100644 index 000000000000..230ecaf005f7 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/gpio.c @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_D5 : SRCCLKREQ0_L ==> PCIE_REFCLK_SSD1_REQ_N */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SOC_GPP_E10 (NC) */ + PAD_NC(GPP_D6, NONE), + /* GPP_D7 : SRCCLKREQ2_L ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX + * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> HOST_MCU_FW_UP_STRAP */ + PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG), + /* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> GSPI0_SOC_FP_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), + /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 + * NF7: GSPI0_CLK] ==> GSPI0_SOC_FP_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> GSPI0_SOC_DI_FP_DO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> GSPI0_SOC_DO_FP_DI */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), + /* GPP_E15 : SRCCLK_OE8_L ==> SOC_GPP_E15 (NC) */ + PAD_NC(GPP_E15, NONE), + /* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX + * NF6: USB_C_GPP_E18] ==> SOC_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E18, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX + * NF6: USB_C_GPP_E20] ==> EN_FP_PWR */ + PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), + /* GPP_E21 : DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_E21, 0, LOCK_CONFIG), + /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK + * NF6: USB_C_GPP_F11] ==> GSPI1_SOC_TCHSCR_CLK */ + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), + /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL + * NF6: USB_C_GPP_F12] ==> GSPI1_SOC_DO_TCHSCR_DI */ + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), + /* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA + * NF6: USB_C_GPP_F13] ==> GSPI1_SOC_DI_TCHSCR_DO */ + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), + /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 + * NF6: USB_C_GPP_F15] ==> PCH_TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_F15, 0, PLTRST), + /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# + * NF6: USB_C_GPP_F16] ==> GSPI1_SOC_TCHSCR_CS_L */ + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), + /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_S4, NONE, PLTRST), + /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_S5, NONE, PLTRST), + /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_S6, NONE, PLTRST), + /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_S7, NONE, PLTRST), + /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, EDGE_SINGLE, NONE), +}; + + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_S4, NONE, PLTRST), + /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_S5, NONE, PLTRST), + /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_S6, NONE, PLTRST), + /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_S7, NONE, PLTRST), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/brox/variants/lotso/memory.c b/src/mainboard/google/brox/variants/lotso/memory.c new file mode 100644 index 000000000000..0765d5e57eb0 --- /dev/null +++ b/src/mainboard/google/brox/variants/lotso/memory.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* Leave Rcomp unspecified to use the FSP optimized defaults */ + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 13, 15, 14, 12, 11, 9, 10, 8 }, + .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4 }, + }, + .ddr1 = { + .dq0 = { 2, 0, 1, 3, 6, 4, 7, 5 }, + .dq1 = { 13, 15, 12, 14, 10, 11, 8, 9 }, + }, + .ddr2 = { + .dq0 = { 14, 13, 12, 15, 9, 10, 11, 8 }, + .dq1 = { 4, 6, 7, 5, 1, 2, 0, 3 }, + }, + .ddr3 = { + .dq0 = { 14, 13, 15, 12, 8, 11, 9, 10 }, + .dq1 = { 0, 2, 1, 3, 6, 5, 7, 4 }, + }, + .ddr4 = { + .dq0 = { 8, 11, 10, 9, 14, 15, 13, 12 }, + .dq1 = { 3, 0, 2, 1, 5, 7, 4, 6 }, + }, + .ddr5 = { + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5 }, + .dq1 = { 12, 13, 15, 14, 10, 9, 8, 11 }, + }, + .ddr6 = { + .dq0 = { 1, 0, 3, 2, 5, 7, 6, 4 }, + .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 7, 4, 5, 6 }, + .dq1 = { 14, 15, 9, 11, 12, 8, 10, 13 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, /* Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * MEM_STRAP_0 GPP_S4 + * MEM_STRAP_1 GPP_S5 + * MEM_STRAP_2 GPP_S6 + * MEM_STRAP_3 GPP_S7 + */ + gpio_t spd_gpios[] = { + GPP_S4, + GPP_S5, + GPP_S6, + GPP_S7, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk index eace2e443e20..2616d2d015c2 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/lotso/memory src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 0(0b0000) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = K3KL8L80DM-MGCU, MT62F1G32D2DS-023 WT:C, H58G56BK8BX068 diff --git a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt index fa247902eeee..e7d0650b950c 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt @@ -1 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/lotso/memory src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt + DRAM Part Name ID to assign +K3KL6L60GM-MGCT 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL8L80DM-MGCU 2 (0010) +MT62F1G32D2DS-023 WT:C 2 (0010) +H58G56BK8BX068 2 (0010) diff --git a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt index 2499005682ab..d2c09aee31ed 100644 --- a/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt +++ b/src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +K3KL6L60GM-MGCT +H9JCNNNBK3MLYR-N6E +K3KL8L80DM-MGCU +MT62F1G32D2DS-023 WT:C +H58G56BK8BX068 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 66839d161cdb..db2ed796e714 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -1,5 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +config ACPI_FNKEY_GEN_SCANCODE + default 94 if BOARD_GOOGLE_XOL + config BOARD_GOOGLE_BRYA_COMMON def_bool n select DRIVERS_GENERIC_ALC1015 @@ -64,7 +67,7 @@ config BOARD_GOOGLE_BASEBOARD_BRASK select CR50_RESET_CLEAR_EC_AP_IDLE_FLAG select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP select HAVE_SLP_S0_GATE - select MEMORY_SODIMM if !BOARD_GOOGLE_CONSTITUTION + select MEMORY_SODIMM if !(BOARD_GOOGLE_CONSTITUTION || BOARD_GOOGLE_NOVA) select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE @@ -93,6 +96,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_AUDIO_SOF select DRIVERS_INTEL_ISH select MAINBOARD_DISABLE_STAGE_CACHE + select MAINBOARD_HAS_EARLY_LIBGFXINIT select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW @@ -184,6 +188,7 @@ config BOARD_GOOGLE_BRYA0 config BOARD_GOOGLE_BUJIA select BOARD_GOOGLE_BASEBOARD_BRASK + select INTEL_GMA_HAVE_VBT select SOC_INTEL_RAPTORLAKE config BOARD_GOOGLE_CRAASK @@ -358,6 +363,7 @@ config BOARD_GOOGLE_NOKRIS config BOARD_GOOGLE_NOVA select BOARD_GOOGLE_BASEBOARD_BRASK select SOC_INTEL_RAPTORLAKE + select MEMORY_SOLDERDOWN config BOARD_GOOGLE_OMNIGUL select BOARD_GOOGLE_BASEBOARD_BRYA @@ -366,6 +372,10 @@ config BOARD_GOOGLE_OMNIGUL select SOC_INTEL_RAPTORLAKE select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS +config BOARD_GOOGLE_ORISA + select BOARD_GOOGLE_BASEBOARD_TRULO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + config BOARD_GOOGLE_OSIRIS select BOARD_GOOGLE_BASEBOARD_BRYA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -403,10 +413,17 @@ config BOARD_GOOGLE_PUJJO config BOARD_GOOGLE_SUNDANCE select BOARD_GOOGLE_BASEBOARD_NISSA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_GPIO_KEYS + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_PUJJOGA select BOARD_GOOGLE_BASEBOARD_NISSA + select DRIVERS_GENERIC_GPIO_KEYS + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA @@ -439,6 +456,11 @@ config BOARD_GOOGLE_REDRIX4ES select GOOGLE_DSM_PARAM_FILE_NAME if VPD select SOC_INTEL_COMMON_BLOCK_IPU +config BOARD_GOOGLE_RIVEN + select BOARD_GOOGLE_BASEBOARD_NISSA + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_TWINLAKE + config BOARD_GOOGLE_SKOLAS select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENERIC_NAU8315 @@ -533,6 +555,7 @@ config BOARD_GOOGLE_XIVU config BOARD_GOOGLE_XOL select BOARD_GOOGLE_BASEBOARD_BRYA + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_I2C_DA7219 select DRIVERS_INTEL_ISH select SOC_INTEL_RAPTORLAKE @@ -634,6 +657,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_NIVVIKS default 0x1 if BOARD_GOOGLE_NOVA default 0x1 if BOARD_GOOGLE_OMNIGUL + default 0x0 if BOARD_GOOGLE_ORISA default 0x1 if BOARD_GOOGLE_OSIRIS default 0x0 if BOARD_GOOGLE_PIRRHA default 0x1 if BOARD_GOOGLE_PRIMUS @@ -641,6 +665,7 @@ config DRIVER_TPM_I2C_BUS default 0x0 if BOARD_GOOGLE_QUANDISO default 0x1 if BOARD_GOOGLE_REDRIX default 0x3 if BOARD_GOOGLE_REDRIX4ES + default 0x0 if BOARD_GOOGLE_RIVEN default 0x1 if BOARD_GOOGLE_SKOLAS default 0x1 if BOARD_GOOGLE_SKOLAS4ES default 0x1 if BOARD_GOOGLE_TAEKO @@ -669,8 +694,9 @@ config FMDFILE config TPM_TIS_ACPI_INTERRUPT int - default 13 if !BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_13 (GPP_A13_IRQ) + default 17 if BOARD_GOOGLE_ORISA # GPE0_DW0_17 (GPP_A17_IRQ) default 20 if BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_20 (GPP_A20_IRQ) + default 13 if !BOARD_GOOGLE_BASEBOARD_HADES # GPE0_DW0_13 (GPP_A13_IRQ) config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -722,6 +748,7 @@ config MAINBOARD_PART_NUMBER default "Nokris" if BOARD_GOOGLE_NOKRIS default "Nova" if BOARD_GOOGLE_NOVA default "Omnigul" if BOARD_GOOGLE_OMNIGUL + default "Orisa" if BOARD_GOOGLE_ORISA default "Osiris" if BOARD_GOOGLE_OSIRIS default "Pirrha" if BOARD_GOOGLE_PIRRHA default "Primus" if BOARD_GOOGLE_PRIMUS @@ -729,6 +756,7 @@ config MAINBOARD_PART_NUMBER default "Quandiso" if BOARD_GOOGLE_QUANDISO default "Redrix" if BOARD_GOOGLE_REDRIX default "Redrix4ES" if BOARD_GOOGLE_REDRIX4ES + default "Riven" if BOARD_GOOGLE_RIVEN default "Skolas" if BOARD_GOOGLE_SKOLAS default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES default "Sundance" if BOARD_GOOGLE_SUNDANCE @@ -785,6 +813,7 @@ config VARIANT_DIR default "nokris" if BOARD_GOOGLE_NOKRIS default "nova" if BOARD_GOOGLE_NOVA default "omnigul" if BOARD_GOOGLE_OMNIGUL + default "orisa" if BOARD_GOOGLE_ORISA default "osiris" if BOARD_GOOGLE_OSIRIS default "pirrha" if BOARD_GOOGLE_PIRRHA default "primus" if BOARD_GOOGLE_PRIMUS @@ -792,6 +821,7 @@ config VARIANT_DIR default "quandiso" if BOARD_GOOGLE_QUANDISO default "redrix" if BOARD_GOOGLE_REDRIX default "redrix4es" if BOARD_GOOGLE_REDRIX4ES + default "riven" if BOARD_GOOGLE_RIVEN default "skolas" if BOARD_GOOGLE_SKOLAS default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES default "sundance" if BOARD_GOOGLE_SUNDANCE @@ -814,9 +844,6 @@ config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA select VBOOT_LID_SWITCH -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index fe8fcc942ec5..3229b18cd884 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -122,6 +122,9 @@ config BOARD_GOOGLE_REDRIX config BOARD_GOOGLE_REDRIX4ES bool "-> Redrix4ES" +config BOARD_GOOGLE_RIVEN + bool "-> Riven" + config BOARD_GOOGLE_SKOLAS bool "-> Skolas" @@ -181,3 +184,6 @@ config BOARD_GOOGLE_SUNDANCE config BOARD_GOOGLE_PUJJOGA bool "-> Pujjoga" + +config BOARD_GOOGLE_ORISA + bool "-> Orisa" diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk index 3743228e8e8b..3a6695828f71 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk +++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk @@ -4,6 +4,7 @@ bootblock-y += gpio.c romstage-y += memory.c romstage-y += gpio.c +romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 55bd9c0be22a..495b5713da96 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -155,7 +155,37 @@ chip soc/intel/alderlake }" device domain 0 on - device ref igpu on end + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end device ref dtt on end device ref tcss_xhci on end device ref xhci on end diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads new file mode 100644 index 000000000000..3b02f14d95a7 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (eDP, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c index dc686fe242b1..64e1b14cfb22 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/ramstage.c @@ -16,7 +16,8 @@ void variant_configure_pads(void) base_pads = variant_gpio_table(&base_num); gpio_padbased_override(padbased_table, base_pads, base_num); override_pads = variant_gpio_override_table(&override_num); - gpio_padbased_override(padbased_table, override_pads, override_num); + if (override_pads != NULL) + gpio_padbased_override(padbased_table, override_pads, override_num); fw_config_gpio_padbased_override(padbased_table); gpio_configure_pads_with_padbased(padbased_table); free(padbased_table); diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk index 54a5c5b5c9e4..be05cd4e5c6c 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk +++ b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk @@ -1,8 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += gpio.c - romstage-y += memory.c -romstage-y += gpio.c - -ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index a5e2217fef71..9e6378f6e7a5 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -1,4 +1,57 @@ chip soc/intel/alderlake + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + register "usb2_ports[0]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 0 + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 2 + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 3 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 4 + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 5 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8 + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9 + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 10 + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 11 + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 12 + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 13 + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 14 + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 15 + + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 0 + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 2 + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 3 + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 5 + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 6 + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 7 + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 8 + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 9 + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # Disable USB3.0 Port 10 + + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 0 + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 2 + register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable USB-C Port 3 + + device domain 0 on + device ref igpu on end + device ref dtt on end + device ref tcss_xhci on end + device ref xhci on end + device ref shared_sram on end + device ref heci1 on end + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end end end diff --git a/src/mainboard/google/brya/variants/bujia/Makefile.mk b/src/mainboard/google/brya/variants/bujia/Makefile.mk new file mode 100644 index 000000000000..d38141ca2476 --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/bujia/data.vbt b/src/mainboard/google/brya/variants/bujia/data.vbt Binary files differnew file mode 100644 index 000000000000..6a06e1570d37 --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/data.vbt diff --git a/src/mainboard/google/brya/variants/bujia/gpio.c b/src/mainboard/google/brya/variants/bujia/gpio.c new file mode 100644 index 000000000000..484ce292299d --- /dev/null +++ b/src/mainboard/google/brya/variants/bujia/gpio.c @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A14 : USB_OC1# ==> NC */ + PAD_NC_LOCK(GPP_A14, NONE, LOCK_CONFIG), + /* A15 : USB_OC2# ==> NC */ + PAD_NC_LOCK(GPP_A15, NONE, LOCK_CONFIG), + /* A18 : DDSP_HPDB ==> HDMIB_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> NC */ + PAD_NC_LOCK(GPP_A19, NONE, LOCK_CONFIG), + /* A20 : DDSP_HPD2 ==> NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* A21 : DDPC_CTRCLK ==> NC */ + PAD_NC(GPP_A21, NONE), + /* A22 : DDPC_CTRLDATA ==> NC */ + PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG), + + /* B2 : VRALERT# ==> M2_SSD_PLA_L */ + PAD_NC(GPP_B2, NONE), + /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), + /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), + + /* D0 : ISH_GP0 ==> NC */ + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), + /* D2 : ISH_GP2 ==> NC */ + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), + /* D3 : ISH_GP3 ==> NC */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : ISH_SPI_CS# ==> NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> GPI */ + PAD_CFG_GPI_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D17 : UART1_RXD */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* D18 : UART1_TXD */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* E14 : DDSP_HPDA ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E20 : DDP2_CTRLCLK ==> DDIA_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> DDIA_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* F13 : GSXDOUT ==> NC */ + PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), + /* F15 : GSXSRESET# ==> NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : GSXCLK ==> NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + + /* H12 : I2C7_SDA ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : I2C7_SCL ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + + /* R4 : HDA_RST# ==> NC */ + PAD_NC(GPP_R4, NONE), + /* R5 : HDA_SDI1 ==> NC */ + PAD_NC(GPP_R5, NONE), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), + /* R7 : I2S2_RXD ==> NC */ + PAD_NC(GPP_R7, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F14 : GSXDIN ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 4f2c04a57af4..252d82f8a593 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -1,6 +1,320 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" - device domain 0 on - end + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | NC | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | NC | + #| I2C5 | NC | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + register "usb2_ports[0]" = "USB2_PORT_MAX_TYPE_C(OC2)" # set to Max for USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable Port 6 + + register "usb3_ports[2]" = "USB3_PORT_EMPTY " # Disable Port 2 + # USB3 Port 3 for OPS interface + + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable Port1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #NVME + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 off end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end # I2C1 + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "customized_leds" = "0x060f" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # RTL8111 Ethernet NIC + device ref pcie_rp8 off end # disable SD reader + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(8, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(7, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 OPS interface TX25A"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port4 on end + end + end + end + end + end end diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index 16c44af69204..61cb50022a3c 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -349,8 +349,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end @@ -377,7 +377,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -385,7 +385,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -398,14 +398,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/brya/variants/glassway/Makefile.mk b/src/mainboard/google/brya/variants/glassway/Makefile.mk index 102307a6cafe..e409037840dc 100644 --- a/src/mainboard/google/brya/variants/glassway/Makefile.mk +++ b/src/mainboard/google/brya/variants/glassway/Makefile.mk @@ -4,4 +4,7 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c + ramstage-y += variant.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/glassway/ramstage.c b/src/mainboard/google/brya/variants/glassway/ramstage.c new file mode 100644 index 000000000000..6d63eaa8f7dc --- /dev/null +++ b/src/mainboard/google/brya/variants/glassway/ramstage.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->VccInAuxImonIccImax = 100; // 25 * 4 for ADL-N + printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax); +} diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 49dfea867e8a..61344d7e63fe 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -297,8 +297,8 @@ chip soc/intel/alderlake end device ref pch_espi on chip ec/google/chromeec - use conn1 as mux_conn[1] - use conn2 as mux_conn[0] + use conn1 as mux_conn[0] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end @@ -325,7 +325,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" register "usb_lpm_incapable" = "true" device ref tcss_usb3_port2 on end end @@ -333,7 +333,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on end end end @@ -346,14 +346,14 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C2 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -365,7 +365,7 @@ chip soc/intel/alderlake register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -379,7 +379,7 @@ chip soc/intel/alderlake register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" device ref usb3_port1 on end end end diff --git a/src/mainboard/google/brya/variants/nova/Makefile.mk b/src/mainboard/google/brya/variants/nova/Makefile.mk index d38141ca2476..f4627aec1b19 100644 --- a/src/mainboard/google/brya/variants/nova/Makefile.mk +++ b/src/mainboard/google/brya/variants/nova/Makefile.mk @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c +romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/nova/memory.c b/src/mainboard/google/brya/variants/nova/memory.c new file mode 100644 index 000000000000..c3999501775b --- /dev/null +++ b/src/mainboard/google/brya/variants/nova/memory.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map as per doc #573387 */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 2, 1, 4, 6, 5, 7, }, + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, }, + }, + .ddr1 = { + .dq0 = { 13, 14, 11, 12, 10, 8, 15, 9, }, + .dq1 = { 5, 2, 4, 3, 1, 6, 0, 7, }, + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 7, 6, 5, 4, }, + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, }, + }, + .ddr3 = { + .dq0 = { 13, 14, 12, 15, 11, 9, 8, 10, }, + .dq1 = { 5, 2, 1, 4, 7, 0, 3, 6, }, + }, + .ddr4 = { + .dq0 = { 11, 10, 8, 9, 14, 15, 13, 12, }, + .dq1 = { 3, 0, 2, 1, 5, 4, 6, 7, }, + }, + .ddr5 = { + .dq0 = { 11, 15, 13, 12, 10, 9, 14, 8, }, + .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4, }, + }, + .ddr6 = { + .dq0 = { 11, 13, 10, 12, 15, 9, 14, 8, }, + .dq1 = { 4, 3, 5, 2, 7, 0, 1, 6, }, + }, + .ddr7 = { + .dq0 = { 12, 13, 15, 14, 11, 9, 10, 8, }, + .dq1 = { 4, 5, 1, 2, 6, 3, 0, 7, }, + }, + }, + + /* DQS CPU<>DRAM map as per doc #573387 */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 1, .dqs1 = 0 }, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_F16 + * GPIO_MEM_CONFIG_1 GPP_F12 + * GPIO_MEM_CONFIG_2 GPP_F13 + * GPIO_MEM_CONFIG_3 GPP_F15 + */ + gpio_t spd_gpios[] = { + GPP_F16, + GPP_F12, + GPP_F13, + GPP_F15, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_F11 */ + return gpio_get(GPP_F11); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brya/variants/nova/memory/Makefile.mk b/src/mainboard/google/brya/variants/nova/memory/Makefile.mk index bb0957dfe233..121eaba69d05 100644 --- a/src/mainboard/google/brya/variants/nova/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/nova/memory/Makefile.mk @@ -1,8 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AB-MGCL, H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt index e2089db069fc..65c620a31b45 100644 --- a/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/nova/memory/dram_id.generated.txt @@ -1,10 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen CZN lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen ADL lp4x src/mainboard/google/brya/variants/nova/memory src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt DRAM Part Name ID to assign K4U6E3S4AB-MGCL 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) -MT53E1G32D2NP-046 WT:B 1 (0001) -K4UBE3D4AB-MGCL 1 (0001) diff --git a/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt index 10f244d15b2f..c1727abb80a8 100644 --- a/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/nova/memory/mem_parts_used.txt @@ -1,4 +1,2 @@ K4U6E3S4AB-MGCL H9HCNNNBKMMLXR-NEE -MT53E1G32D2NP-046 WT:B -K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index 93018ea074d7..950bb9beabbe 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -6,6 +6,8 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 @@ -178,13 +180,6 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port1 as dfp[0].typec_port - device generic 0 on end - end - end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" diff --git a/src/mainboard/google/brya/variants/orisa/Makefile.mk b/src/mainboard/google/brya/variants/orisa/Makefile.mk new file mode 100644 index 000000000000..c0c42324f803 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/orisa/fw_config.c b/src/mainboard/google/brya/variants/orisa/fw_config.c new file mode 100644 index 000000000000..800fc1f20518 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/fw_config.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config emmc_disable_pads[] = { + /* I7 : EMMC_CMD */ + PAD_NC(GPP_I7, NONE), + /* I8 : EMMC_D0 */ + PAD_NC(GPP_I8, NONE), + /* I9 : EMMC_D1 */ + PAD_NC(GPP_I9, NONE), + /* I10 : EMMC_D2 */ + PAD_NC(GPP_I10, NONE), + /* I11 : EMMC_D3 */ + PAD_NC(GPP_I11, NONE), + /* I12 : EMMC_D4 */ + PAD_NC(GPP_I12, NONE), + /* I13 : EMMC_D5 */ + PAD_NC(GPP_I13, NONE), + /* I14 : EMMC_D6 */ + PAD_NC(GPP_I14, NONE), + /* I15 : EMMC_D7 */ + PAD_NC(GPP_I15, NONE), + /* I16 : EMMC_RCLK */ + PAD_NC(GPP_I16, NONE), + /* I17 : EMMC_CLK */ + PAD_NC(GPP_I17, NONE), + /* I18 : EMMC_RST_L */ + PAD_NC(GPP_I18, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "Disable eMMC GPIO pins.\n"); + gpio_padbased_override(padbased_table, emmc_disable_pads, + ARRAY_SIZE(emmc_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/gpio.c b/src/mainboard/google/brya/variants/orisa/gpio.c index 410f194f6502..beee6fcb29a6 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/orisa/gpio.c @@ -16,19 +16,24 @@ static const struct pad_config early_gpio_table[] = { /* TODO */ }; -const struct pad_config *__weak variant_gpio_table(size_t *num) +/* Fill romstage gpio configuration */ +static const struct pad_config romstage_gpio_table[] = { + /* TODO */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); return gpio_table; } -const struct pad_config *__weak variant_gpio_override_table(size_t *num) +const struct pad_config *variant_gpio_override_table(size_t *num) { *num = 0; return NULL; } -const struct pad_config *__weak variant_early_gpio_table(size_t *num) +const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; @@ -39,8 +44,8 @@ static const struct cros_gpio cros_gpios[] = { }; DECLARE_CROS_GPIOS(cros_gpios); -const struct pad_config *__weak variant_romstage_gpio_table(size_t *num) +const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = 0; - return NULL; + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; } diff --git a/src/mainboard/google/brya/variants/orisa/hda_verb.c b/src/mainboard/google/brya/variants/orisa/hda_verb.c new file mode 100644 index 000000000000..bf998e1f0c6e --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/hda_verb.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0x10ec12ac, // Subsystem ID + 0x00000013, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting - 1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default (used for headset) + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/ec.h b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h new file mode 100644 index 000000000000..7a2a6ff8b774 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h new file mode 100644 index 000000000000..c4fe342621e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/orisa/memory.c b/src/mainboard/google/brya/variants/orisa/memory.c new file mode 100644 index 000000000000..2d738554ec86 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/memory.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg variant_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &variant_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E1 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E1, + GPP_E2, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + return true; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brya/variants/orisa/memory/Makefile.mk b/src/mainboard/google/brya/variants/orisa/memory/Makefile.mk new file mode 100644 index 000000000000..28a0bee46b12 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/memory/Makefile.mk @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/orisa/memory src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/orisa/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/orisa/memory/dram_id.generated.txt new file mode 100644 index 000000000000..7f1a1837443e --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/memory/dram_id.generated.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/orisa/memory src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt index 2499005682ab..fc41c85c3324 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/orisa/memory/mem_parts_used.txt @@ -9,3 +9,4 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb new file mode 100644 index 000000000000..600eb024222a --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -0,0 +1,552 @@ +fw_config + field THERMAL_SOLUTION 0 0 + option THERMAL_SOLUTION_6W 0 + option THERMAL_SOLUTION_15W 1 + end + field STORAGE 30 31 + option STORAGE_EMMC 0 + option STORAGE_UFS 1 + end +end + +chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # GPE configuration + register "pmc_gpe0_dw1" = "GPP_B" + + # S0ix enable + register "s0ix_enable" = "1" + + # DPTF enable + register "dptf_enable" = "1" + + register "tcc_offset" = "10" # TCC of 90 + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # eMMC HS400 + register "emmc_enable_hs400_mode" = "1" + + #eMMC DLL tuning parameters + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC. + # Bit 2 - C1 has a redriver which does SBU muxing. + # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. + register "tcss_aux_ori" = "0" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_sdi_enable[1]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # FIXME: To be enabled in future based on PNP impact data. + # Disable Package C-state demotion for nissa baseboard. + register "disable_package_c_state_demotion" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Trackpad | + #| I2C5 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + register "power_limits_config[ADL_N_041_6W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 25, + .tdp_pl4 = 78, + }" + + register "power_limits_config[ADL_N_081_15W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 35, + .tdp_pl4 = 83, + }" + + device domain 0 on + device ref igpu on end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 60), + TEMP_PCT(39, 55), + TEMP_PCT(38, 50), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 60), + TEMP_PCT(50, 55), + TEMP_PCT(48, 50), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 6000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_6W + end + end + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(70, 100), + TEMP_PCT(60, 65), + TEMP_PCT(42, 58), + TEMP_PCT(39, 53), + TEMP_PCT(38, 47), + TEMP_PCT(35, 43), + TEMP_PCT(31, 30), + } + }, + [1] = { + .target = DPTF_TEMP_SENSOR_0, + .thresholds = { + TEMP_PCT(60, 100), + TEMP_PCT(55, 65), + TEMP_PCT(52, 58), + TEMP_PCT(50, 53), + TEMP_PCT(48, 47), + TEMP_PCT(45, 43), + TEMP_PCT(41, 30), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 100, 6000, 220, 2200, }, + [1] = { 92, 5500, 180, 1800, }, + [2] = { 85, 5000, 145, 1450, }, + [3] = { 70, 4400, 115, 1150, }, + [4] = { 56, 3900, 90, 900, }, + [5] = { 45, 3300, 55, 550, }, + [6] = { 38, 3000, 30, 300, }, + [7] = { 33, 2900, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 1 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_15W + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + end + end + end + device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)" + device i2c 50 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)" + register "wake" = "GPE0_DW1_03" + register "detect" = "1" + device i2c 15 on end + end + end #I2C1 + device ref i2c5 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)" + register "generic.enable_delay_ms" = "1" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)" + register "generic.stop_delay_ms" = "150" + register "generic.stop_off_delay_ms" = "2" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C5 + device ref heci1 on end + device ref pcie_rp7 off end + device ref emmc on end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end + device ref ufs on end + device ref uart0 on end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/google/brya/variants/orisa/variant.c b/src/mainboard/google/brya/variants/orisa/variant.c new file mode 100644 index 000000000000..f34fb2698b1c --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/variant.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <device/device.h> +#include <fw_config.h> + +void variant_devtree_update(void) +{ + struct device *emmc = DEV_PTR(emmc); + struct device *ufs = DEV_PTR(ufs); + struct device *ish = DEV_PTR(ish); + + if (!fw_config_is_provisioned()) { + printk(BIOS_INFO, "fw_config unprovisioned so enable all storage devices\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) { + printk(BIOS_INFO, "eMMC disabled by fw_config\n"); + emmc->enabled = 0; + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + printk(BIOS_INFO, "UFS disabled by fw_config\n"); + ufs->enabled = 0; + ish->enabled = 0; + } +} diff --git a/src/mainboard/google/brya/variants/pujjoga/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk new file mode 100644 index 000000000000..e04a887191b2 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/Makefile.mk @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += variant.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/pujjoga/fw_config.c b/src/mainboard/google/brya/variants/pujjoga/fw_config.c new file mode 100644 index 000000000000..eaef2a2fe338 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/fw_config.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config wwan_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* A12 : WWAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_A12, NONE), + /* D5 : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */ + PAD_NC(GPP_D5, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* D15 : EN_PP2800_WCAM_X ==> WWAN_SAR_DETECT_2_ODL */ + PAD_NC(GPP_D15, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H21 : WCAM_MCLK_R ==> WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT))) { + printk(BIOS_INFO, "Disable WWAN-related GPIO pins.\n"); + gpio_padbased_override(padbased_table, wwan_disable_pads, + ARRAY_SIZE(wwan_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c new file mode 100644 index 000000000000..cf5c9bdc0d49 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage for Sundance */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A18 : HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A20 : NC */ + PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG), + /* B5 : SOC_I2C_SUB_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : SOC_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_TERM_GPO(GPP_C1, 1, UP_20K, DEEP), + /* D3 : test point */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D8 : NC */ + PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG), + /* D15 : WWAN_SAR_DETECT_2_ODL */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : NC */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* D17 : NC ==> SD_WAKE_N */ + PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), + /* E20 : NC */ + PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG), + /* E21 : NC */ + PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H12 : NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_LOCK(GPP_H19, NONE, LOCK_CONFIG), + /* H21 : WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H22 : WCAM_MCLK_R ==> NC */ + PAD_NC_LOCK(GPP_H22, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL ==> NC */ + PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* + * WWAN_EN is asserted in ramstage to meet the 500 ms warm reset toff + * requirement. WWAN_EN must be asserted before WWAN_RST_L is released + * (with min delay 0 ms), so this works as long as the pin used for + * WWAN_EN comes before the pin used for WWAN_RST_L. + */ + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 0, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +/* Pad configuration in romstage for Sundance */ +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h index c4fe342621e6..c96b01fc1509 100644 --- a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk index eace2e443e20..c6e0a1cf1b87 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/pujjoga/memory/Makefile.mk @@ -1,5 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068, K3KL8L80CM-MGCT, MT62F1G32D2DS-026 WT:B +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt index fa247902eeee..adec69c7168c 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/dram_id.generated.txt @@ -1 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/pujjoga/memory src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt + DRAM Part Name ID to assign +H58G56BK7BX068 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL6L60GM-MGCT 2 (0010) +K3KL8L80CM-MGCT 0 (0000) +MT62F1G32D2DS-026 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt index 2499005682ab..b962c72c9cc2 100644 --- a/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/pujjoga/memory/mem_parts_used.txt @@ -9,3 +9,8 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H58G56BK7BX068 +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT +MT62F1G32D2DS-026 WT:B diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb index 4f2c04a57af4..951d60ef22d1 100644 --- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb @@ -1,6 +1,428 @@ +fw_config + field WWAN 3 4 + option WWAN_ABSENT 0 + option LTE_PRESENT 1 + option 5G_PRESENT 2 + end + field WIFI_SAR_ID 13 16 + option WIFI_SAR_TABLE_AX211 0 + option WIFI_SAR_TABLE_AX203 1 + end +end + chip soc/intel/alderlake + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "PreWake" = "100" + + register "sagv" = "SaGv_Enabled" + + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. + # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "5" + + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" + register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # UF Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WF Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN + + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 port for WWAN + + # Configure external V1P05/Vnn/VnnSx Rails for Pujjoga + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C1 | Touchscreen | + #| I2C2 | Sub-board(PSensor)/WCAM | + #| I2C3 | Audio | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .early_init = 1, + .speed = I2C_SPEED_FAST_PLUS, + .speed_config[0] = { + .speed = I2C_SPEED_FAST_PLUS, + .scl_lcnt = 55, + .scl_hcnt = 30, + .sda_hold = 7, + } + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 157, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 158, + .scl_hcnt = 79, + .sda_hold = 7, + } + }, + }" + + device domain 0 on + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.detect" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "20" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "3" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" + register "key.wake_gpe" = "GPE0_DW2_15" + register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x00" + register "reg_afe_ctrl1" = "0x10" + register "reg_afe_ctrl2" = "0x00" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl5" = "0x00" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0a" + register "reg_prox_ctrl2" = "0x90" + register "reg_prox_ctrl3" = "0x60" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x19" + register "reg_prox_ctrl7" = "0x58" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x08" + register "reg_adv_ctrl17" = "0x56" + register "reg_adv_ctrl18" = "0x33" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "1024" + register "ph23_resolution" = "1024" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "2" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""hi-z"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on end + end + end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""RTL5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/generic/alc1015 + register "hid" = ""RTL1019"" + register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + device generic 0 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "detect" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SYNA0000"" + register "generic.cid" = ""ACPI0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end + end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end - device domain 0 on - end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on + probe WWAN LTE_PRESENT + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 UFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WFC"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port3 on + probe WWAN LTE_PRESENT + end + end + end + end + end + end end diff --git a/src/mainboard/google/brya/variants/pujjoga/variant.c b/src/mainboard/google/brya/variants/pujjoga/variant.c new file mode 100644 index 000000000000..c4a6face5b57 --- /dev/null +++ b/src/mainboard/google/brya/variants/pujjoga/variant.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); +} diff --git a/src/mainboard/google/brya/variants/quandiso/overridetree.cb b/src/mainboard/google/brya/variants/quandiso/overridetree.cb index 21c9aba4818c..bebc927864c4 100644 --- a/src/mainboard/google/brya/variants/quandiso/overridetree.cb +++ b/src/mainboard/google/brya/variants/quandiso/overridetree.cb @@ -264,6 +264,9 @@ chip soc/intel/alderlake register "generic.detect" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" register "generic.reset_delay_ms" = "50" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "55" + register "generic.stop_off_delay_ms" = "5" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" register "generic.enable_delay_ms" = "1" register "generic.has_power_resource" = "1" diff --git a/src/mainboard/google/brya/variants/riven/Makefile.mk b/src/mainboard/google/brya/variants/riven/Makefile.mk new file mode 100644 index 000000000000..d38141ca2476 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/Makefile.mk @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/riven/data.vbt b/src/mainboard/google/brya/variants/riven/data.vbt Binary files differnew file mode 100644 index 000000000000..bc735476a5da --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/data.vbt diff --git a/src/mainboard/google/brya/variants/riven/gpio.c b/src/mainboard/google/brya/variants/riven/gpio.c new file mode 100644 index 000000000000..4d0a6fea79b0 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/gpio.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage for craask */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A18 : NC ==> HDMI_HPD_SUB_ODL*/ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + /* H12 : UART0_RTS# ==> NC */ + PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), + /* H13 : UART0_CTS# ==> NC */ + PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG), + /* H15 : HDMI_SRC_DDC_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : HDMI_SRC_DDC_SDA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* Configure the virtual CNVi Bluetooth I2S GPIO pads */ + /* BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), + /* BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), + /* BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), + /* BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), + /* SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* D6 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* Enable touchscreen, hold in reset */ + /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/riven/include/variant/ec.h b/src/mainboard/google/brya/variants/riven/include/variant/ec.h new file mode 100644 index 000000000000..7a2a6ff8b774 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/riven/include/variant/gpio.h b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h new file mode 100644 index 000000000000..c4fe342621e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/riven/memory/Makefile.mk b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk new file mode 100644 index 000000000000..0288c51143e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 0(0b0000) Parts = MT62F1G32D4DR-031 WT:B, H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-5.hex # ID = 2(0b0010) Parts = K3LKLKL0EM-MGCN +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 3(0b0011) Parts = K3LKBKB0BM-MGCP diff --git a/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt new file mode 100644 index 000000000000..f76709207524 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/dram_id.generated.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/riven/memory/ src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F1G32D4DR-031 WT:B 0 (0000) +MT62F512M32D2DR-031 WT:B 1 (0001) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3LKLKL0EM-MGCN 2 (0010) +K3LKBKB0BM-MGCP 3 (0011) +H9JCNNNCP3MLYR-N6E 0 (0000) diff --git a/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt new file mode 100644 index 000000000000..b08faac3e744 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/memory/mem_parts_used.txt @@ -0,0 +1,17 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name +MT62F1G32D4DR-031 WT:B +MT62F512M32D2DR-031 WT:B +H9JCNNNBK3MLYR-N6E +K3LKLKL0EM-MGCN +K3LKBKB0BM-MGCP +H9JCNNNCP3MLYR-N6E diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb new file mode 100644 index 000000000000..4f2c04a57af4 --- /dev/null +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end diff --git a/src/mainboard/google/brya/variants/sundance/Makefile.mk b/src/mainboard/google/brya/variants/sundance/Makefile.mk index d38141ca2476..be823735219d 100644 --- a/src/mainboard/google/brya/variants/sundance/Makefile.mk +++ b/src/mainboard/google/brya/variants/sundance/Makefile.mk @@ -3,4 +3,6 @@ bootblock-y += gpio.c romstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/sundance/fw_config.c b/src/mainboard/google/brya/variants/sundance/fw_config.c new file mode 100644 index 000000000000..f8f9a07933e6 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/fw_config.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config wwan_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* A12 : WWAN_PCIE_WAKE_ODL */ + PAD_NC(GPP_A12, NONE), + /* D5 : SRCCLKREQ0# ==> WWAN_CLKREQ_ODL */ + PAD_NC(GPP_D5, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* D15 : EN_PP2800_WCAM_X ==> WWAN_SAR_DETECT_2_ODL */ + PAD_NC(GPP_D15, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H21 : WCAM_MCLK_R ==> WWAN_PERST_L */ + PAD_NC_LOCK(GPP_H21, NONE, LOCK_CONFIG), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (fw_config_probe(FW_CONFIG(WWAN, LTE_ABSENT))) { + printk(BIOS_INFO, "Disable WWAN-related GPIO pins.\n"); + gpio_padbased_override(padbased_table, wwan_disable_pads, + ARRAY_SIZE(wwan_disable_pads)); + } +} diff --git a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h index c4fe342621e6..c96b01fc1509 100644 --- a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index bd1ed7403de7..bd5112fe44fd 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -1,3 +1,13 @@ +fw_config + field WWAN 3 4 + option LTE_ABSENT 0 + option LTE_PRESENT 1 + end + field WIFI_SAR_ID 12 15 + option WIFI_SAR_TABLE_AX211 0 + end +end + chip soc/intel/alderlake # Acoustic settings register "acoustic_noise_mitigation" = "1" @@ -11,31 +21,31 @@ chip soc/intel/alderlake # EMMC Tx CMD Delay # Refer to EDS-Vol2-42.3.7. - # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39, total 625ps. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39, total 625ps. register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-42.3.8. - # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78. - # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78, total 465ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79, total 465ps. register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" # EMMC TX DATA Delay 2 # Refer to EDS-Vol2-42.3.9. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79. - # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 5250ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79, total 5000ps. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79, total 5000ps. register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" # EMMC RX CMD/DATA Delay 1 # Refer to EDS-Vol2-42.3.10. - # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119. - # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. - # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. - # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 3375ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119, total 3250ps. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119, total 3375ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. @@ -44,14 +54,14 @@ chip soc/intel/alderlake # 01: Rx clock before output buffer, # 10: Automatic selection based on working mode. # 11: Reserved - # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. - # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39, total 0ps. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79, total 5000ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11. - # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39. - # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39. + # [14:8] Rx Strobe Delay DLL 1 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. + # [6:0] Rx Strobe Delay DLL 2 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" # SOC Aux orientation override: @@ -195,7 +205,7 @@ chip soc/intel/alderlake register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" register "generic.wake" = "GPE0_DW2_14" register "generic.detect" = "1" - register "hid_desc_reg_offset" = "0x20" + register "hid_desc_reg_offset" = "0x01" device i2c 0x38 on end end end @@ -275,7 +285,9 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb2_port5 on end + device ref usb2_port5 on + probe WWAN LTE_PRESENT + end end chip drivers/usb/acpi register "desc" = ""USB2 UFC"" @@ -304,7 +316,9 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device ref usb3_port3 on end + device ref usb3_port3 on + probe WWAN LTE_PRESENT + end end end end diff --git a/src/mainboard/google/brya/variants/sundance/variant.c b/src/mainboard/google/brya/variants/sundance/variant.c new file mode 100644 index 000000000000..c4a6face5b57 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/variant.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); +} diff --git a/src/mainboard/google/brya/variants/trulo/Makefile.mk b/src/mainboard/google/brya/variants/trulo/Makefile.mk new file mode 100644 index 000000000000..91f031e7a474 --- /dev/null +++ b/src/mainboard/google/brya/variants/trulo/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c new file mode 100644 index 000000000000..1a6d1b14662d --- /dev/null +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* A14 : USB_OC1# ==> USB_A0_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A14, NONE, NF1, LOCK_CONFIG), + /* A15 : USB_OC2# ==> USB_A1_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A15, NONE, NF1, LOCK_CONFIG), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* TODO */ +}; + +/* Fill romstage gpio configuration */ +static const struct pad_config romstage_gpio_table[] = { + /* TODO */ +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + /* TODO */ +}; +DECLARE_CROS_GPIOS(cros_gpios); + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index ee861420f699..9285c3304305 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/alderlake - device domain 0 on - end + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + + device domain 0 on + end end diff --git a/src/mainboard/google/brya/variants/xol/Makefile.mk b/src/mainboard/google/brya/variants/xol/Makefile.mk index c346b0abc938..d85ce1bfbe2a 100644 --- a/src/mainboard/google/brya/variants/xol/Makefile.mk +++ b/src/mainboard/google/brya/variants/xol/Makefile.mk @@ -4,3 +4,4 @@ bootblock-y += gpio.c romstage-y += memory.c ramstage-y += gpio.c ramstage-y += ramstage.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 168d9821d053..39478a148912 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -195,6 +195,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */ diff --git a/src/mainboard/google/brya/variants/xol/include/variant/gpio.h b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h index c4fe342621e6..f62197dfe618 100644 --- a/src/mainboard/google/brya/variants/xol/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/xol/include/variant/gpio.h @@ -5,4 +5,6 @@ #include <baseboard/gpio.h> +#define CAM_PWR GPP_A17 + #endif diff --git a/src/mainboard/google/brya/variants/xol/memory.c b/src/mainboard/google/brya/variants/xol/memory.c index f8afa73e1459..b0cbaad72fd9 100644 --- a/src/mainboard/google/brya/variants/xol/memory.c +++ b/src/mainboard/google/brya/variants/xol/memory.c @@ -63,9 +63,11 @@ static const struct mb_cfg variant_memcfg = { .ccc_config = 0xff, }, + .LpDdrDqDqsReTraining = 1, + .ect = 1, /* Early Command Training */ - .UserBd = BOARD_TYPE_MOBILE, + .UserBd = BOARD_TYPE_ULT_ULX, }; const struct mb_cfg *variant_memory_params(void) diff --git a/src/mainboard/google/brya/variants/xol/overridetree.cb b/src/mainboard/google/brya/variants/xol/overridetree.cb index 80d15feb6221..d73702c4bbe2 100644 --- a/src/mainboard/google/brya/variants/xol/overridetree.cb +++ b/src/mainboard/google/brya/variants/xol/overridetree.cb @@ -3,6 +3,10 @@ fw_config option STORAGE_UFS 0 option STORAGE_NVME 1 end + field WIFI_SAR_ID 31 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 + end end chip soc/intel/alderlake @@ -25,6 +29,12 @@ chip soc/intel/alderlake # display flickering issue. register "disable_dynamic_tccold_handshake" = "true" + register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 55, + .tdp_pl4 = 114, + }" + register "tcc_offset" = "6" # TCC of 94 register "platform_pmax" = "122" @@ -132,7 +142,7 @@ chip soc/intel/alderlake .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 650, - .fall_time_ns = 400, + .fall_time_ns = 200, .data_hold_time_ns = 50, }, }" diff --git a/src/mainboard/google/brya/variants/xol/variant.c b/src/mainboard/google/brya/variants/xol/variant.c new file mode 100644 index 000000000000..8d14715a670c --- /dev/null +++ b/src/mainboard/google/brya/variants/xol/variant.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <baseboard/variants.h> +#include <variant/gpio.h> +#include <chip.h> +#include <fw_config.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + /* Add board-specific MS0X entries */ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(CAM_PWR); + if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(CAM_PWR); +} diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index f3960ca654c9..cb34f3c55edd 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -25,22 +25,6 @@ chip northbridge/intel/sandybridge # Force double refresh rate register "ddr_refresh_rate_config" = "DDR_REFRESH_RATE_DOUBLE" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0080 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref peg10 off end # PCIe Bridge for discrete graphics @@ -69,6 +53,19 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, 0, -1}, /* P0: Right USB 3.0 #1 (no OC) */ + {1, 0, -1}, /* P1: Right USB 3.0 #2 (no OC) */ + {1, 0, -1}, /* P2: Camera (no OC) */ + /* P3-P8: Empty */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, + {0, 0, -1}, {0, 0, -1}, {0, 0, -1}, + {1, 1, -1}, /* P9: Left USB 1 (no OC) */ + {1, 0, -1}, /* P10: Mini PCIe - WLAN / BT (no OC) */ + /* P11-P13: Empty */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1} + }" + device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 @@ -101,7 +98,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index f63d3c3d75fc..8d07a38b14ee 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -44,24 +44,6 @@ void mainboard_late_rcba_config(void) DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, -1 }, /* P0: Right USB 3.0 #1 (no OC) */ - { 1, 0, -1 }, /* P1: Right USB 3.0 #2 (no OC) */ - { 1, 0, -1 }, /* P2: Camera (no OC) */ - { 0, 0, -1 }, /* P3: Empty */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 0, 0, -1 }, /* P8: Empty */ - { 1, 1, -1 }, /* P9: Left USB 1 (no OC) */ - { 1, 0, -1 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index 8c291ce2799c..6baaeac3db0a 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -9,6 +9,7 @@ config BOARD_GOOGLE_KINGLER_COMMON def_bool BOARD_GOOGLE_KINGLER || \ BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ + BOARD_GOOGLE_SQUIRTLE || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB @@ -27,9 +28,9 @@ config BOARD_GOOGLE_STARYU_COMMON if BOARD_GOOGLE_CORSOLA_COMMON config CORSOLA_SDCARD_INIT - def_bool BOARD_GOOGLE_MAGIKARP || \ + def_bool BOARD_GOOGLE_KINGLER_COMMON || \ + BOARD_GOOGLE_MAGIKARP || \ BOARD_GOOGLE_TENTACRUEL || \ - BOARD_GOOGLE_KINGLER_COMMON || \ BOARD_GOOGLE_WUGTRIO config BOARD_SPECIFIC_OPTIONS @@ -56,6 +57,7 @@ config BOARD_SPECIFIC_OPTIONS BOARD_GOOGLE_KINGLER || \ BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ + BOARD_GOOGLE_SQUIRTLE || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB select DRIVER_PARADE_PS8640 if BOARD_GOOGLE_KRABBY || \ @@ -82,19 +84,20 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string + default "Chinchou" if BOARD_GOOGLE_CHINCHOU default "Kingler" if BOARD_GOOGLE_KINGLER default "Krabby" if BOARD_GOOGLE_KRABBY default "Kyogre" if BOARD_GOOGLE_KYOGRE - default "Steelix" if BOARD_GOOGLE_STEELIX - default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Magikarp" if BOARD_GOOGLE_MAGIKARP - default "Voltorb" if BOARD_GOOGLE_VOLTORB - default "Starmie" if BOARD_GOOGLE_STARMIE default "Ponyta" if BOARD_GOOGLE_PONYTA - default "Chinchou" if BOARD_GOOGLE_CHINCHOU - default "Wugtrio" if BOARD_GOOGLE_WUGTRIO default "Skitty" if BOARD_GOOGLE_SKITTY + default "Squirtle" if BOARD_GOOGLE_SQUIRTLE + default "Starmie" if BOARD_GOOGLE_STARMIE + default "Steelix" if BOARD_GOOGLE_STEELIX + default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Veluza" if BOARD_GOOGLE_VELUZA + default "Voltorb" if BOARD_GOOGLE_VOLTORB + default "Wugtrio" if BOARD_GOOGLE_WUGTRIO config BOOT_DEVICE_SPI_FLASH_BUS int diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index cbe1928a6fa1..ab6a132868ea 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -8,32 +8,35 @@ config BOARD_GOOGLE_KINGLER config BOARD_GOOGLE_KYOGRE bool "-> Kyogre" +config BOARD_GOOGLE_PONYTA + bool "-> Ponyta" + +config BOARD_GOOGLE_SQUIRTLE + bool "-> Squirtle" + config BOARD_GOOGLE_STEELIX bool "-> Steelix" config BOARD_GOOGLE_VOLTORB bool "-> Voltorb" -config BOARD_GOOGLE_PONYTA - bool "-> Ponyta" - comment "Krabby" +config BOARD_GOOGLE_CHINCHOU + bool "-> Chinchou" + config BOARD_GOOGLE_KRABBY bool "-> Krabby" -config BOARD_GOOGLE_TENTACRUEL - bool "-> Tentacruel" - config BOARD_GOOGLE_MAGIKARP bool "-> Magikarp" -config BOARD_GOOGLE_CHINCHOU - bool "-> Chinchou" - config BOARD_GOOGLE_SKITTY bool "-> Skitty" +config BOARD_GOOGLE_TENTACRUEL + bool "-> Tentacruel" + config BOARD_GOOGLE_VELUZA bool "-> Veluza" diff --git a/src/mainboard/google/corsola/devicetree.cb b/src/mainboard/google/corsola/devicetree.cb index 300ba7b8a78d..bb7f003c0372 100644 --- a/src/mainboard/google/corsola/devicetree.cb +++ b/src/mainboard/google/corsola/devicetree.cb @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only fw_config + field SECONDARY_USB 27 + option DISABLED 0 + option ENABLED 1 + end field AUDIO_AMP 28 29 option AMP_ALC1019 0 option AMP_ALC5645 1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index a1ba5f9356b4..1a0ab3c9171b 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -53,6 +53,11 @@ static void mainboard_init(struct device *dev) setup_usb_host(); + if (fw_config_probe(FW_CONFIG(SECONDARY_USB, ENABLED))) { + /* Change host to USB2 port0 for initialization */ + setup_usb_secondary_host(); + } + if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO_AMP, AMP_ALC1019))) configure_alc1019(); diff --git a/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk b/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk index 892563e28d82..3e346616922d 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk @@ -5,3 +5,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-5.hex # ID = 1(0b0001) Parts = SDVB8D8A34XGCL3N3T diff --git a/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt index 6a92eb9c1c57..6bd852744b7d 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt @@ -9,3 +9,4 @@ K4U6E3S4AA-MGCR 0 (0000) H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AB-MGCL 0 (0000) +SDVB8D8A34XGCL3N3T 1 (0001) diff --git a/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt index 86b3025417b3..f8d00775e731 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt @@ -3,3 +3,4 @@ K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E512M32D1NP-046 WT:B K4U6E3S4AB-MGCL +SDVB8D8A34XGCL3N3T diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 5e39c884e41f..2c25e60a1bfc 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -134,6 +134,15 @@ chip soc/intel/jasperlake end end chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on + probe DB_PORTS DB_PORTS_1C_1A + probe DB_PORTS DB_PORTS_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(2, 2)" @@ -152,6 +161,15 @@ chip soc/intel/jasperlake device usb 2.6 on end end chip drivers/usb/acpi + register "desc" = ""Right Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on + probe DB_PORTS DB_PORTS_1C_1A + probe DB_PORTS DB_PORTS_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" register "group" = "ACPI_PLD_GROUP(2, 2)" diff --git a/src/mainboard/google/dedede/variants/kracko/ramstage.c b/src/mainboard/google/dedede/variants/kracko/ramstage.c index 255e58557ec0..459fc77dc1b2 100644 --- a/src/mainboard/google/dedede/variants/kracko/ramstage.c +++ b/src/mainboard/google/dedede/variants/kracko/ramstage.c @@ -11,7 +11,23 @@ static void ext_vr_update(void) cfg->disable_external_bypass_vr = 1; } +static void usb_port_update(void) +{ + struct soc_intel_jasperlake_config *cfg = config_of_soc(); + + if (fw_config_is_provisioned() && + fw_config_probe(FW_CONFIG(DB_PORTS, DB_PORTS_NONE))) { + /* Disable USB C1 port */ + cfg->usb2_ports[1].enable = 0; + cfg->usb3_ports[1].enable = 0; + /* Disable USB A1 port */ + cfg->usb2_ports[3].enable = 0; + cfg->usb3_ports[3].enable = 0; + } +} + void variant_devtree_update(void) { ext_vr_update(); + usb_port_update(); } diff --git a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk index 8b4d130e9621..90505f8f5f46 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/pirika/memory/Makefile.mk @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, MT53E512M32D1NP-046 WT:B, H54G46CYRBX267 SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4CBAM-ML-A diff --git a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt index 76ab7e0c78de..c62f08b15f5d 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/dram_id.generated.txt @@ -1,10 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# /tmp/go-build469829719/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +# /tmp/go-build796126413/b001/exe/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) K4U6E3S4AA-MGCR 0 (0000) K4U6E3S4AB-MGCL 0 (0000) CXDB4CBAM-ML-A 1 (0001) +MT53E512M32D1NP-046 WT:B 0 (0000) +H54G46CYRBX267 0 (0000) diff --git a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt index b93cdbf0db89..c87f6c1ca2c5 100644 --- a/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/pirika/memory/mem_parts_used.txt @@ -2,3 +2,5 @@ H9HCNNNBKMMLXR-NEE K4U6E3S4AA-MGCR K4U6E3S4AB-MGCL CXDB4CBAM-ML-A +MT53E512M32D1NP-046 WT:B +H54G46CYRBX267 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d6200d9a4863..86aab95ab1ff 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -216,10 +216,8 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on + device ref igpu on chip drivers/gfx/generic register "device_count" = "1" register "device[0].name" = ""LCD0"" @@ -233,18 +231,16 @@ chip soc/intel/cannonlake register "device[0].privacy.disable_function" = ""\\_SB.PCI0.LPCB.EC0.DPVX"" device generic 0 on end end - end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub + end + device ref dptf on end + device ref thermal on end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""drallion_ish.bin"" device generic 0 on end end end - device pci 14.0 on + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -320,16 +316,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" @@ -389,8 +383,8 @@ chip soc/intel/cannonlake register "device_present_gpio_invert" = "1" device i2c 34 on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -405,59 +399,29 @@ chip soc/intel/cannonlake register "detect" = "1" device i2c 15 on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 on + end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on + end + device ref pcie_rp9 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" - end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + end + device ref pcie_rp13 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref uart0 on end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h index 89c5175d9cf1..3298d9c322b8 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/hda_verb.h @@ -18,14 +18,14 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x12, 0xb7a60130), - AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x16, 0x40000000), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40c00001), AZALIA_PIN_CFG(0, 0x1e, 0x421212f2), AZALIA_PIN_CFG(0, 0x21, 0x04211020), diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 906f98e0bb6d..31a9461d99e2 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <boardid.h> +#include <device/dram/ddr3.h> #include <string.h> #include <ec/google/chromeec/ec.h> #include <fsp/soc_binding.h> @@ -37,7 +38,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3; /* Limit K4EBE304EB-EGCF memory to 1600MHz for stability */ if (board_id() < 6 && mainboard_get_spd_index() == 5) { diff --git a/src/mainboard/google/eve/spd/spd.c b/src/mainboard/google/eve/spd/spd.c index c053177d55d3..2f0d2e42181f 100644 --- a/src/mainboard/google/eve/spd/spd.c +++ b/src/mainboard/google/eve/spd/spd.c @@ -2,8 +2,10 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <gpio.h> #include <soc/romstage.h> +#include <spd.h> #include <string.h> #include "../gpio.h" @@ -18,7 +20,7 @@ static void mainboard_print_spd_info(uint8_t spd[]) const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; + char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 }; int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; @@ -30,21 +32,21 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Module type */ printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: + switch (spd[SPD_MEMORY_TYPE]) { + case SPD_MEMORY_TYPE_SDRAM_DDR3: printk(BIOS_INFO, "DDR3\n"); break; - case SPD_DRAM_LPDDR3: + case SPD_MEMORY_TYPE_LPDDR3_INTEL: printk(BIOS_INFO, "LPDDR3\n"); break; default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]); break; } /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; + memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN); + spd_name[SPD_DDR3_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); printk(BIOS_INFO, @@ -86,16 +88,16 @@ uintptr_t mainboard_get_spd_data(void) die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); spd_index = 1; } - spd_index *= SPD_LEN; + spd_index *= SPD_SIZE_MAX_DDR3; mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); return (uintptr_t)(spd_file + spd_index); diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 7b53fd43c0e3..847160de9cf7 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -3,18 +3,10 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 #define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 int mainboard_get_spd_index(void); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 0d631cc5e4a4..795d96ef9b8a 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -14,7 +14,7 @@ #include <smbios.h> #include <soc/pci_devs.h> #include <soc/nhlt.h> -#include <string.h> +#include <stdio.h> #include <timer.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 35b53e26af95..64b363db2c37 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variant.h> +#include <device/dram/ddr3.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/romstage.h> @@ -30,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) }; const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3; mem_cfg->DqPinsInterleaved = FALSE; spd_memory_init_params(mupd, spd_idx); diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index a6e655bbef7a..edbedffa654c 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -2,8 +2,10 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <gpio.h> #include <soc/romstage.h> +#include <spd.h> #include <string.h> #include <baseboard/variant.h> @@ -19,7 +21,7 @@ static void mainboard_print_spd_info(uint8_t spd[]) const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; + char spd_name[SPD_DDR3_PART_LEN + 1] = { 0 }; int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; @@ -31,21 +33,21 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Module type */ printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: + switch (spd[SPD_MEMORY_TYPE]) { + case SPD_MEMORY_TYPE_SDRAM_DDR3: printk(BIOS_INFO, "DDR3\n"); break; - case SPD_DRAM_LPDDR3: + case SPD_MEMORY_TYPE_LPDDR3_INTEL: printk(BIOS_INFO, "LPDDR3\n"); break; default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_MEMORY_TYPE]); break; } /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; + memcpy(spd_name, &spd[SPD_DDR3_PART_NUM], SPD_DDR3_PART_LEN); + spd_name[SPD_DDR3_PART_LEN] = 0; printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); printk(BIOS_INFO, @@ -83,16 +85,16 @@ void spd_memory_init_params(FSPM_UPD *mupd, int spd_index) die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 1 - old hardware?\n"); spd_index = 1; } - const size_t spd_offset = spd_index * SPD_LEN; + const size_t spd_offset = spd_index * SPD_SIZE_MAX_DDR3; /* Make sure a valid SPD was found */ if (spd_file[spd_offset] == 0) die("Invalid SPD data."); diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index 764958b86afd..8e1a5f43c377 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -3,17 +3,9 @@ #ifndef MAINBOARD_SPD_H #define MAINBOARD_SPD_H -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 #define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 #endif diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 64f45dea9e9e..02790b0762a3 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -5,7 +5,7 @@ #include <console/console.h> #include <gpio.h> #include <soc/sdram.h> -#include <string.h> +#include <stdio.h> #include <types.h> static const char *sdram_configs[] = { diff --git a/src/mainboard/google/jecht/hda_verb.c b/src/mainboard/google/jecht/hda_verb.c index 3609de92743a..f55b0c5da703 100644 --- a/src/mainboard/google/jecht/hda_verb.c +++ b/src/mainboard/google/jecht/hda_verb.c @@ -19,16 +19,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD - Disabled */ - AZALIA_PIN_CFG(0, 0x14, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -38,10 +38,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1A, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1A, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1B, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1B, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -51,7 +51,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1D, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1E, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1E, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 427f094677a9..685414e64776 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/acpi.h> -#include <string.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -16,6 +15,7 @@ #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/southbridge.h> +#include <stdio.h> #include <amdblocks/acpimmio.h> #include <variant/ec.h> #include <variant/thermal.h> diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 69047fa4a22a..22f8150d5e9e 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -19,7 +19,7 @@ #include <soc/mtcmos.h> #include <soc/spm.h> #include <soc/usb.h> -#include <string.h> +#include <stdio.h> #include "gpio.h" #include "panel.h" diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 88983dcfc676..028db5e52803 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 1, 3, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge @@ -65,6 +49,23 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + { 0, 0, -1 }, /* P0: Empty */ + { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ + { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ + { 1, 0, -1 }, /* P3: SDCARD (no OC) */ + { 0, 0, -1 }, /* P4: Empty */ + { 1, 0, -1 }, /* P5: WWAN (no OC) */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, -1 }, /* P8: Camera (no OC) */ + { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ + { 0, 0, -1 }, /* P10: Empty */ + { 0, 0, -1 }, /* P11: Empty */ + { 0, 0, -1 }, /* P12: Empty */ + { 0, 0, -1 }, /* P13: Empty */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index e40531dac153..2d20ac03a9f0 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -63,24 +63,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, -1 }, /* P3: SDCARD (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 1, 0, -1 }, /* P5: WWAN (no OC) */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: Camera (no OC) */ - { 1, 0, -1 }, /* P9: Bluetooth (no OC) */ - { 0, 0, -1 }, /* P10: Empty */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { /* LINK has 2 channels of memory down */ diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 49b40b95b62b..1509f0a1cc09 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 0, 3, 0x0000 }, - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 0, 3, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on device ref host_bridge on end # host bridge device ref igd on end # vga controller @@ -56,6 +40,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x1" + register "usb_port_config" = "{ + {0, 0, -1}, /* P0: Empty */ + {1, 0, 0}, /* P1: Left USB 1 (OC0) */ + {1, 0, 1}, /* P2: Left USB 2 (OC1) */ + {1, 0, 1}, /* P3: Left USB 3 (OC1) */ + {0, 0, -1}, /* P4-P7: Empty */ + {0, 0, -1}, + {0, 0, -1}, + {0, 0, -1}, + /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ + {1, 0, -1}, /* P8: MiniPCIe (WLAN) (no OC) */ + {0, 0, -1}, /* P9: Empty */ + {1, 0, -1}, /* P10: Camera (no OC) */ + {0, 0, -1}, {0, 0, -1}, {0, 0, -1} + }" + # EC range is 0xFD60 (EC_IO) and 0x68/0x6C register "gen1_dec" = "0x0004fd61" register "gen2_dec" = "0x00040069" @@ -89,7 +89,7 @@ chip northbridge/intel/sandybridge end # LPC bridge device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f91b7d9f459d..077cb64576cb 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -50,22 +50,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 0, 0, -1 }, /* P0: Empty */ - { 1, 0, 0 }, /* P1: Left USB 1 (OC0) */ - { 1, 0, 1 }, /* P2: Left USB 2 (OC1) */ - { 1, 0, 1 }, /* P3: Left USB 3 (OC1) */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - /* Empty and onboard Ports 8-13, set to un-used pin OC4 */ - { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */ - { 0, 0, -1 }, /* P9: Empty */ - { 1, 0, -1 }, /* P10: Camera (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; diff --git a/src/mainboard/google/parrot/hda_verb.c b/src/mainboard/google/parrot/hda_verb.c index 1c838a390b82..9b8d62174d26 100644 --- a/src/mainboard/google/parrot/hda_verb.c +++ b/src/mainboard/google/parrot/hda_verb.c @@ -29,7 +29,7 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ // group 1, front left/right @@ -39,10 +39,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 2, cap 1 @@ -52,7 +52,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x04a71021), /* Pin Complex (NID 0x1A) LINE1 PORTC */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE */ // group 2, cap 0 @@ -69,7 +69,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORTA? */ // group1, diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index aaa51dd84026..7bdfb5e17719 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -13,7 +13,7 @@ #include <intelblocks/power_limit.h> #include <smbios.h> #include <soc/ramstage.h> -#include <string.h> +#include <stdio.h> #include <variant/sku.h> #include <gpio.h> #include <delay.h> diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 7350fb05c801..b77513ba56f4 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -6,7 +6,7 @@ #include <device/device.h> #include <device/pci_ops.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> #include <variant/sku.h> #define R_PCH_OC_WDT_CTL 0x54 diff --git a/src/mainboard/google/poppy/variants/rammus/mainboard.c b/src/mainboard/google/poppy/variants/rammus/mainboard.c index 90cf7cec611f..7eafebcff076 100644 --- a/src/mainboard/google/poppy/variants/rammus/mainboard.c +++ b/src/mainboard/google/poppy/variants/rammus/mainboard.c @@ -3,7 +3,7 @@ #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> #include <sar.h> #define SKU_UNKNOWN 0xFFFFFFFF diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 28496b15badf..b9aa870c109e 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -2,6 +2,7 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> #include <soc/gpio.h> #include <soc/mrc_wrapper.h> #include <soc/romstage.h> @@ -38,7 +39,7 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) if (dual_channel_config & (1 << ram_id)) *dual = 1; - return &spd_file_content[SPD_SIZE * ram_id]; + return &spd_file_content[SPD_SIZE_MAX_DDR3 * ram_id]; } void mainboard_fill_mrc_params(struct mrc_params *mp) @@ -52,7 +53,7 @@ void mainboard_fill_mrc_params(struct mrc_params *mp) if (!spd_file) die("SPD data not found."); - spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, + spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE_MAX_DDR3, &dual_channel); mp->mainboard.dram_type = DRAM_DDR3L; diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h index c9cf327586d2..47e0a2671fed 100644 --- a/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 1) | (1 << 3) | (1 << 5); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h index dcecbbeddc37..33ad2e62662a 100644 --- a/src/mainboard/google/rambi/variants/candy/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/candy/include/variant/variant.h @@ -24,7 +24,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7) | (1 << 10); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h index c41b4aafae71..5105201114ee 100644 --- a/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h index 8944e7b1505b..60c424d149d0 100644 --- a/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h b/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h index 17d9acc35368..1536601f8cc1 100644 --- a/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/expresso/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h index d581de8e5f9b..e26402330533 100644 --- a/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h @@ -24,7 +24,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 6) | (1 << 7); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h index 50e9ad872543..4df3c8d83c3a 100644 --- a/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 6) | (1 << 7); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h index 2e00104265f8..b357c6f52679 100644 --- a/src/mainboard/google/rambi/variants/heli/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/heli/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 6) | (1 << 7); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h index 25c3f373fbe3..ea3e8927923f 100644 --- a/src/mainboard/google/rambi/variants/kip/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/kip/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h index 8a48c11e91e4..7b20daf1c787 100644 --- a/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h index 4d8eebb5a0f1..16d39710997d 100644 --- a/src/mainboard/google/rambi/variants/orco/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/orco/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h index 51051e25918b..d74551e270a3 100644 --- a/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h index 46ee249f411a..a9bd04c942a3 100644 --- a/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/variant.h @@ -17,7 +17,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h index 51051e25918b..d74551e270a3 100644 --- a/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h index 8a48c11e91e4..7b20daf1c787 100644 --- a/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/variant.h @@ -20,7 +20,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 6); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h index 97094a952cb2..f5ec6a613d07 100644 --- a/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/variant.h @@ -16,7 +16,6 @@ static const uint32_t dual_channel_config = (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h index f4aa2137274d..223823366607 100644 --- a/src/mainboard/google/rambi/variants/winky/include/variant/variant.h +++ b/src/mainboard/google/rambi/variants/winky/include/variant/variant.h @@ -18,7 +18,6 @@ static const uint32_t dual_channel_config = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); -#define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 #define GPIO_SSUS_39_PAD 58 diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index ff3bb36e09c2..964fc1ce7463 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -10,7 +10,7 @@ #include <nhlt.h> #include <smbios.h> #include <soc/nhlt.h> -#include <string.h> +#include <stdio.h> #include <variant/ec.h> #include <variant/gpio.h> diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 5e019ee38d46..9ee0bc066392 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -122,6 +122,11 @@ config BOARD_GOOGLE_OVIS4ES config BOARD_GOOGLE_REX0 select BOARD_GOOGLE_MODEL_REX +config BOARD_GOOGLE_REX64 + select BOARD_GOOGLE_MODEL_REX + select HAVE_X86_64_SUPPORT + select USE_X86_64_SUPPORT + config BOARD_GOOGLE_REX_EC_ISH select BOARD_GOOGLE_MODEL_REX_EC_ISH @@ -182,6 +187,7 @@ config MAINBOARD_FAMILY config MAINBOARD_PART_NUMBER default "Rex" if BOARD_GOOGLE_REX0 + default "Rex64" if BOARD_GOOGLE_REX64 default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH default "Rex4ES" if BOARD_GOOGLE_REX4ES default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index 6aca8faca2f6..f4fed2a82855 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -32,6 +32,9 @@ config BOARD_GOOGLE_REX4ES config BOARD_GOOGLE_REX4ES_EC_ISH bool "-> Rex4ES EC ISH" +config BOARD_GOOGLE_REX64 + bool "-> Rex 64" + config BOARD_GOOGLE_SCREEBO bool "-> Screebo" diff --git a/src/mainboard/google/rex/mainboard.c b/src/mainboard/google/rex/mainboard.c index bf489ff52831..9157abbe38f1 100644 --- a/src/mainboard/google/rex/mainboard.c +++ b/src/mainboard/google/rex/mainboard.c @@ -9,6 +9,7 @@ #include <ec/ec.h> #include <fw_config.h> #include <soc/ramstage.h> +#include <stdio.h> #include <stdlib.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h index bd3d535c16a9..8a97d00deb98 100644 --- a/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/rex/variants/baseboard/include/baseboard/variants.h @@ -24,6 +24,9 @@ int variant_memory_sku(void); bool variant_is_half_populated(void); void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config); +/* Get soc power limit config struct for current CPU sku */ +struct soc_power_limits_config *variant_get_soc_power_limit_config(void); + enum s0ix_entry { S0IX_EXIT, S0IX_ENTRY, diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb index aace5adcf4cb..7cb10d278c6a 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb @@ -86,6 +86,7 @@ chip soc/intel/meteorlake device domain 0 on device ref igpu on end device ref dtt on end + device ref vpu on end device ref ioe_shared_sram on end device ref xhci on end device ref pmc_shared_sram on end diff --git a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c index 1eec1ec01b9e..2798be6c7b94 100644 --- a/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c +++ b/src/mainboard/google/rex/variants/baseboard/ovis/ramstage.c @@ -1,8 +1,35 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <intelblocks/power_limit.h> +#include <soc/pci_devs.h> + +struct soc_power_limits_config *variant_get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + size_t i = 0; + + if (mchid == 0xffff) + return NULL; + + for (i = 0; i < ARRAY_SIZE(cpuid_to_mtl); i++) { + if (mchid == cpuid_to_mtl[i].cpu_id && tdp == cpuid_to_mtl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_mtl[i].limits]; + } + } + + if (i == ARRAY_SIZE(cpuid_to_mtl)) { + printk(BIOS_ERR, "Cannot find correct ovis sku index.\n"); + return NULL; + } + + return NULL; +} /* * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 58c1719b4889..1a80e2aecb20 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -97,6 +97,7 @@ chip soc/intel/meteorlake device domain 0 on device ref igpu on end device ref dtt on end + device ref vpu on end device ref ioe_shared_sram on end device ref xhci on end device ref pmc_shared_sram on end diff --git a/src/mainboard/google/rex/variants/deku/Makefile.mk b/src/mainboard/google/rex/variants/deku/Makefile.mk index 91f031e7a474..090dd5be738d 100644 --- a/src/mainboard/google/rex/variants/deku/Makefile.mk +++ b/src/mainboard/google/rex/variants/deku/Makefile.mk @@ -3,3 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c index 52cb2e010304..55464dd46806 100644 --- a/src/mainboard/google/rex/variants/deku/gpio.c +++ b/src/mainboard/google/rex/variants/deku/gpio.c @@ -27,99 +27,99 @@ static const struct pad_config gpio_table[] = { /* GPP_A12 : [] ==> LAN1_ISOLATE_R_ODL */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* GPP_A13 : net NC is not present in the given design */ - PAD_NC(GPP_A13, UP_20K), + PAD_NC(GPP_A13, NONE), /* GPP_A14 : net NC is not present in the given design */ - PAD_NC(GPP_A14, UP_20K), + PAD_NC(GPP_A14, NONE), /* GPP_A15 : net NC is not present in the given design */ - PAD_NC(GPP_A15, UP_20K), + PAD_NC(GPP_A15, NONE), /* GPP_A16 : [] ==> ESPI_SOC_ALERT_L */ PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_A18 : net NC is not present in the given design */ - PAD_NC(GPP_A18, UP_20K), + PAD_NC(GPP_A18, NONE), /* GPP_A21 : [] ==> SOC_GPP_A21 */ - PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A21, NONE), /* GPP_B00 : net NC is not present in the given design */ - PAD_NC(GPP_B00, UP_20K), + PAD_NC(GPP_B00, NONE), /* GPP_B01 : [] ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_B01, 1, DEEP), /* GPP_B02 : net NC is not present in the given design */ - PAD_NC(GPP_B02, UP_20K), + PAD_NC(GPP_B02, NONE), /* GPP_B03 : net NC is not present in the given design */ - PAD_NC(GPP_B03, UP_20K), + PAD_NC(GPP_B03, NONE), /* GPP_B04 : [GPP_B04_STRAP] ==> Component NC */ - PAD_NC(GPP_B04, UP_20K), + PAD_NC(GPP_B04, NONE), /* GPP_B05 : net NC is not present in the given design */ - PAD_NC(GPP_B05, UP_20K), + PAD_NC(GPP_B05, NONE), /* GPP_B06 : net NC is not present in the given design */ - PAD_NC(GPP_B06, UP_20K), + PAD_NC(GPP_B06, NONE), /* GPP_B07 : net NC is not present in the given design */ - PAD_NC(GPP_B07, UP_20K), + PAD_NC(GPP_B07, NONE), /* GPP_B08 : [] ==> PWM_BUZZER */ PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPP_B09 : net NC is not present in the given design */ - PAD_NC(GPP_B09, UP_20K), + PAD_NC(GPP_B09, NONE), /* GPP_B10 : [] ==> WIFI_DISABLE_L */ PAD_CFG_GPO(GPP_B10, 1, DEEP), /* GPP_B11 : net NC is not present in the given design */ - PAD_NC(GPP_B11, UP_20K), + PAD_NC(GPP_B11, NONE), /* GPP_B12 : [] ==> SLP_S0_R_L */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 : [] ==> PLT_PCIE_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 : [GPP_B14_STRAP] ==> Component NC */ - PAD_NC(GPP_B14, UP_20K), + PAD_NC(GPP_B14, NONE), /* GPP_B15 : [] ==> USB_A_OC_ODL */ PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), /* GPP_B16 : net NC is not present in the given design */ - PAD_NC(GPP_B16, UP_20K), + PAD_NC(GPP_B16, NONE), /* GPP_B17 : net NC is not present in the given design */ - PAD_NC(GPP_B17, UP_20K), + PAD_NC(GPP_B17, NONE), /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), /* GPP_B20 : net NC is not present in the given design */ - PAD_NC(GPP_B20, UP_20K), + PAD_NC(GPP_B20, NONE), /* GPP_B21 : net NC is not present in the given design */ - PAD_NC(GPP_B21, UP_20K), + PAD_NC(GPP_B21, NONE), /* GPP_B22 : [] ==> USB_C_FORCE_PWR */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 : net NC is not present in the given design */ - PAD_NC(GPP_B23, UP_20K), + PAD_NC(GPP_B23, NONE), /* GPP_C00 : net NC is not present in the given design */ - PAD_NC(GPP_C00, UP_20K), + PAD_NC(GPP_C00, NONE), /* GPP_C01 : net NC is not present in the given design */ - PAD_NC(GPP_C01, UP_20K), + PAD_NC(GPP_C01, NONE), /* GPP_C02 : [GPP_C02_STRAP] ==> Component NC */ - PAD_NC(GPP_C02, UP_20K), + PAD_NC(GPP_C02, NONE), /* GPP_C03 : net NC is not present in the given design */ - PAD_NC(GPP_C03, UP_20K), + PAD_NC(GPP_C03, NONE), /* GPP_C04 : net NC is not present in the given design */ - PAD_NC(GPP_C04, UP_20K), + PAD_NC(GPP_C04, NONE), /* GPP_C05 : [GPP_C05_STRAP] ==> Component NC */ - PAD_NC(GPP_C05, UP_20K), + PAD_NC(GPP_C05, NONE), /* GPP_C06 : net NC is not present in the given design */ - PAD_NC(GPP_C06, UP_20K), + PAD_NC(GPP_C06, NONE), /* GPP_C07 : net NC is not present in the given design */ - PAD_NC(GPP_C07, UP_20K), + PAD_NC(GPP_C07, NONE), /* GPP_C08 : [] ==> SOCHOT_ODL */ PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), /* GPP_C09 : [] ==> MISC_SYNC_OD */ PAD_CFG_GPI(GPP_C09, NONE, DEEP), /* GPP_C10 : net NC is not present in the given design*/ - PAD_NC(GPP_C10, UP_20K), + PAD_NC(GPP_C10, NONE), /* GPP_C11 : [] ==> LAN1_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* GPP_C12 : net NC is not present in the given design */ - PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C12, NONE), /* GPP_C13 : [] ==> LAN0_PERST_L */ PAD_CFG_GPO_LOCK(GPP_C13, 1, LOCK_CONFIG), /* GPP_C15 : [GPP_C15_STRAP] ==> Component NC */ - PAD_NC(GPP_C15, UP_20K), + PAD_NC(GPP_C15, NONE), /* GPP_C16 : [] ==> USB_C0_LSX_TX */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GPP_C17 : [] ==> USB_C0_LSX_RX */ @@ -138,43 +138,43 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* GPP_D00 : net NC is not present in the given design */ - PAD_NC(GPP_D00, UP_20K), + PAD_NC(GPP_D00, NONE), /* GPP_D01 : [] ==> LAN1_PCIE_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_D01, NONE, DEEP, EDGE_SINGLE), /* GPP_D02 : [] ==> LAN1_PERST_L */ PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), /* GPP_D03 : net NC is not present in the given design */ - PAD_NC(GPP_D03, UP_20K), + PAD_NC(GPP_D03, NONE), /* GPP_D04 : net NC is not present in the given design */ - PAD_NC(GPP_D04, UP_20K), + PAD_NC(GPP_D04, NONE), /* GPP_D05 : [] ==> UART_DBG_TX_ISH_RX */ - PAD_NC(GPP_D05, UP_20K), + PAD_NC(GPP_D05, NONE), /* GPP_D06 : [] ==> UART_ISH_TX_DBG_RX */ - PAD_NC(GPP_D06, UP_20K), + PAD_NC(GPP_D06, NONE), /* GPP_D07 : [] ==> SOC_GPP_D07 */ - PAD_NC(GPP_D07, UP_20K), + PAD_NC(GPP_D07, NONE), /* GPP_D08 : net NC is not present in the given design */ - PAD_NC(GPP_D08, UP_20K), + PAD_NC(GPP_D08, NONE), /* GPP_D09 : net NC is not present in the given design */ - PAD_NC(GPP_D09, UP_20K), + PAD_NC(GPP_D09, NONE), /* GPP_D10 : net NC is not present in the given design */ - PAD_NC(GPP_D10, UP_20K), + PAD_NC(GPP_D10, NONE), /* GPP_D11 : net NC is not present in the given design */ - PAD_NC(GPP_D11, UP_20K), + PAD_NC(GPP_D11, NONE), /* GPP_D12 : [GPP_D12_STRAP] ==> Component NC */ - PAD_NC(GPP_D12, UP_20K), + PAD_NC(GPP_D12, NONE), /* GPP_D13 : net NC is not present in the given design */ - PAD_NC(GPP_D13, UP_20K), + PAD_NC(GPP_D13, NONE), /* GPP_D14 : net NC is not present in the given design */ - PAD_NC(GPP_D14, UP_20K), + PAD_NC(GPP_D14, NONE), /* GPP_D15 : net NC is not present in the given design */ - PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D15, NONE), /* GPP_D16 : net NC is not present in the given design */ - PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D16, NONE), /* GPP_D17 : net NC is not present in the given design */ - PAD_NC(GPP_D17, UP_20K), + PAD_NC(GPP_D17, NONE), /* GPP_D18 : net NC is not present in the given design */ - PAD_NC(GPP_D18, UP_20K), + PAD_NC(GPP_D18, NONE), /* GPP_D19 : [] ==> SSD_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* GPP_D20 : [] ==> LAN0_PCIE_CLKREQ_ODL */ @@ -182,12 +182,12 @@ static const struct pad_config gpio_table[] = { /* GPP_D21 : [] ==> WLAN_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* GPP_D22 : [] ==> SOC_DBG_BPKI3C_SDA */ - PAD_NC(GPP_D22, UP_20K), + PAD_NC(GPP_D22, NONE), /* GPP_D23 : [] ==> SOC_DBG_BPKI3C_SCL */ - PAD_NC(GPP_D23, UP_20K), + PAD_NC(GPP_D23, NONE), /* GPP_E00 : net NC is not present in the given design */ - PAD_NC(GPP_E00, UP_20K), + PAD_NC(GPP_E00, NONE), /* GPP_E01 : [] ==> MEM_STRAP_2 */ PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), /* GPP_E02 : [] ==> MEM_STRAP_1 */ @@ -199,15 +199,15 @@ static const struct pad_config gpio_table[] = { /* GPP_E05 : [] ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_E05, NONE, PLTRST, LEVEL, INVERT), /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ - PAD_NC(GPP_E06, UP_20K), + PAD_NC(GPP_E06, NONE), /* GPP_E07 : net NC is not present in the given design */ - PAD_NC(GPP_E07, UP_20K), + PAD_NC(GPP_E07, NONE), /* GPP_E08 : [] ==> USB_C0_AUX_DC_N */ PAD_CFG_NF(GPP_E08, NONE, DEEP, NF6), /* GPP_E09 : [] ==> USB_C_OC_ODL */ PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), /* GPP_E10 : net NC is not present in the given design */ - PAD_NC(GPP_E10, UP_20K), + PAD_NC(GPP_E10, NONE), /* GPP_E11 : [] ==> MEM_STRAP_0 */ PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* GPP_E12 : [] ==> MEM_STRAP_3 */ @@ -215,13 +215,13 @@ static const struct pad_config gpio_table[] = { /* GPP_E13 : [] ==> MEM_CH_SEL */ PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* GPP_E14 : net NC is not present in the given design */ - PAD_NC(GPP_E14, UP_20K), + PAD_NC(GPP_E14, NONE), /* GPP_E15 : [] ==> SOC_GPP_E15 */ - PAD_NC(GPP_E15, UP_20K), + PAD_NC(GPP_E15, NONE), /* GPP_E16 : [] ==> GPP_E16_ISH_GP10 */ - PAD_NC(GPP_E16, UP_20K), + PAD_NC(GPP_E16, NONE), /* GPP_E17 : net NC is not present in the given design */ - PAD_NC(GPP_E17, UP_20K), + PAD_NC(GPP_E17, NONE), /* GPP_E22 : [] ==> USB_C0_AUX_DC_P */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), @@ -240,13 +240,13 @@ static const struct pad_config gpio_table[] = { /* GPP_F06 : [] ==> WLAN_COEX3 */ PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* GPP_F07 : net NC is not present in the given design */ - PAD_NC(GPP_F07, UP_20K), + PAD_NC(GPP_F07, NONE), /* GPP_F08 : [] ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_F08, 1, DEEP), /* GPP_F09 : net NC is not present in the given design */ - PAD_NC(GPP_F09, UP_20K), + PAD_NC(GPP_F09, NONE), /* GPP_F10 : net NC is not present in the given design */ - PAD_NC(GPP_F10, UP_20K), + PAD_NC(GPP_F10, NONE), /* GPP_F11 : [] ==> AV_GPIO_P0 */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* GPP_F12 : [] ==> AV_GPIO_P1 */ @@ -264,30 +264,30 @@ static const struct pad_config gpio_table[] = { /* GPP_F18 : [] ==> AV_GPIO_P7 */ PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPP_F19 : [GPP_F19_STRAP] ==> Component NC */ - PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F19, NONE), /* GPP_F20 : [GPP_F20_STRAP] ==> Component NC */ - PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F20, NONE), /* GPP_F21 : [GPP_F21_STRAP] ==> Component NC */ - PAD_NC(GPP_F21, UP_20K), + PAD_NC(GPP_F21, NONE), /* GPP_F22 : [] ==> GPP_F22_ISH_GP8A */ - PAD_NC(GPP_F22, UP_20K), + PAD_NC(GPP_F22, NONE), /* GPP_F23 : [] ==> GPP_F23_ISH_GP9A */ - PAD_NC(GPP_F23, UP_20K), + PAD_NC(GPP_F23, NONE), /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ - PAD_NC(GPP_H00, UP_20K), + PAD_NC(GPP_H00, NONE), /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ - PAD_NC(GPP_H01, UP_20K), + PAD_NC(GPP_H01, NONE), /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ - PAD_NC(GPP_H02, UP_20K), + PAD_NC(GPP_H02, NONE), /* GPP_H04 : [] ==> WLAN_COEX1 */ PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* GPP_H05 : [] ==> WLAN_COEX2 */ PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), /* GPP_H06 : net NC is not present in the given design */ - PAD_NC(GPP_H06, UP_20K), + PAD_NC(GPP_H06, NONE), /* GPP_H07 : net NC is not present in the given design */ - PAD_NC(GPP_H07, UP_20K), + PAD_NC(GPP_H07, NONE), /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ @@ -295,42 +295,42 @@ static const struct pad_config gpio_table[] = { /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), /* GPP_H11 : net NC is not present in the given design */ - PAD_NC(GPP_H11, UP_20K), + PAD_NC(GPP_H11, NONE), /* GPP_H13 : [] ==> CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* GPP_H14 : [] ==> SLP_S0_GATE_R */ PAD_CFG_GPO(GPP_H14, 1, PLTRST), /* GPP_H15 : net NC is not present in the given design */ - PAD_NC(GPP_H15, UP_20K), + PAD_NC(GPP_H15, NONE), /* GPP_H16 : net NC is not present in the given design */ - PAD_NC(GPP_H16, UP_20K), + PAD_NC(GPP_H16, NONE), /* GPP_H17 : net NC is not present in the given design */ - PAD_NC(GPP_H17, UP_20K), + PAD_NC(GPP_H17, NONE), /* GPP_H19 : net NC is not present in the given design */ - PAD_NC(GPP_H19, UP_20K), + PAD_NC(GPP_H19, NONE), /* GPP_H20 : net NC is not present in the given design */ - PAD_NC(GPP_H20, UP_20K), + PAD_NC(GPP_H20, NONE), /* GPP_H21 : net NC is not present in the given design */ - PAD_NC(GPP_H21, UP_20K), + PAD_NC(GPP_H21, NONE), /* GPP_H22 : net NC is not present in the given design */ - PAD_NC(GPP_H22, UP_20K), + PAD_NC(GPP_H22, NONE), /* GPP_S00 : net NC is not present in the given design */ - PAD_NC(GPP_S00, UP_20K), + PAD_NC(GPP_S00, NONE), /* GPP_S01 : net NC is not present in the given design */ - PAD_NC(GPP_S01, UP_20K), + PAD_NC(GPP_S01, NONE), /* GPP_S02 : net NC is not present in the given design */ - PAD_NC(GPP_S02, UP_20K), + PAD_NC(GPP_S02, NONE), /* GPP_S03 : net NC is not present in the given design */ - PAD_NC(GPP_S03, UP_20K), + PAD_NC(GPP_S03, NONE), /* GPP_S04 : net NC is not present in the given design */ - PAD_NC(GPP_S04, UP_20K), + PAD_NC(GPP_S04, NONE), /* GPP_S05 : net NC is not present in the given design */ - PAD_NC(GPP_S05, UP_20K), + PAD_NC(GPP_S05, NONE), /* GPP_S06 : net NC is not present in the given design */ - PAD_NC(GPP_S06, UP_20K), + PAD_NC(GPP_S06, NONE), /* GPP_S07 : net NC is not present in the given design */ - PAD_NC(GPP_S07, UP_20K), + PAD_NC(GPP_S07, NONE), /* GPP_V00 : [] ==> BATLOW_L */ PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), @@ -359,9 +359,9 @@ static const struct pad_config gpio_table[] = { /* GPP_V14 : [] ==> SOC_WAKE_L */ PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* GPP_V22 : net NC is not present in the given design */ - PAD_NC(GPP_V22, UP_20K), + PAD_NC(GPP_V22, NONE), /* GPP_V23 : net NC is not present in the given design */ - PAD_NC(GPP_V23, UP_20K), + PAD_NC(GPP_V23, NONE), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 070f596d3d05..fcacbead862d 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -27,6 +27,15 @@ chip soc/intel/meteorlake [DDI_PORT_4] = DDI_ENABLE_HPD, }" + # Temporary setting TCC of 105C = Tj max (110) - TCC_Offset (5) + register "tcc_offset" = "5" + + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 33, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + }" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, @@ -54,9 +63,57 @@ chip soc/intel/meteorlake }, }" + register "psys_pmax_watts" = "180" + register "psys_pl2_watts" = "178" + + # As per doc 640982, Intel MTL-U 28W CPU supports FVM on GT and SA + # The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A + # For GT VR configuration + register "enable_fast_vmode[VR_DOMAIN_GT]" = "1" + register "cep_enable[VR_DOMAIN_GT]" = "1" + register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "216" # 54A + # For SA VR configuration + register "enable_fast_vmode[VR_DOMAIN_SA]" = "1" + register "cep_enable[VR_DOMAIN_SA]" = "1" + register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "108" # 27A + device domain 0 on device ref dtt on chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""IMVP_SOC"" + register "options.tsr[3].desc" = ""NVME"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 65, 1000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 28000, + .max_power = 28000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 64000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 alias dptf_policy on end end end diff --git a/src/mainboard/google/rex/variants/deku/ramstage.c b/src/mainboard/google/rex/variants/deku/ramstage.c new file mode 100644 index 000000000000..7cb324dd6793 --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/ramstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ +const struct cpu_tdp_power_limits variant_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_1, + .cpu_tdp = 28, + .pl1_min_power = 19000, + .pl1_max_power = 28000, + .pl2_min_power = 64000, + .pl2_max_power = 64000, + .pl4_power = 120000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_3, + .cpu_tdp = 28, + .pl1_min_power = 19000, + .pl1_max_power = 28000, + .pl2_min_power = 64000, + .pl2_max_power = 64000, + .pl4_power = 120000 + }, +}; + +void variant_devtree_update(void) +{ + struct soc_power_limits_config *soc_config; + struct soc_intel_meteorlake_config *config = config_of_soc(); + + soc_config = variant_get_soc_power_limit_config(); + if (soc_config == NULL) + return; + + if (config->psys_pl2_watts) { + soc_config->tdp_psyspl2 = config->psys_pl2_watts; + printk(BIOS_INFO, "Overriding PsysPL2 (%u)\n", soc_config->tdp_psyspl2); + } + + const struct cpu_tdp_power_limits *limits = variant_limits; + size_t total_entries = ARRAY_SIZE(variant_limits); + variant_update_cpu_power_limits(limits, total_entries); +} diff --git a/src/mainboard/google/rex/variants/karis/overridetree.cb b/src/mainboard/google/rex/variants/karis/overridetree.cb index c65493322d55..c74b51c69b16 100644 --- a/src/mainboard/google/rex/variants/karis/overridetree.cb +++ b/src/mainboard/google/rex/variants/karis/overridetree.cb @@ -34,10 +34,6 @@ fw_config option DISABLE 0 option ENABLE 1 end - field VPU 22 - option VPU_DIS 0 - option VPU_EN 1 - end end chip soc/intel/meteorlake @@ -585,8 +581,5 @@ chip soc/intel/meteorlake end end device ref hda on end - device ref vpu on - probe VPU VPU_EN - end end end diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 9d8f9ff75b77..d492bd17a757 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -45,6 +45,8 @@ static const struct pad_config gpio_table[] = { /* GPP_A18 : [] ==> CAM_PSW_L */ PAD_CFG_GPI_INT_LOCK(GPP_A18, NONE, EDGE_BOTH, LOCK_CONFIG), + /* GPP_A19 : [] ==> EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_A19, 1, LOCK_CONFIG), /* GPP_A21 : [] ==> WWAN_CONFIG2 */ PAD_CFG_GPI(GPP_A21, NONE, DEEP), diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 12068ce1dd88..1d1957a692c3 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -52,10 +52,6 @@ fw_config option ISH_DISABLE 0 option ISH_ENABLE 1 end - field VPU 22 - option VPU_DIS 0 - option VPU_EN 1 - end end chip soc/intel/meteorlake @@ -323,9 +319,6 @@ chip soc/intel/meteorlake end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp2 on end - device ref vpu on - probe VPU VPU_EN - end device ref tcss_xhci on chip drivers/usb/acpi device ref tcss_root_hub on diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index fdfe9843cf11..c66b5cb2b923 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -30,10 +30,6 @@ fw_config option WIFI_SAR_ID_0 0 option WIFI_SAR_ID_1 1 end - field VPU 22 - option VPU_DIS 0 - option VPU_EN 1 - end end chip soc/intel/meteorlake @@ -602,8 +598,5 @@ chip soc/intel/meteorlake end end end - device ref vpu on - probe VPU VPU_EN - end end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 93ec7cf9ca79..fcaa73024030 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -208,21 +208,17 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 on # Integrated Sensor Hub + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref ish on chip drivers/intel/ish register "firmware_name" = ""arcada_ish.bin"" device generic 0 on end end end - device pci 14.0 on + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -296,16 +292,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""WCOM48E2"" register "generic.desc" = ""Wacom Touchscreen"" @@ -319,8 +313,8 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x1" device i2c 0A on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -336,65 +330,38 @@ chip soc/intel/cannonlake register "hid_desc_reg_offset" = "0x20" device i2c 2a on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on + end + device ref sata on end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 (USB) - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on + end + device ref uart2 on end + device ref pcie_rp10 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[9]" = "1" - end # PCI Express Port 10 - device pci 1d.2 on # PCI Express Port 11 + end + device ref pcie_rp11 on register "PcieRpSlotImplemented[10]" = "1" end - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + device ref pcie_rp13 on + # x4 lanes chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end end end diff --git a/src/mainboard/google/sarien/variants/arcada/hda_verb.c b/src/mainboard/google/sarien/variants/arcada/hda_verb.c index 2ddb8acfe7a3..810ca8b815a8 100644 --- a/src/mainboard/google/sarien/variants/arcada/hda_verb.c +++ b/src/mainboard/google/sarien/variants/arcada/hda_verb.c @@ -15,14 +15,14 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x12, 0xb7a60130), - AZALIA_PIN_CFG(0, 0x13, 0x411111f0), + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x16, 0x40000000), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40c00001), AZALIA_PIN_CFG(0, 0x1e, 0x421212f2), AZALIA_PIN_CFG(0, 0x21, 0x04211020), diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b21623555012..589ea1c3aa62 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -213,16 +213,11 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "MISCCFG_GPIO_PM_CONFIG_BITS" register "gpio_pm[COMM_4]" = "MISCCFG_GPIO_PM_CONFIG_BITS" - device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on + device ref igpu on end + device ref dptf on end + device ref thermal on end + device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -308,16 +303,14 @@ chip soc/intel/cannonlake end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on + end + device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" device generic 0 on end end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on + end + device ref i2c0 on chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" @@ -349,8 +342,8 @@ chip soc/intel/cannonlake register "device_present_gpio_invert" = "1" device i2c 34 on end end - end # I2C #0 - device pci 15.1 on + end + device ref i2c1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = ""ELAN Touchpad"" @@ -358,73 +351,50 @@ chip soc/intel/cannonlake register "detect" = "1" device i2c 2c on end end - end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 on + end + device ref sata on end + device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D18_IRQ)" device i2c 50 on end end - end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 on # PCI Express Port 1 (USB) + end + device ref uart2 on end + device ref pcie_rp1 on + # USB register "PcieRpSlotImplemented[0]" = "1" end - device pci 1c.1 off end # PCI Express Port 2 (USB) - device pci 1c.2 off end # PCI Express Port 3 (USB) - device pci 1c.3 off end # PCI Express Port 4 (USB) - device pci 1c.4 off end # PCI Express Port 5 (USB) - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 + device ref pcie_rp8 on register "PcieRpSlotImplemented[7]" = "1" end - device pci 1d.0 on + device ref pcie_rp9 on chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" register "PcieRpSlotImplemented[8]" = "1" - end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 + end + device ref pcie_rp10 on register "PcieRpSlotImplemented[9]" = "1" end - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on + device ref pcie_rp13 on + # x4 lanes chip drivers/generic/bayhub register "power_saving" = "1" device pci 00.0 on end end smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" register "PcieRpSlotImplemented[12]" = "1" - end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on + end + device ref lpc_espi on chip ec/google/wilco device pnp 0c09.0 on end end - end # LPC/eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + end + device ref hda on end + device ref smbus on end + device ref gbe on end end end diff --git a/src/mainboard/google/sarien/variants/sarien/hda_verb.c b/src/mainboard/google/sarien/variants/sarien/hda_verb.c index 0972a11b8f58..feea154b662e 100644 --- a/src/mainboard/google/sarien/variants/sarien/hda_verb.c +++ b/src/mainboard/google/sarien/variants/sarien/hda_verb.c @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04a11030), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40700001), AZALIA_PIN_CFG(0, 0x1e, 0x421212f2), AZALIA_PIN_CFG(0, 0x21, 0x04211020), diff --git a/src/mainboard/google/slippy/variants/falco/hda_verb.c b/src/mainboard/google/slippy/variants/falco/hda_verb.c index b64c2dbe3b06..f79300c35028 100644 --- a/src/mainboard/google/slippy/variants/falco/hda_verb.c +++ b/src/mainboard/google/slippy/variants/falco/hda_verb.c @@ -29,10 +29,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 PORTF */ // group 1, cap 1 @@ -42,10 +42,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a71011), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 PORTE - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1d) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -55,7 +55,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HPOUT PORT-I */ // group1, diff --git a/src/mainboard/google/slippy/variants/leon/hda_verb.c b/src/mainboard/google/slippy/variants/leon/hda_verb.c index 633ccdc7419b..b71bb7592f18 100644 --- a/src/mainboard/google/slippy/variants/leon/hda_verb.c +++ b/src/mainboard/google/slippy/variants/leon/hda_verb.c @@ -29,10 +29,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -42,10 +42,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -55,7 +55,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/slippy/variants/peppy/hda_verb.c b/src/mainboard/google/slippy/variants/peppy/hda_verb.c index 575ac77573a5..36fd80bc7a14 100644 --- a/src/mainboard/google/slippy/variants/peppy/hda_verb.c +++ b/src/mainboard/google/slippy/variants/peppy/hda_verb.c @@ -19,7 +19,7 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x12) DMIC - Disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14) SPKR-OUT - Internal Speakers */ // group 1, cap 0 @@ -29,10 +29,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -49,7 +49,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1a, 0x90a70111), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -59,7 +59,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/slippy/variants/wolf/hda_verb.c b/src/mainboard/google/slippy/variants/wolf/hda_verb.c index 53d19d2c0c26..f4c5606000cf 100644 --- a/src/mainboard/google/slippy/variants/wolf/hda_verb.c +++ b/src/mainboard/google/slippy/variants/wolf/hda_verb.c @@ -34,10 +34,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Pin Complex (NID 0x17) MONO Out - Disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18) MIC1 PORTB - Disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x19) MIC2 - 3.5mm Jack */ // group2, cap 0 @@ -47,10 +47,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x03a11020), /* Pin Complex (NID 0x1A) LINE1 PORTC - Disabled */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1B) LINE2 - Disabled */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1D) PCBeep */ // eapd low on ex-amp, laptop, custom enable @@ -60,7 +60,7 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1d, 0x4015812d), /* Pin Complex (NID 0x1E) SPDIF-OUT - Disabled*/ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x21) HP-OUT - 3.5mm Jack*/ // group2, cap 1 diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 8fd19fce5876..0211921c387d 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -22,22 +22,6 @@ chip northbridge/intel/sandybridge # FIXME: Native raminit requires reduced max clock register "max_mem_clock_mhz" = "CONFIG(USE_NATIVE_RAMINIT) ? 666 : 800" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 1, 0x0000 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 1, 0x0040 }, - { 0, 1, 0x0000 }, - { 0, 1, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 0, 5, 0x0000 }, - { 1, 5, 0x0040 },}" - register "usb3.mode" = "2" # Auto register "usb3.hs_port_switch_mask" = "3" # Ports 0 & 1 register "usb3.preboot_support" = "0" # No PreOS boot support @@ -79,6 +63,23 @@ chip northbridge/intel/sandybridge # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" + register "usb_port_config" = "{ + {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, 0, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {0, 0, 0}, /* P8: Empty */ + {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, /* P10: Empty */ + {0, 0, 0}, /* P11: Empty */ + {0, 0, 0}, /* P12: Empty */ + {1, 0, -1}, /* P13: Bluetooth (no OC) */ + }" + device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index e6e62276465e..178d270da71d 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -90,21 +90,3 @@ void mainboard_early_init(int s3resume) early_ec_init(); } } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled USB oc pin length */ - {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ - {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, /* P2: Empty */ - {1, 0, -1}, /* P3: Camera (no OC) */ - {1, 0, -1}, /* P4: WLAN (no OC) */ - {1, 0, -1}, /* P5: WWAN (no OC) */ - {0, 0, 0}, /* P6: Empty */ - {0, 0, 0}, /* P7: Empty */ - {0, 0, 0}, /* P8: Empty */ - {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ - {0, 0, 0}, /* P10: Empty */ - {0, 0, 0}, /* P11: Empty */ - {0, 0, 0}, /* P12: Empty */ - {1, 0, -1}, /* P13: Bluetooth (no OC) */ -}; diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index fba96644e56f..ae7519e10e25 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -12,6 +12,7 @@ #include <intelblocks/tcss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <stdio.h> #include <variant/gpio.h> #include <vb2_api.h> diff --git a/src/mainboard/google/volteer/variants/drobit/data.vbt b/src/mainboard/google/volteer/variants/drobit/data.vbt Binary files differindex f066fbdb2a46..de72dddce2b1 100644 --- a/src/mainboard/google/volteer/variants/drobit/data.vbt +++ b/src/mainboard/google/volteer/variants/drobit/data.vbt diff --git a/src/mainboard/hp/280_g2/gma-mainboard.ads b/src/mainboard/hp/280_g2/gma-mainboard.ads index 735fe2684c41..062821114240 100644 --- a/src/mainboard/hp/280_g2/gma-mainboard.ads +++ b/src/mainboard/hp/280_g2/gma-mainboard.ads @@ -9,7 +9,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (HDMI3, -- DVI-I + (HDMI3, -- DVI-D eDP, -- VGA others => Disabled); diff --git a/src/mainboard/hp/280_g2/hda_verb.c b/src/mainboard/hp/280_g2/hda_verb.c index 3ed214fc04fd..908fe0ad1c55 100644 --- a/src/mainboard/hp/280_g2/hda_verb.c +++ b/src/mainboard/hp/280_g2/hda_verb.c @@ -11,12 +11,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x17, 0x90170120), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x01813030), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4044c301), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221101f), }; diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 993721b4732a..09ba412ac79b 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -26,6 +26,23 @@ chip northbridge/intel/sandybridge register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x0" + register "usb_port_config" = "{ + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 } + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c index 97e069a6ece9..c7cddc7a56be 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/hda_verb.c @@ -9,14 +9,14 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0, 0x103c1495), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x99130120), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01813c30), AZALIA_PIN_CFG(0, 0x19, 0x02a11c3f), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x0221101f), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40028101), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80861495, /* Subsystem ID */ diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb index 7a62df100102..777ff0071d9b 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb +++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb @@ -19,6 +19,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" device ref xhci on # USB 3.0 Controller subsystemid 0x103c 0x3398 end diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c index a0c534c198cf..9c9415969f8a 100644 --- a/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c +++ b/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c @@ -7,15 +7,15 @@ const u32 cim_verb_data[] = { 0x103c3398, /* Subsystem ID */ 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x103c3398), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014020), AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f), AZALIA_PIN_CFG(0, 0x1b, 0x01813c30), AZALIA_PIN_CFG(0, 0x1d, 0x598301f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221102f), 0x80862806, /* Codec Vendor / Device ID: Intel */ diff --git a/src/mainboard/hp/elitebook_820_g2/hda_verb.c b/src/mainboard/hp/elitebook_820_g2/hda_verb.c index 7199d3f827c9..2d535922d512 100644 --- a/src/mainboard/hp/elitebook_820_g2/hda_verb.c +++ b/src/mainboard/hp/elitebook_820_g2/hda_verb.c @@ -13,14 +13,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x0421101f), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x04a11020), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40748605), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x02050007, 0x0204c200, 0x02050063, 0x02044800, 0x02050066, 0x02040809, 0x02050015, 0x02048842, diff --git a/src/mainboard/hp/folio_9480m/hda_verb.c b/src/mainboard/hp/folio_9480m/hda_verb.c index 9ee6de01a8d5..91a550b09b52 100644 --- a/src/mainboard/hp/folio_9480m/hda_verb.c +++ b/src/mainboard/hp/folio_9480m/hda_verb.c @@ -12,14 +12,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x0321101f), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738105), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* The following is from the OEM firmware */ 0x02050007, 0x0204c200, 0x02050063, 0x02044800, diff --git a/src/mainboard/hp/pro_3500_series/hda_verb.c b/src/mainboard/hp/pro_3500_series/hda_verb.c index 4b3104e052d4..cacda9b435fe 100644 --- a/src/mainboard/hp/pro_3500_series/hda_verb.c +++ b/src/mainboard/hp/pro_3500_series/hda_verb.c @@ -8,15 +8,15 @@ const u32 cim_verb_data[] = { 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x103c2abf), AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19830), AZALIA_PIN_CFG(0, 0x19, 0x02a19831), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/hda_verb.c b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/hda_verb.c index 27ab4b527593..024ff227e5ef 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/hda_verb.c @@ -10,12 +10,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x403c0000), AZALIA_PIN_CFG(0, 0x14, 0x01014020), AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x02a11030), AZALIA_PIN_CFG(0, 0x1b, 0x0181303f), AZALIA_PIN_CFG(0, 0x1d, 0x40400001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221102f), 0x80862806, /* Codec Vendor / Device ID: Intel */ diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb index 1867d3a535bd..a8dcb17bb689 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_cmt_workstation/overridetree.cb @@ -9,6 +9,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 5 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 7 }, + { 1, 0, 7 } + }" device ref xhci on end device ref pcie_rp2 on end diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/hda_verb.c index 27ab4b527593..024ff227e5ef 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/hda_verb.c +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/hda_verb.c @@ -10,12 +10,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x403c0000), AZALIA_PIN_CFG(0, 0x14, 0x01014020), AZALIA_PIN_CFG(0, 0x17, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x02a11030), AZALIA_PIN_CFG(0, 0x1b, 0x0181303f), AZALIA_PIN_CFG(0, 0x1d, 0x40400001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0221102f), 0x80862806, /* Codec Vendor / Device ID: Intel */ diff --git a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb index 560b407eedc2..4684b0e7bf53 100644 --- a/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_desktops/variants/z220_sff_workstation/overridetree.cb @@ -9,6 +9,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_switchable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 5 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 7 }, + { 1, 0, 7 } + }" device ref xhci on end end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb index 092049c286af..dfd1cce25121 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2170p/overridetree.cb @@ -23,6 +23,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, /* SSP1: dock */ + {1, 1, 0}, /* SSP2: left, EHCI Debug */ + {0, 1, 1}, /* SSP3 */ + {1, 1, 1}, /* SSP4: right */ + {0, 0, 2}, /* B0P5 */ + {0, 0, 2}, /* B0P6 */ + {0, 0, 3}, /* B0P7 */ + {1, 0, 3}, /* B0P8: smart card reader */ + {1, 0, 4}, /* B1P1: fingerprint reader */ + {1, 0, 4}, /* B1P2: (EHCI Debug) wlan usb */ + {1, 1, 5}, /* B1P3: Camera */ + {1, 0, 5}, /* B1P4 */ + {1, 0, 6}, /* B1P5: wwan USB */ + {0, 0, 6} + }" device ref xhci on end device ref mei1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb index c73786ad3163..f5db40f8021f 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2560p/overridetree.cb @@ -21,6 +21,23 @@ chip northbridge/intel/sandybridge # HDD(0), ODD(1), eSATA(4), dock eSATA(5) register "sata_port_map" = "0x33" + register "usb_port_config" = "{ + {1, 1, 0}, /* back bottom USB port, USB debug */ + {1, 1, 0}, /* back upper USB port */ + {1, 1, 1}, /* eSATA */ + {1, 1, 1}, /* webcam */ + {1, 0, 2}, + {1, 0, 2}, /* bluetooth */ + {1, 0, 3}, + {1, 0, 3}, /* smartcard */ + {1, 1, 4}, /* fingerprint reader */ + {1, 1, 4}, /* WWAN */ + {0, 0, 5}, + {1, 0, 5}, /* docking */ + {0, 0, 6}, + {0, 0, 6} + }" + device ref pcie_rp1 off end device ref pcie_rp2 on smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb index af80813ae035..ab6529ea0d3a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2570p/overridetree.cb @@ -22,6 +22,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, + {0, 1, 0}, + {1, 1, 1}, + {1, 1, 1}, + {1, 0, 2}, + {1, 0, 2}, /* bluetooth */ + {0, 0, 3}, + {1, 0, 3}, /* smartcard */ + {1, 1, 4}, + {1, 1, 4}, /* mainboard USB 2.0 */ + {1, 0, 5}, /* camera */ + {0, 0, 5}, + {1, 0, 6}, /* WWAN */ + {0, 0, 6} + }" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb index 9d1890a15a28..22f2b84c5961 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/2760p/overridetree.cb @@ -20,6 +20,23 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 1, 1, 0, 0, 0, 0, 0 }" register "sata_port_map" = "0x21" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 1, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 0, 4 }, + { 0, 0, 5 }, + { 1, 1, 5 }, + { 0, 0, 6 }, + { 1, 1, 6 } + }" + device ref pcie_rp1 on end device ref pcie_rp2 on smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb index bf640995e944..b1d03baea080 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8460p/overridetree.cb @@ -21,6 +21,23 @@ chip northbridge/intel/sandybridge # HDD(0), ODD(1), docking(3,5), eSATA(4) register "sata_port_map" = "0x3b" + register "usb_port_config" = "{ + {1, 1, 0}, /* USB0, eSATA */ + {1, 0, 0}, /* USB charger */ + {0, 1, 1}, + {1, 1, 1}, /* camera */ + {1, 0, 2}, /* USB4 expresscard */ + {1, 0, 2}, /* bluetooth */ + {0, 0, 3}, + {1, 0, 3}, /* smartcard */ + {1, 1, 4}, /* fingerprint */ + {1, 1, 4}, /* WWAN */ + {1, 0, 5}, /* CONN */ + {1, 0, 5}, /* docking */ + {1, 0, 6}, /* CONN */ + {1, 0, 6} /* docking */ + }" + device ref me_kt on end device ref pcie_rp1 on end device ref pcie_rp2 on diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb index cfc53727e23f..b3cc3a9f938a 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8470p/overridetree.cb @@ -23,6 +23,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 0, 0, 2 }, + { 0, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref xhci on end device ref me_kt on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb index f326c401919b..771cda0b2412 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/8770w/overridetree.cb @@ -24,6 +24,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, /* Dock USB3.0 */ + {1, 1, 0}, /* Conn */ + {1, 1, 1}, /* USB 3.0 */ + {1, 1, 1}, /* USB 3.0 */ + {1, 0, 2}, /* Express Card */ + {1, 0, 2}, /* Bluetooth */ + {0, 0, 3}, + {1, 0, 3}, /* Smart Card */ + {1, 1, 4}, /* Fingerprint Reader */ + {1, 1, 4}, /* Conn (Charger) */ + {1, 0, 5}, /* Camera */ + {1, 0, 5}, /* Dock */ + {1, 0, 6}, /* WWAN */ + {1, 0, 6} /* Conn (eSATA Combo) */ + }" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb index 1e3984d4ba0d..c16634d97fb4 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/folio_9470m/overridetree.cb @@ -22,6 +22,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + {1, 1, 0}, /* SSP1: dock */ + {1, 1, 0}, /* SSP2: left, EHCI Debug */ + {1, 1, 1}, /* SSP3: right back side */ + {1, 1, 1}, /* SSP4: right front side */ + {1, 0, 2}, /* B0P5 */ + {1, 0, 2}, /* B0P6: wlan USB */ + {0, 0, 3}, /* B0P7 */ + {1, 1, 3}, /* B0P8: smart card reader */ + {1, 1, 4}, /* B1P1: fingerprint reader */ + {0, 0, 4}, /* B1P2: (EHCI Debug, not connected) */ + {1, 1, 5}, /* B1P3: Camera */ + {0, 0, 5}, /* B1P4 */ + {1, 1, 6}, /* B1P5: wwan USB */ + {0, 0, 6} + }" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb index 64653bc01594..b3bbe1ce8f48 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/probook_6360b/overridetree.cb @@ -20,6 +20,23 @@ chip northbridge/intel/sandybridge # FIXME: ports 3, 5 are untested register "sata_port_map" = "0x3b" + register "usb_port_config" = "{ + {1, 1, 0}, /* left front */ + {1, 1, 0}, /* left rear, debug */ + {1, 1, 1}, /* eSATA */ + {1, 1, 1}, /* webcam */ + {1, 0, 2}, + {1, 0, 2}, /* bluetooth */ + {0, 0, 3}, + {0, 0, 3}, + {1, 1, 4}, /* fingerprint reader */ + {1, 1, 4}, /* WWAN */ + {1, 0, 5}, /* right */ + {1, 0, 5}, + {1, 0, 6}, + {1, 0, 6} + }" + device ref pcie_rp1 on end device ref pcie_rp2 on smbios_slot_desc "SlotTypePcmcia" "SlotLengthShort" diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb index 2e363711e3f1..45a3c3e319fc 100644 --- a/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/variants/revolve_810_g1/overridetree.cb @@ -22,6 +22,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 0, 1, 1 }, + { 0, 0, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 0, 4 }, /* B1P1: Digitizer */ + { 1, 0, 4 }, /* B1P2: wlan USB, EHCI debug */ + { 1, 1, 5 }, /* B1P3: Camera */ + { 0, 0, 5 }, /* B1P4 */ + { 1, 0, 6 }, /* B1P5: wwan USB */ + { 0, 0, 6 }, /* B1P6 */ + }" device ref xhci on end device ref pcie_rp1 on end diff --git a/src/mainboard/ibm/sbp1/ramstage.c b/src/mainboard/ibm/sbp1/ramstage.c index d748b1b176fe..98aa999827ef 100644 --- a/src/mainboard/ibm/sbp1/ramstage.c +++ b/src/mainboard/ibm/sbp1/ramstage.c @@ -2,6 +2,7 @@ #include <cpu/x86/smm.h> #include <soc/ramstage.h> #include <soc/smmrelocate.h> +#include <stdio.h> #include "include/spr_sbp1_gpio.h" #include <bootstate.h> diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c index 365d6b10ae57..489f09f05b7c 100644 --- a/src/mainboard/ibm/sbp1/romstage.c +++ b/src/mainboard/ibm/sbp1/romstage.c @@ -70,11 +70,11 @@ sbp1_socket_config[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { CFG_UPD_PCIE_PORT(0, 1, 16), /* 37:07.0 RSSD16 */ CFG_UPD_PCIE_PORT(1, 0, 0), /* IOU3 (PE3): array index 25 ~ 32 IIO_BIFURCATE_x4x4x4x4 */ - CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:01.0 - NIC2*/ + CFG_UPD_PCIE_PORT(0, 1, 37), /* 48:01.0 - NIC2*/ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), - CFG_UPD_PCIE_PORT(0, 0, 0), /* 48:05.0 - NIC1 */ + CFG_UPD_PCIE_PORT(0, 1, 33), /* 48:05.0 - NIC1 */ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), @@ -128,11 +128,11 @@ sbp1_socket_config[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), /* IOU4 (PE4): array index 33 ~ 40 IIO_BIFURCATE_x4x4x4x4 */ - CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:01.0 - NIC2 */ + CFG_UPD_PCIE_PORT(0, 1, 38), /* 59:01.0 - NIC2 */ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), - CFG_UPD_PCIE_PORT(0, 0, 0), /* 59:05.0 - NIC1 */ + CFG_UPD_PCIE_PORT(0, 1, 34), /* 59:05.0 - NIC1 */ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), @@ -159,11 +159,11 @@ sbp1_socket_config[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), /* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */ - CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */ + CFG_UPD_PCIE_PORT(0, 1, 35), /* 37:01.0 - NIC1 */ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), - CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */ + CFG_UPD_PCIE_PORT(0, 1, 39), /* 37:05.0 - NIC2 */ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), @@ -208,11 +208,11 @@ sbp1_socket_config[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS] = { CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), /* IOU2 (PE2): array index 17 ~ 24 IIO_BIFURCATE_x4x4x4x4 */ - CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:01.0 - NIC1 */ + CFG_UPD_PCIE_PORT(0, 1, 36), /* 37:01.0 - NIC1 */ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), - CFG_UPD_PCIE_PORT(0, 0, 0), /* 37:05.0 - NIC2 */ + CFG_UPD_PCIE_PORT(0, 1, 40), /* 37:05.0 - NIC2 */ CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), CFG_UPD_PCIE_PORT(1, 0, 0), diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 1083ce2b9c41..5ee091bc8be5 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -135,9 +135,6 @@ config DEVICETREE config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -config DIMM_SPD_SIZE - default 512 - choice prompt "ON BOARD EC" default ADL_CHROME_EC if BOARD_INTEL_ADLRVP_P_EXT_EC || BOARD_INTEL_ADLRVP_P_MCHP || BOARD_INTEL_ADLRVP_N_EXT_EC || BOARD_INTEL_ADLRVP_RPL_EXT_EC diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c index 9ac480d4866b..c02cbf9a58db 100644 --- a/src/mainboard/intel/adlrvp/mainboard.c +++ b/src/mainboard/intel/adlrvp/mainboard.c @@ -11,7 +11,7 @@ #include <smbios.h> #include <soc/gpio.h> #include <stdint.h> -#include <string.h> +#include <stdio.h> #include "board_id.h" diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c index 6e4bd8e11ef9..9189099df9c7 100644 --- a/src/mainboard/intel/archercity_crb/romstage.c +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -11,7 +11,8 @@ void mainboard_ewl_check(void) { - get_ewl(); + if (CONFIG(OCP_EWL)) + get_ewl(); } static void mainboard_config_iio(FSPM_UPD *mupd) @@ -35,15 +36,23 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; + /* Setup FSP log */ + if (CONFIG(OCP_VPD)) { + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } + } - /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set SerialIoUartDebugEnable to %d\n", - FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); } /* Set Rank Margin Tool to disable. */ diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig b/src/mainboard/intel/avenuecity_crb/Kconfig new file mode 100644 index 000000000000..fff244e92eb7 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_AVENUECITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select OCP_VPD + select MEMORY_MAPPED_TPM + +config CARDBUS_PLUGIN_SUPPORT + bool + default n + +config MAINBOARD_DIR + string + default "intel/avenuecity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Avenue City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/avenuecity_crb/Kconfig.name b/src/mainboard/intel/avenuecity_crb/Kconfig.name new file mode 100644 index 000000000000..f73d1d936ff3 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_AVENUECITY_CRB + bool "Avenue City CRB" diff --git a/src/mainboard/intel/avenuecity_crb/Makefile.mk b/src/mainboard/intel/avenuecity_crb/Makefile.mk new file mode 100644 index 000000000000..2e1a74a45a59 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +romstage-y += config/iio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/avenuecity_crb/board.fmd b/src/mainboard/intel/avenuecity_crb/board.fmd new file mode 100644 index 000000000000..df5bc059f414 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board.fmd @@ -0,0 +1,12 @@ +FLASH@0xfc000000 64M { + SI_ALL 48M { + SI_DESC@0x0 0x1000 + } + SI_BIOS 16M { + RW_MRC_CACHE 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/intel/avenuecity_crb/board_info.txt b/src/mainboard/intel/avenuecity_crb/board_info.txt new file mode 100644 index 000000000000..2c502cfdf2b6 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Avenue City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/avenuecity_crb/bootblock.c b/src/mainboard/intel/avenuecity_crb/bootblock.c new file mode 100644 index 000000000000..e68d874c900e --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/bootblock.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/avenuecity_crb/config/iio.c b/src/mainboard/intel/avenuecity_crb/config/iio.c new file mode 100644 index 000000000000..117d604a2dc0 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/config/iio.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/iio.h> + +static const struct iio_pe_config iio_config_table[] = { + /* + * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated + * then port settings are listed accordingly. The minimal port elements are x2. + * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be + * disabled. + */ + {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { + /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ + _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5), + }}, +}; + +const struct iio_pe_config *get_iio_config_table(int *size) +{ + *size = ARRAY_SIZE(iio_config_table); + return iio_config_table; +} diff --git a/src/mainboard/intel/avenuecity_crb/devicetree.cb b/src/mainboard/intel/avenuecity_crb/devicetree.cb new file mode 100644 index 000000000000..0754916c393e --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/devicetree.cb @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE + + device domain 0 on + device pci 1f.0 on + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + end +end diff --git a/src/mainboard/intel/avenuecity_crb/dsdt.asl b/src/mainboard/intel/avenuecity_crb/dsdt.asl new file mode 100644 index 000000000000..34c29374faff --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/avenuecity_crb/ramstage.c b/src/mainboard/intel/avenuecity_crb/ramstage.c new file mode 100644 index 000000000000..a09016d46114 --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + +} diff --git a/src/mainboard/intel/avenuecity_crb/romstage.c b/src/mainboard/intel/avenuecity_crb/romstage.c new file mode 100644 index 000000000000..f0e67af21efb --- /dev/null +++ b/src/mainboard/intel/avenuecity_crb/romstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/ocp/include/vpd.h> +#include <drivers/vpd/vpd.h> +#include <fmap_config.h> +#include <device/device.h> +#include <soc/ddr.h> +#include <soc/iio.h> +#include <soc/romstage.h> + +#include "chip.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + /* FSP log outputs */ + const config_t *config = config_of_soc(); + m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base; + m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT); + m_cfg->DebugPrintLevel = config->debug_print_level; + m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL, + FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ + m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START; + m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE; + printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase); + printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize); + + /* IIO init */ + int size; + const struct iio_pe_config *iio_config_table = get_iio_config_table(&size); + soc_config_iio_pe_ports(mupd, iio_config_table, size); +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + //TODO: not implemented yet + return false; +} diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig b/src/mainboard/intel/beechnutcity_crb/Kconfig new file mode 100644 index 000000000000..3c2f02a9ea70 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_BEECHNUTCITY_CRB + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_65536 + select SOC_INTEL_GRANITERAPIDS + select SUPERIO_ASPEED_AST2400 + select HAVE_ACPI_TABLES + select IPMI_KCS + select IPMI_KCS_ROMSTAGE + select VPD + select OCP_VPD + select MEMORY_MAPPED_TPM + +config CARDBUS_PLUGIN_SUPPORT + bool + default n + +config MAINBOARD_DIR + string + default "intel/beechnutcity_crb" + +config MAINBOARD_PART_NUMBER + string + default "Beechnut City CRB" + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config DIMM_MAX + int + default 1 + +endif diff --git a/src/mainboard/intel/beechnutcity_crb/Kconfig.name b/src/mainboard/intel/beechnutcity_crb/Kconfig.name new file mode 100644 index 000000000000..083fbf033527 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_BEECHNUTCITY_CRB + bool "Beechnut City CRB" diff --git a/src/mainboard/intel/beechnutcity_crb/Makefile.mk b/src/mainboard/intel/beechnutcity_crb/Makefile.mk new file mode 100644 index 000000000000..2e1a74a45a59 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +romstage-y += romstage.c +romstage-y += config/iio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/beechnutcity_crb/board.fmd b/src/mainboard/intel/beechnutcity_crb/board.fmd new file mode 100644 index 000000000000..df5bc059f414 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board.fmd @@ -0,0 +1,12 @@ +FLASH@0xfc000000 64M { + SI_ALL 48M { + SI_DESC@0x0 0x1000 + } + SI_BIOS 16M { + RW_MRC_CACHE 0x10000 + FMAP 0x800 + RW_VPD(PRESERVE) 0x4000 + RO_VPD(PRESERVE) 0x4000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/intel/beechnutcity_crb/board_info.txt b/src/mainboard/intel/beechnutcity_crb/board_info.txt new file mode 100644 index 000000000000..1de903ec8a36 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Beechnut City CRB +Category: eval +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/intel/beechnutcity_crb/bootblock.c b/src/mainboard/intel/beechnutcity_crb/bootblock.c new file mode 100644 index 000000000000..e68d874c900e --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/bootblock.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <intelblocks/lpc_lib.h> +#include <soc/intel/common/block/lpc/lpc_def.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <superio/aspeed/common/aspeed.h> + +#define ASPEED_SIO_PORT 0x2E + +void bootblock_mainboard_early_init(void) +{ + /* Enable eSPI decoding for com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + lpc_io_setup_comm_a_b(); + lpc_enable_fixed_io_ranges(LPC_IOE_SUPERIO_2E_2F); + + if (CONFIG_UART_FOR_CONSOLE == 0) { + /* Setup superio com1 */ + const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } else + die("COMs other than COM1 not supported\n"); +} diff --git a/src/mainboard/intel/beechnutcity_crb/config/iio.c b/src/mainboard/intel/beechnutcity_crb/config/iio.c new file mode 100644 index 000000000000..117d604a2dc0 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/config/iio.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <soc/iio.h> + +static const struct iio_pe_config iio_config_table[] = { + /* + * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated + * then port settings are listed accordingly. The minimal port elements are x2. + * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be + * disabled. + */ + {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) { + /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */ + _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1), + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_DISABLED, + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4), + _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5), + }}, +}; + +const struct iio_pe_config *get_iio_config_table(int *size) +{ + *size = ARRAY_SIZE(iio_config_table); + return iio_config_table; +} diff --git a/src/mainboard/intel/beechnutcity_crb/devicetree.cb b/src/mainboard/intel/beechnutcity_crb/devicetree.cb new file mode 100644 index 000000000000..0754916c393e --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/devicetree.cb @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/intel/xeon_sp/gnr + + # configure LPC generic IO decode ranges + # [bits 31..24: reserved] + # [bits 23..18: io decode address mask <7..2>] + # [bits 17..16: reserved] + # [bits 15..2 : io decode dword aligned address <15..2>] + # [bit 1 : reserved] + # [bit 0 : enabled] + register "gen1_dec" = "0x00000CA1" # IPMI KCS + + # configure FSP debug settings + register "serial_io_uart_debug_io_base" = CONFIG_TTYS0_BASE + + device domain 0 on + device pci 1f.0 on + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "1" + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 # PNP_IDX_IO0 + irq 0x70 = 4 # PNP_IDX_IRQ0 + end + end + end + end + chip drivers/ipmi + device pnp ca2.0 on end # BMC KCS + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + end + end + end +end diff --git a/src/mainboard/intel/beechnutcity_crb/dsdt.asl b/src/mainboard/intel/beechnutcity_crb/dsdt.asl new file mode 100644 index 000000000000..34c29374faff --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/dsdt.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/xeon_sp/gnr/acpi/gpe.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <commonlib/include/commonlib/console/post_codes.h> + #include <arch/x86/acpi/post.asl> + #include <arch/x86/acpi/debug.asl> +} diff --git a/src/mainboard/intel/beechnutcity_crb/ramstage.c b/src/mainboard/intel/beechnutcity_crb/ramstage.c new file mode 100644 index 000000000000..a09016d46114 --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *params) +{ + +} diff --git a/src/mainboard/intel/beechnutcity_crb/romstage.c b/src/mainboard/intel/beechnutcity_crb/romstage.c new file mode 100644 index 000000000000..f0e67af21efb --- /dev/null +++ b/src/mainboard/intel/beechnutcity_crb/romstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <drivers/ipmi/ipmi_if.h> +#include <drivers/ocp/include/vpd.h> +#include <drivers/vpd/vpd.h> +#include <fmap_config.h> +#include <device/device.h> +#include <soc/ddr.h> +#include <soc/iio.h> +#include <soc/romstage.h> + +#include "chip.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + /* FSP log outputs */ + const config_t *config = config_of_soc(); + m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base; + m_cfg->SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT); + m_cfg->DebugPrintLevel = config->debug_print_level; + m_cfg->serialDebugMsgLvl = get_int_from_vpd_range(FSP_MEM_LOG_LEVEL, + FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + + /* Early connect BMC, e.g. to query configuration parameters */ + if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) + printk(BIOS_INFO, "IPMI at 0x%04x initialized successfully\n", + CONFIG_BMC_KCS_BASE); + + /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ + m_cfg->BiosRegionBase = FMAP_SECTION_SI_BIOS_START; + m_cfg->BiosRegionSize = FMAP_SECTION_SI_BIOS_SIZE; + printk(BIOS_INFO, "BiosRegionBase is set to %x\n", mupd->FspmConfig.BiosRegionBase); + printk(BIOS_INFO, "BiosRegionSize is set to %x\n", mupd->FspmConfig.BiosRegionSize); + + /* IIO init */ + int size; + const struct iio_pe_config *iio_config_table = get_iio_config_table(&size); + soc_config_iio_pe_ports(mupd, iio_config_table, size); +} + +bool mainboard_dimm_slot_exists(uint8_t socket, uint8_t channel, uint8_t dimm) +{ + //TODO: not implemented yet + return false; +} diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 3d8321793c7a..59ce66c8d72d 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock( { Device (PCI0) { - #include <soc/intel/xeon_sp/acpi/southcluster.asl> + #include <soc/intel/xeon_sp/acpi/gen1/southcluster.asl> #include <soc/intel/common/block/acpi/acpi/lpc.asl> } diff --git a/src/mainboard/intel/coffeelake_rvp/bootblock.c b/src/mainboard/intel/coffeelake_rvp/bootblock.c index 90833269e400..df30c471f816 100644 --- a/src/mainboard/intel/coffeelake_rvp/bootblock.c +++ b/src/mainboard/intel/coffeelake_rvp/bootblock.c @@ -2,7 +2,7 @@ #include <baseboard/variants.h> #include <bootblock_common.h> -#include <soc/gpio.h> +#include <gpio.h> void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c index eb9a316a34b6..481f71562439 100644 --- a/src/mainboard/intel/coffeelake_rvp/mainboard.c +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -4,7 +4,7 @@ #include <baseboard/variants.h> #include <device/device.h> #include <nhlt.h> -#include <soc/gpio.h> +#include <gpio.h> #include <soc/nhlt.h> static void mainboard_init(void *chip_info) diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h index 102f5e12eba2..848024ec10fc 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/gpio.h @@ -3,6 +3,6 @@ #ifndef __BASEBOARD_GPIO_H__ #define __BASEBOARD_GPIO_H__ -#include <soc/gpio.h> +#include <gpio.h> #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h index 6ae25d4d8487..d93c446f1343 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/include/baseboard/variants.h @@ -4,7 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <soc/cnl_memcfg_init.h> -#include <soc/gpio.h> +#include <gpio.h> /* The next set of functions return the gpio table and fill in the number of * entries for each table. */ diff --git a/src/mainboard/intel/d510mo/hda_verb.c b/src/mainboard/intel/d510mo/hda_verb.c index 7a5215508285..2ec1e7e28757 100644 --- a/src/mainboard/intel/d510mo/hda_verb.c +++ b/src/mainboard/intel/d510mo/hda_verb.c @@ -10,13 +10,13 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014410), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19841), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), AZALIA_PIN_CFG(0, 0x1b, 0x02214420), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4015c603), AZALIA_PIN_CFG(0, 0x1e, 0x99430130), }; diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index f4e948f76c1c..954f572b312e 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -15,22 +15,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "666" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - register "usb_port_config" = "{ - {1, 0, 0x0040}, - {1, 0, 0x0040}, - {1, 1, 0x0040}, - {1, 1, 0x0040}, - {1, 2, 0x0040}, - {1, 2, 0x0040}, - {1, 3, 0x0040}, - {0, 3, 0x0040}, - {0, 4, 0x0040}, - {0, 4, 0x0040}, - {0, 5, 0x0040}, - {0, 5, 0x0040}, - {0, 6, 0x0040}, - {0, 6, 0x0040}, }" - device domain 0 on device ref host_bridge on end # Host bridge device ref peg10 off end # PCIe Bridge for discrete graphics @@ -43,6 +27,23 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + register "usb_port_config" = "{ + {1, 1, 0}, /* back, towards HDMI plugs */ + {1, 1, 0}, /* back, towards power plug */ + {1, 1, 1}, /* half-width miniPCIe */ + {1, 1, 1}, /* full-width miniPCIe */ + {1, 1, 2}, /* front-panel header */ + {1, 1, 2}, /* front-panel header */ + {1, 1, 3}, /* front connector */ + {0, 1, 3}, /* not available x7 */ + {0, 1, 4}, + {0, 1, 4}, + {0, 1, 5}, + {0, 1, 5}, + {0, 1, 6}, + {0, 1, 6} + }" + device ref xhci off end # USB xHCI device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index e0f27bab51f0..a137e35d4227 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -124,8 +124,3 @@ void bootblock_mainboard_early_init(void) superio_init(); hwm_init(); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { -#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin } -#include "usb.h" -}; diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h deleted file mode 100644 index 24693098a690..000000000000 --- a/src/mainboard/intel/dcp847ske/usb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DCP847SKE_USB_H -#define DCP847SKE_USB_H - -USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */ -USB_CONFIG(1, 1, 0), /* back, towards power plug */ -USB_CONFIG(1, 1, 1), /* half-width miniPCIe */ -USB_CONFIG(1, 1, 1), /* full-width miniPCIe */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 2), /* front-panel header */ -USB_CONFIG(1, 1, 3), /* front connector */ -USB_CONFIG(0, 1, 3), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 4), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 5), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ -USB_CONFIG(0, 1, 6), /* not available */ - -#endif diff --git a/src/mainboard/intel/dg41wv/hda_verb.c b/src/mainboard/intel/dg41wv/hda_verb.c index 700953675da5..5bef966e75a4 100644 --- a/src/mainboard/intel/dg41wv/hda_verb.c +++ b/src/mainboard/intel/dg41wv/hda_verb.c @@ -12,8 +12,8 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), diff --git a/src/mainboard/intel/dg43gt/hda_verb.c b/src/mainboard/intel/dg43gt/hda_verb.c index 235ed285428d..00ec79cfef0c 100644 --- a/src/mainboard/intel/dg43gt/hda_verb.c +++ b/src/mainboard/intel/dg43gt/hda_verb.c @@ -11,19 +11,19 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ AZALIA_PIN_CFG(0, 0x11, 0x01452140), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014410), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19850), AZALIA_PIN_CFG(0, 0x19, 0x02a19960), AZALIA_PIN_CFG(0, 0x1a, 0x0181345f), AZALIA_PIN_CFG(0, 0x1b, 0x02214520), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4006f601), AZALIA_PIN_CFG(0, 0x1e, 0x99430130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* HDMI */ 0x80862803, diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb index f29b772e8a43..6a28bcc1bf0a 100644 --- a/src/mainboard/intel/dq67sw/devicetree.cb +++ b/src/mainboard/intel/dq67sw/devicetree.cb @@ -14,6 +14,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 4 }, + { 0, 0, 5 }, + { 0, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref mei1 on end # Management Engine Interface 1 device ref me_ide_r on end # Management Engine IDE-R device ref me_kt on end # Management Engine KT diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c index 14317a69e0b6..f7515a540c4f 100644 --- a/src/mainboard/intel/dq67sw/early_init.c +++ b/src/mainboard/intel/dq67sw/early_init.c @@ -1,29 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <southbridge/intel/bd82x6x/pch.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 4 }, - { 0, 0, 5 }, - { 0, 0, 5 }, - { 1, 0, 6 }, - { 1, 0, 6 }, -}; - void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/intel/dq67sw/hda_verb.c b/src/mainboard/intel/dq67sw/hda_verb.c index 81794c15ad15..8fbd95858d85 100644 --- a/src/mainboard/intel/dq67sw/hda_verb.c +++ b/src/mainboard/intel/dq67sw/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x80862008, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x80862008), - AZALIA_PIN_CFG(2, 0x11, 0x411111f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014410), - AZALIA_PIN_CFG(2, 0x15, 0x411111f0), - AZALIA_PIN_CFG(2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x17, 0x99130140), AZALIA_PIN_CFG(2, 0x18, 0x01a19c50), AZALIA_PIN_CFG(2, 0x19, 0x02a19960), AZALIA_PIN_CFG(2, 0x1a, 0x0181345f), AZALIA_PIN_CFG(2, 0x1b, 0x02214120), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4004c601), AZALIA_PIN_CFG(2, 0x1e, 0x99430130), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80862008, /* Subsystem ID */ diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index e75505e270c2..e547ff111f09 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -14,22 +14,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 2, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 6, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end @@ -58,6 +42,22 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x000c0181" # SuperIO range is 0x700-0x73f register "gen3_dec" = "0x003c0701" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 0, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ + }" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 19747135208a..329f13d2c160 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -47,21 +47,3 @@ void bootblock_mainboard_early_init(void) void mainboard_fill_pei_data(struct pei_data *pei_data) { } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, 0 }, /* P0: Front port (OC0) */ - { 1, 0, 1 }, /* P1: Back port (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 1, 0, 2 }, /* P4: Front port (OC2) */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, 4 }, /* P8: Back port (OC4) */ - { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 1, 0, 6 }, /* P12: Back port (OC6) */ - { 1, 0, 5 }, /* P13: Back port (OC5) */ -}; diff --git a/src/mainboard/intel/glkrvp/boardid.c b/src/mainboard/intel/glkrvp/boardid.c index 35dcc4b29d49..ba2f879047ce 100644 --- a/src/mainboard/intel/glkrvp/boardid.c +++ b/src/mainboard/intel/glkrvp/boardid.c @@ -2,7 +2,6 @@ #include <baseboard/variants.h> #include <boardid.h> -#include <stddef.h> #include <ec/acpi/ec.h> #define BOARD_ID_GLK_RVP1_DDR4 0x5 /* RVP1 - DDR4 */ diff --git a/src/mainboard/intel/harcuvar/spd/spd.c b/src/mainboard/intel/harcuvar/spd/spd.c index e3912ec91efd..d3cefa6b20f3 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.c +++ b/src/mainboard/intel/harcuvar/spd/spd.c @@ -2,6 +2,8 @@ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr4.h> +#include <spd.h> #include "spd.h" @@ -19,17 +21,17 @@ uint8_t *mainboard_find_spd_data(void) if (!spd_file) die("SPD data not found."); - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR4)) { printk(BIOS_ERR, "SPD index override to 0 due to incorrect SPD index.\n"); spd_index = 0; } - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR4) die("Missing SPD data."); /* Assume same memory in both channels */ - spd_index *= SPD_LEN; + spd_index *= SPD_SIZE_MAX_DDR4; spd_data = (uint8_t *)(spd_file + spd_index); /* Make sure a valid SPD was found */ diff --git a/src/mainboard/intel/harcuvar/spd/spd.h b/src/mainboard/intel/harcuvar/spd/spd.h index 44eec02a6b97..92377fd9ac88 100644 --- a/src/mainboard/intel/harcuvar/spd/spd.h +++ b/src/mainboard/intel/harcuvar/spd/spd.h @@ -5,18 +5,6 @@ #include <stdint.h> -#define SPD_LEN 512 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - uint8_t *mainboard_find_spd_data(void); #endif diff --git a/src/mainboard/intel/kblrvp/board_id.c b/src/mainboard/intel/kblrvp/board_id.c index 4305295d9bcd..23c93350c677 100644 --- a/src/mainboard/intel/kblrvp/board_id.c +++ b/src/mainboard/intel/kblrvp/board_id.c @@ -2,7 +2,6 @@ #include "board_id.h" #include <ec/acpi/ec.h> #include <stdint.h> -#include <stddef.h> /* * Get Board info via EC I/O port write/read diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 56c86115ccd8..156c626b6082 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -4,6 +4,9 @@ #include <gpio.h> #include "gpio.h" #include <soc/romstage.h> +#include <device/dram/ddr3.h> +#include <spd.h> + #include "spd/spd.h" void mainboard_memory_init_params(FSPM_UPD *mupd) @@ -20,5 +23,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); if (mainboard_has_dual_channel_mem()) mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; - mem_cfg->MemorySpdDataLen = SPD_LEN; + mem_cfg->MemorySpdDataLen = SPD_SIZE_MAX_DDR3; } diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index c53c6e4379a0..0b4d0e26effc 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -8,19 +8,6 @@ #define MAINBOARD_SPD_H -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 -#define SPD_MANU_OFF 148 - #define HYNIX_SINGLE_CHAN 0x1 #define SAMSUNG_SINGLE_CHAN 0x4 #define MIC_SINGLE_CHAN 0x5 diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index 8c1407adc6da..e79759cced56 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> #include <console/console.h> +#include <device/dram/ddr3.h> +#include <spd.h> #include <stdint.h> #include <string.h> + #include "boardid.h" #include "spd.h" @@ -72,16 +75,16 @@ uintptr_t mainboard_get_spd_data(void) die("SPD data not found."); /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) + if (spd_file_len < SPD_SIZE_MAX_DDR3) die("Missing SPD data."); /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + if (spd_file_len < ((spd_index + 1) * SPD_SIZE_MAX_DDR3)) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - spd_span = spd_index * SPD_LEN; + spd_span = spd_index * SPD_SIZE_MAX_DDR3; return (uintptr_t)(spd_file + spd_span); } diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 36842b577a3a..bbff4aa7c564 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -79,7 +79,9 @@ config GBB_HWID config MAINBOARD_PART_NUMBER string - default "mtlrvp" + default "Mtlrvp_P_Ext_Ec" if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP4ES_P_EXT_EC + default "Mtlrvp_P_Mchp" if BOARD_INTEL_MTLRVP_P_MCHP + default "Mtlrvp" if BOARD_INTEL_MTLRVP_P config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP diff --git a/src/mainboard/intel/mtlrvp/Makefile.mk b/src/mainboard/intel/mtlrvp/Makefile.mk index d8144c861458..6c93add77b0e 100644 --- a/src/mainboard/intel/mtlrvp/Makefile.mk +++ b/src/mainboard/intel/mtlrvp/Makefile.mk @@ -8,6 +8,7 @@ romstage-y += romstage.c ramstage-y += ec.c ramstage-y += mainboard.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/mtlrvp/mainboard.c b/src/mainboard/intel/mtlrvp/mainboard.c index 2e515f713773..93cec476f679 100644 --- a/src/mainboard/intel/mtlrvp/mainboard.c +++ b/src/mainboard/intel/mtlrvp/mainboard.c @@ -8,7 +8,7 @@ #include <soc/ramstage.h> #include <smbios.h> #include <stdint.h> -#include <string.h> +#include <stdio.h> const char *smbios_system_sku(void) { diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h index 402c9c17f8ed..44f9b43dcf53 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h @@ -59,6 +59,9 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 17c0014b4bc3..f01479bcaa39 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -42,9 +42,6 @@ config VBOOT select HAS_RECOVERY_MRC_CACHE select VBOOT_EARLY_EC_SYNC -config DIMM_SPD_SIZE - default 512 - config DEVICETREE default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c index bbce9278df67..b15f2c14b61d 100644 --- a/src/mainboard/intel/tglrvp/mainboard.c +++ b/src/mainboard/intel/tglrvp/mainboard.c @@ -6,7 +6,7 @@ #include <ec/ec.h> #include <soc/gpio.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> const char *smbios_system_sku(void) { diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c index 9299c7dc041c..25ff2d62266c 100644 --- a/src/mainboard/inventec/transformers/romstage.c +++ b/src/mainboard/inventec/transformers/romstage.c @@ -6,6 +6,7 @@ #include <drivers/ipmi/ipmi_if.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> #include <drivers/ocp/ewl/ocp_ewl.h> +#include <soc/config.h> #include <soc/romstage.h> #include <defs_cxl.h> #include <defs_iio.h> @@ -98,22 +99,28 @@ static void mainboard_config_iio(FSPM_UPD *mupd) void mainboard_memory_init_params(FSPM_UPD *mupd) { - uint8_t val; - /* Since it's the first IPMI command, it's better to run get BMC selftest result first */ if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { init_frb2_wdt(); } - /* Send FSP log message to SOL */ - if (CONFIG(VPD) && vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val)) - mupd->FspmConfig.SerialIoUartDebugEnable = val; - else { - printk(BIOS_INFO, "Not able to get VPD %s, default set " - "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT); - mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT; + /* Setup FSP log */ + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } } + /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; /* Enable - Portions of memory reference code will be skipped when possible to increase boot speed on warm boots */ diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index dbdd059af931..bd50fc33ca4c 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <string.h> #include <types.h> #include <device/device.h> #include <console/console.h> #include <drivers/intel/gma/int15.h> #include <option.h> +#include <stdio.h> #include <superio/hwm5_conf.h> #include <superio/nuvoton/common/hwm.h> diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index a03562842c65..6f21837d4e88 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -10,21 +10,6 @@ chip northbridge/intel/sandybridge register "usb3.mode" = "3" register "usb3.preboot_support" = "1" register "usb3.xhci_streams" = "1" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, }" chip cpu/intel/model_206ax device cpu_cluster 0 on end @@ -55,6 +40,22 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */ + { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */ + { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */ + { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */ + { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */ + { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */ + { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ + }" device ref xhci on end # USB 3.0 Controller device ref mei1 on end # Management Engine Interface 1 diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index e514f102b53a..7a2376508f03 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -54,24 +54,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */ - { 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */ - { 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */ - { 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */ - { 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */ -}; - void mainboard_early_init(int s3resume) { /* Enable PEG10 (1x16) */ diff --git a/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c b/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c index 60b21be1e4f3..9d3692fe6086 100644 --- a/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c +++ b/src/mainboard/lenovo/haswell/variants/t440p/hda_verb.c @@ -12,13 +12,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x0321101f), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738105), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x05350000, 0x0534601a, 0x05450000, 0x05442000, 0x05350003, 0x05341ef8, 0x05450003, 0x05441ef8, diff --git a/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c b/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c index f99c3938c309..f92731ca1eca 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c +++ b/src/mainboard/lenovo/haswell/variants/w541/hda_verb.c @@ -12,13 +12,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x0321101f), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738105), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x05350000, 0x0534601a, 0x05450000, 0x05442000, 0x05350003, 0x05341ef8, 0x05450003, 0x05441ef8, diff --git a/src/mainboard/lenovo/haswell/variants/w541/romstage.c b/src/mainboard/lenovo/haswell/variants/w541/romstage.c index 4a189d42b837..a410f5620179 100644 --- a/src/mainboard/lenovo/haswell/variants/w541/romstage.c +++ b/src/mainboard/lenovo/haswell/variants/w541/romstage.c @@ -4,7 +4,6 @@ #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <option.h> #include <ec/lenovo/pmh7/pmh7.h> #include <device/pci_ops.h> diff --git a/src/mainboard/lenovo/l520/Makefile.mk b/src/mainboard/lenovo/l520/Makefile.mk index e4b6fbf0f0a5..761119433905 100644 --- a/src/mainboard/lenovo/l520/Makefile.mk +++ b/src/mainboard/lenovo/l520/Makefile.mk @@ -4,5 +4,3 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += early_init.c -romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index ead7e0bb871f..e398e78e317e 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -12,7 +12,14 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_up_delay" = "0" register "gpu_pch_backlight" = "0x00000000" register "spd_addresses" = "{0x50, 0, 0x52, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21dd inherit @@ -36,6 +43,23 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 } + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c deleted file mode 100644 index ebcd639e6a2f..000000000000 --- a/src/mainboard/lenovo/l520/early_init.c +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> -#include <southbridge/intel/common/gpio.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c index 3d48a8b86b4f..33da0b1ff2bb 100644 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ b/src/mainboard/lenovo/l520/hda_verb.c @@ -9,13 +9,13 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0, 0x17aa21de), AZALIA_PIN_CFG(0, 0x12, 0x99a30920), AZALIA_PIN_CFG(0, 0x14, 0x99130110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40079a2d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0321101f), 0x80862805, /* Codec Vendor / Device ID: Intel */ diff --git a/src/mainboard/lenovo/m900_tiny/hda_verb.c b/src/mainboard/lenovo/m900_tiny/hda_verb.c index b545df48cf5a..6c1f5456c2d1 100644 --- a/src/mainboard/lenovo/m900_tiny/hda_verb.c +++ b/src/mainboard/lenovo/m900_tiny/hda_verb.c @@ -9,13 +9,13 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(1, 0x17aa30d0), AZALIA_PIN_CFG(1, 0x12, 0x40000000), AZALIA_PIN_CFG(1, 0x14, 0x90170110), - AZALIA_PIN_CFG(1, 0x17, 0x411111f0), - AZALIA_PIN_CFG(1, 0x18, 0x411111f0), + AZALIA_PIN_CFG(1, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(1, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x19, 0x02a11030), AZALIA_PIN_CFG(1, 0x1a, 0x02a11040), AZALIA_PIN_CFG(1, 0x1b, 0x01011020), AZALIA_PIN_CFG(1, 0x1d, 0x40400001), - AZALIA_PIN_CFG(1, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(1, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(1, 0x21, 0x0221101f), 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 47add6f39a90..6e66f3a7cc79 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -5,7 +5,6 @@ #include <drivers/intel/gma/int15.h> #include <gpio.h> #include <mainboard/gpio.h> -#include <soc/gpio.h> #include <soc/ramstage.h> static void print_board_id(void) diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index eae969633678..eb832bed74bc 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -34,6 +34,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 0, 1 }, + { 1, 1, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 1, 3 }, + { 1, 0, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 1, 6 } + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 58e95932b80d..f4396cb617e2 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -20,23 +20,6 @@ void mainboard_pch_lpc_setup(void) ec_mm_set_bit(0x3b, 4); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 0, 1 }, - { 1, 1, 2 }, - { 1, 0, 2 }, - { 0, 0, 3 }, - { 0, 1, 3 }, - { 1, 0, 4 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, -}; - static const char *mainboard_spd_names[9] = { "ELPIDA 4GB", "SAMSUNG 4GB", diff --git a/src/mainboard/lenovo/s230u/hda_verb.c b/src/mainboard/lenovo/s230u/hda_verb.c index ab28cf9506ea..1d0586318530 100644 --- a/src/mainboard/lenovo/s230u/hda_verb.c +++ b/src/mainboard/lenovo/s230u/hda_verb.c @@ -56,25 +56,25 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x03211020), /* Unknown: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* MIC1 in: Location left, mic in, 1/8" jack, black */ AZALIA_PIN_CFG(0, 0x18, 0x03a11830), /* MIC2 in: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), /* Line1 in: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* Line2 in: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* PCBEEP */ AZALIA_PIN_CFG(0, 0x1d, 0x40148605), /* S/PDIF out: (Unconnected) */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x01470740, /* Enable output for NID 0x14 (Speaker out) */ 0x015707C0, /* Enable output & HP amp for NID 0x15 (HP out) */ diff --git a/src/mainboard/lenovo/s230u/mainboard.c b/src/mainboard/lenovo/s230u/mainboard.c index b5e3b8786d5b..f51ec6705fa9 100644 --- a/src/mainboard/lenovo/s230u/mainboard.c +++ b/src/mainboard/lenovo/s230u/mainboard.c @@ -5,6 +5,7 @@ #include <drivers/intel/gma/int15.h> #include <ec/acpi/ec.h> #include <southbridge/intel/common/gpio.h> +#include <stdio.h> #include <string.h> #include <smbios.h> #include "ec.h" diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index d4b31afe88b7..6b721f3f74d5 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21ce inherit @@ -51,6 +58,24 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + # OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 + register "usb_port_config" = "{ + {1, 1, 0}, /* P0: system port 4, OC0 */ + {1, 1, 1}, /* P1: system port 2 (EHCI debug), OC 1 */ + {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */ + {1, 0, -1}, /* P3: WWAN, no OC */ + {1, 0, -1}, /* P4: smartcard, no OC */ + {1, 1, -1}, /* P5: ExpressCard, no OC */ + {0, 0, -1}, /* P6: empty */ + {0, 0, -1}, /* P7: empty */ + {1, 1, 4}, /* P8: system port 3, OC4*/ + {1, 1, 5}, /* P9: system port 1 (EHCI debug), OC 5 */ + {1, 0, -1}, /* P10: fingerprint reader, no OC */ + {1, 0, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: docking, no OC */ + {1, 1, -1} /* P13: camera (LCD), no OC */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c index c90221ed67cd..79e3cf7f5ac0 100644 --- a/src/mainboard/lenovo/t420/early_init.c +++ b/src/mainboard/lenovo/t420/early_init.c @@ -31,24 +31,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -// OC3 set in BIOS to port 2-7, OC7 set in BIOS to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index fb309170fe75..b35888506958 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -16,7 +16,14 @@ chip northbridge/intel/sandybridge register "gpu_pch_backlight" = "0x06100610" register "spd_addresses" = "{0x50, 0, 0x51, 0}" - + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21d2 inherit @@ -53,6 +60,23 @@ chip northbridge/intel/sandybridge register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" + register "usb_port_config" = "{ + {0, 1, -1}, /* P0: empty */ + {1, 1, 1}, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ + {1, 1, -1}, /* P2: HALF MINICARD (WLAN) no oc */ + {1, 0, -1}, /* P3: WWAN, no OC */ + {1, 1, -1}, /* P4: smartcard, no OC */ + {1, 1, -1}, /* P5: ExpressCard, no OC */ + {0, 0, -1}, /* P6: empty */ + {0, 0, -1}, /* P7: empty */ + {0, 1, -1}, /* P8: empty (touch panel) */ + {1, 0, 5}, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + {1, 0, -1}, /* P10: fingerprint reader, no OC */ + {1, 1, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: docking, no OC */ + {1, 1, -1} /* P13: camera (LCD), no OC */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c index e5e95b218a11..79e3cf7f5ac0 100644 --- a/src/mainboard/lenovo/t420s/early_init.c +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -31,23 +31,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0: empty */ - { 1, 1, 1 }, /* P1: system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 649254290619..f0f7975117c4 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -35,6 +35,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x7" register "xhci_switchable_ports" = "0x7" register "xhci_overcurrent_mapping" = "0x04000201" + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 2, 3 }, + { 1, 1, -1 }, + { 1, 1, 2 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 1, 2, -1 }, + { 1, 0, -1 }, + { 1, 1, 5 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 3, -1 }, + { 1, 1, -1 } + }" # device specific SPI configuration register "spi_uvscc" = "0x2005" diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c index 5e397ab7c433..86fcda8b37f0 100644 --- a/src/mainboard/lenovo/t430/early_init.c +++ b/src/mainboard/lenovo/t430/early_init.c @@ -33,24 +33,6 @@ static void hybrid_graphics_init(void) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } -/* FIXME: used T530 values here */ -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 2, 3 }, - { 1, 1, -1 }, - { 1, 1, 2 }, - { 1, 0, -1 }, - { 0, 0, -1 }, - { 1, 2, -1 }, - { 1, 0, -1 }, - { 1, 1, 5 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 3, -1 }, - { 1, 1, -1 }, -}; - void mainboard_early_init(int s3resume) { hybrid_graphics_init(); diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c index ea0f13f6df06..6ece6954fded 100644 --- a/src/mainboard/lenovo/t430/hda_verb.c +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -10,13 +10,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c index 8a663286f9a8..b891e854834c 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c @@ -31,19 +31,19 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), 0x01970804, 0x01870803, 0x01470740, 0x00970600, - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Misc entries */ 0x00370600, diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index 5677a8729a85..a9da73081511 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -2,6 +2,22 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P0:, OC 0 */ + { 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */ + { 1, 1, 3 }, /* P2: OC 3 */ + { 1, 0, -1 }, /* P3: no OC */ + { 1, 2, -1 }, /* P4: no OC */ + { 1, 1, -1 }, /* P5: no OC */ + { 1, 1, -1 }, /* P6: no OC */ + { 0, 1, -1 }, /* P7: empty, no OC */ + { 1, 1, -1 }, /* P8: smart card reader, no OC */ + { 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 0, 0, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" # Enable hotplug on Port 5 for Thunderbolt controller register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" device ref pcie_rp5 on end # Thunderbolt controller diff --git a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c index ec7683ab1d1a..e801e9ce4675 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x17, 0x40008000), AZALIA_PIN_CFG(0, 0x18, 0x03a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f38205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e839358ddf23..15712f941d85 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -23,6 +23,23 @@ chip northbridge/intel/sandybridge # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* SSP1: right */ + { 1, 0, 1 }, /* SSP2: left, EHCI Debug */ + { 1, 1, 3 }, /* SSP3: dock USB3 */ + { 1, 1, -1 }, /* B0P4: wwan USB */ + { 1, 1, 2 }, /* B0P5: dock USB2 */ + { 0, 0, -1 }, /* B0P6 */ + { 0, 0, -1 }, /* B0P7 */ + { 1, 2, -1 }, /* B0P8: unknown */ + { 1, 0, -1 }, /* B1P1: smart card reader */ + { 0, 2, 5 }, /* B1P2 */ + { 1, 1, -1 }, /* B1P3: fingerprint reader */ + { 0, 0, -1 }, /* B1P4 */ + { 1, 1, -1 }, /* B1P5: wlan USB */ + { 1, 1, -1 }, /* B1P6: Camera */ + }" + device ref pcie_rp1 on chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index a2e12c34d7f8..5edb63e95d35 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -15,6 +15,14 @@ chip northbridge/intel/sandybridge register "gpu_cpu_backlight" = "0x1155" register "gpu_pch_backlight" = "0x06100610" + chip cpu/intel/model_206ax + # Values obtained from vendor BIOS + register "pp0_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp0_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + register "pp1_psi[VR12_PSI2]" = "{VR12_ALL_PHASES, 5}" + register "pp1_psi[VR12_PSI3]" = "{VR12_ALL_PHASES, 1}" + device cpu_cluster 0 on end + end device domain 0 on subsystemid 0x17aa 0x21cf inherit diff --git a/src/mainboard/lenovo/t530/hda_verb.c b/src/mainboard/lenovo/t530/hda_verb.c index 05d62213cf51..564aff2d778f 100644 --- a/src/mainboard/lenovo/t530/hda_verb.c +++ b/src/mainboard/lenovo/t530/hda_verb.c @@ -34,16 +34,16 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), 0x01970804, 0x01870803, 0x01470740, 0x00970600, - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Misc entries */ 0x00370600, diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb index b574f367db56..3f058e385456 100644 --- a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -2,6 +2,22 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x51, 0}" device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ + { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ + { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ + { 1, 1, -1 }, /* P3: WWAN slot, no OC */ + { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ + { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 1, 2, -1 }, /* P7: docking, no OC */ + { 1, 0, -1 }, /* P8: smart card reader, no OC */ + { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb index 6b8638772649..a54db1efe2a4 100644 --- a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -5,6 +5,22 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21f5 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: USB double port upper, USB3, OC 0 */ + { 1, 1, 1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */ + { 1, 2, 3 }, /* P2: Dock, USB3, OC 3 */ + { 1, 1, -1 }, /* P3: WWAN slot, no OC */ + { 1, 1, 2 }, /* P4: yellow USB, OC 2 */ + { 1, 0, -1 }, /* P5: ExpressCard slot, no OC */ + { 1, 0, -1 }, /* P6: color sensor, no OC */ + { 1, 2, -1 }, /* P7: docking, no OC */ + { 1, 0, -1 }, /* P8: smart card reader, no OC */ + { 1, 1, 5 }, /* P9: USB port single (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/ + { 1, 1, -1 }, /* P13: camera, no OC */ + }" device ref me_kt on end device ref pcie_rp1 on chip drivers/ricoh/rce822 # Ricoh cardreader diff --git a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c index c1cf92baa400..594b9d7ea9a9 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c +++ b/src/mainboard/lenovo/thinkcentre_a58/hda_verb.c @@ -13,14 +13,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x99130120), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19830), AZALIA_PIN_CFG(0, 0x19, 0x02a19831), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), AZALIA_PIN_CFG(0, 0x1c, 0x593301f0), AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 96385ed2cdf3..b74e78f6c09e 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -43,6 +43,18 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x00000c03" + register "usb_port_config" = "{ + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, + {1, 0, -1} /* P13: Bluetooth (no OC) */ + }" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index a4232460519b..4abc9c0cd16f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -43,6 +43,22 @@ chip northbridge/intel/sandybridge register "xhci_switchable_ports" = "0xf" register "superspeed_capable_ports" = "0xf" register "xhci_overcurrent_mapping" = "0x4000201" + register "usb_port_config" = "{ + {0, 3, 0 }, /* P00 disconnected */ + {1, 1, 1 }, /* P01 left or right */ + {0, 1, 3 }, /* P02 disconnected */ + {1, 3, -1}, /* P03 WWAN */ + {0, 1, 2 }, /* P04 disconnected */ + {0, 1, -1}, /* P05 disconnected */ + {0, 1, -1}, /* P06 disconnected */ + {0, 2, -1}, /* P07 disconnected */ + {0, 1, -1}, /* P08 disconnected */ + {1, 2, 5 }, /* P09 left or right */ + {1, 3, -1}, /* P10 FPR */ + {1, 3, -1}, /* P11 Bluetooth */ + {1, 1, -1}, /* P12 WLAN */ + {1, 1, -1} /* P13 Camera */ + }" # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" diff --git a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c index 288d673bdf5f..069d483411d9 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/hda_verb.c @@ -10,13 +10,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk index b104bb52a98b..7e597079158a 100644 --- a/src/mainboard/lenovo/x220/Makefile.mk +++ b/src/mainboard/lenovo/x220/Makefile.mk @@ -2,7 +2,6 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c -romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index dc2f4a58586b..aaeecc824653 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -19,22 +19,6 @@ chip northbridge/intel/sandybridge register "ec_present" = "1" # I have an embedded controller register "max_mem_clock_mhz" = "666" # So DDR3 freq = 1333 - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 2, 0x0040 }, - { 1, 2, 0x0040 }, - { 1, 6, 0x0080 }, - { 1, 5, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 7, 0x0080 }, - { 1, 6, 0x0080 },}" - chip cpu/intel/model_206ax # Values obtained from vendor BIOS v1.46 # schematics say 33Amps for 17W TDP, 53Amps for 35W TDP diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index bf8815004422..cb1d12535954 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -16,6 +16,22 @@ chip northbridge/intel/sandybridge subsystemid 0x17aa 0x21e8 inherit chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 3 }, + { 0, 0, 3 }, + { 0, 0, 3 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 0, 7 }, + { 1, 1, 7 }, + { 1, 1, 7 }, + { 1, 0, 7 } + }" # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap) register "sata_port_map" = "0x1d" # X1 does not have ExpressCard slot diff --git a/src/mainboard/lenovo/x220/variants/x1/romstage.c b/src/mainboard/lenovo/x220/variants/x1/romstage.c deleted file mode 100644 index 593b7b2008d3..000000000000 --- a/src/mainboard/lenovo/x220/variants/x1/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 1, 3 }, - { 0, 0, 3 }, - { 0, 0, 3 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 0, 7 }, - { 1, 1, 7 }, - { 1, 1, 7 }, - { 1, 0, 7 }, -}; diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index b9caa255de7c..626f7eb3a677 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,6 +1,23 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "usb_port_config" = "{ + {1, 0, 0 }, + {1, 1, 1 }, + {1, 1, 3 }, + {1, 1, 3 }, + {1, 1, -1}, + {1, 1, -1}, + {1, 0, 2 }, + {1, 0, 2 }, + {1, 1, 6 }, + {1, 1, 5 }, + {1, 1, 6 }, + {1, 1, 6 }, + {1, 1, 7 }, + {1, 1, 6 }, + }" + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy diff --git a/src/mainboard/lenovo/x220/variants/x220/romstage.c b/src/mainboard/lenovo/x220/variants/x220/romstage.c deleted file mode 100644 index bd33cef65f3d..000000000000 --- a/src/mainboard/lenovo/x220/variants/x220/romstage.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <southbridge/intel/bd82x6x/pch.h> - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 1, 3 }, - { 1, 1, 3 }, - { 1, 1, -1 }, - { 1, 1, -1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 1, 6 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, - { 1, 1, 7 }, - { 1, 1, 6 }, -}; diff --git a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c index 05fb3fd775e7..153d08e3d8d2 100644 --- a/src/mainboard/lenovo/x230/variants/x230/hda_verb.c +++ b/src/mainboard/lenovo/x230/variants/x230/hda_verb.c @@ -35,10 +35,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x18, 0x03a11830), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40138205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Misc entries */ 0x01970804, diff --git a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb index d82faae94fd8..e7b06b6b2b42 100644 --- a/src/mainboard/lenovo/x230/variants/x230/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230/overridetree.cb @@ -3,6 +3,22 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "docking_supported" = "1" register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "usb_port_config" = "{ + {1, 0, 0 }, /* P0 (left, fan side), OC 0 */ + {1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ + {1, 1, 3 }, /* P2: dock, OC 3 */ + {1, 1, -1}, /* P3: wwan, no OC */ + {1, 1, -1}, /* P4: Wacom tablet on X230t, otherwise empty */ + {1, 1, -1}, /* P5: Expresscard, no OC */ + {0, 0, -1}, /* P6: Empty */ + {1, 2, -1}, /* P7: dock, no OC */ + {0, 0, -1}, /* P8: Empty */ + {1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ + {1, 1, -1}, /* P10: fingerprint reader, no OC */ + {1, 1, -1}, /* P11: bluetooth, no OC. */ + {1, 1, -1}, /* P12: wlan, no OC */ + {1, 1, -1}, /* P13: webcam, no OC */ + }" device ref pcie_rp3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end diff --git a/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c b/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c index 77919041e55b..bbc93d29ac22 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c +++ b/src/mainboard/lenovo/x230/variants/x230s/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x03211020), AZALIA_PIN_CFG(0, 0x17, 0x40008000), AZALIA_PIN_CFG(0, 0x18, 0x03a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f38205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x80862806, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb index 09e7f9289c8c..a84b5f3bdd15 100644 --- a/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb +++ b/src/mainboard/lenovo/x230/variants/x230s/overridetree.cb @@ -18,7 +18,22 @@ chip northbridge/intel/sandybridge # X230s does not support docking # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) register "sata_port_map" = "0x3" - + register "usb_port_config" = "{ + {1, 3, 0}, /* SSP1: Right */ + {1, 3, 1}, /* SSP2: Left, EHCI Debug */ + {0, 1, 3}, /* SSP3 */ + {1, 3, -1}, /* B0P4: WWAN USB */ + {0, 1, 2}, /* B0P5 */ + {0, 1, -1}, /* B0P6 */ + {0, 1, -1}, /* B0P7 */ + {0, 1, -1}, /* B0P8 */ + {0, 1, -1}, /* B1P1 */ + {0, 1, 5}, /* B1P2 */ + {1, 1, -1}, /* B1P3: Fingerprint Reader */ + {0, 1, -1}, /* B1P4 */ + {1, 3, -1}, /* B1P5: WLAN USB */ + {1, 1, -1}, /* B1P6: Camera */ + }" device ref lpc on chip ec/lenovo/h8 register "config1" = "0x05" diff --git a/src/mainboard/msi/h81m-p33/hda_verb.c b/src/mainboard/msi/h81m-p33/hda_verb.c index 735c026aedce..5c17ab3fee2c 100644 --- a/src/mainboard/msi/h81m-p33/hda_verb.c +++ b/src/mainboard/msi/h81m-p33/hda_verb.c @@ -8,19 +8,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x1462d817), AZALIA_PIN_CFG(0, 0x11, 0x4037c040), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19030), AZALIA_PIN_CFG(0, 0x19, 0x02a19040), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4025c603), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index 90eea95cb76f..df1696ae8b59 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -17,6 +17,22 @@ chip northbridge/intel/sandybridge register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "gpe0_en" = "0x28000040" + register "usb_port_config" = "{ + {1, 0, 0}, + {1, 0, 0}, + {1, 0, 1}, + {1, 0, 1}, + {1, 0, 2}, + {1, 0, 2}, + {1, 0, 3}, + {1, 0, 3}, + {1, 0, 4}, + {1, 0, 4}, + {1, 0, 6}, + {1, 0, 5}, + {1, 0, 5}, + {1, 0, 6} + }" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c index e574bb9b5d91..bfbde22a11e6 100644 --- a/src/mainboard/msi/ms7707/hda_verb.c +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -7,20 +7,20 @@ const u32 cim_verb_data[] = { 0x14627707, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x14627707), - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014410), AZALIA_PIN_CFG(0, 0x15, 0x01011412), AZALIA_PIN_CFG(0, 0x16, 0x01016411), AZALIA_PIN_CFG(0, 0x17, 0x01012414), AZALIA_PIN_CFG(0, 0x18, 0x01813c40), AZALIA_PIN_CFG(0, 0x19, 0x02a19c50), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1e, 0x01454130), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[0] = {}; diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig index 3fb6f40f5202..ab9fa2b4a8e2 100644 --- a/src/mainboard/msi/ms7d25/Kconfig +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -41,9 +41,6 @@ config MAINBOARD_VERSION string default "2.0" if BOARD_MSI_Z690_A_PRO_WIFI_DDR5 -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/msi/ms7d25/die.c b/src/mainboard/msi/ms7d25/die.c index 52b3338799f5..34fa75b1a3a5 100644 --- a/src/mainboard/msi/ms7d25/die.c +++ b/src/mainboard/msi/ms7d25/die.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <pc80/i8254.h> -#include <soc/gpio.h> #include <delay.h> #include <gpio.h> diff --git a/src/mainboard/msi/ms7d25/hda_verb.c b/src/mainboard/msi/ms7d25/hda_verb.c index 3ce5591f65c3..3906a84eb57a 100644 --- a/src/mainboard/msi/ms7d25/hda_verb.c +++ b/src/mainboard/msi/ms7d25/hda_verb.c @@ -9,7 +9,7 @@ const u32 cim_verb_data[] = { 15, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x14629d25), AZALIA_PIN_CFG(0, 0x11, 0x4037d540), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), @@ -18,10 +18,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x02a19040), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x402af66b), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* Alderlake HDMI */ 0x80862815, /* Vendor ID */ diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig index c46effc9caa9..cfa644798d58 100644 --- a/src/mainboard/msi/ms7e06/Kconfig +++ b/src/mainboard/msi/ms7e06/Kconfig @@ -34,9 +34,6 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY default "Default string" -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE default 0 diff --git a/src/mainboard/msi/ms7e06/die.c b/src/mainboard/msi/ms7e06/die.c index 52b3338799f5..34fa75b1a3a5 100644 --- a/src/mainboard/msi/ms7e06/die.c +++ b/src/mainboard/msi/ms7e06/die.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <pc80/i8254.h> -#include <soc/gpio.h> #include <delay.h> #include <gpio.h> diff --git a/src/mainboard/msi/ms7e06/hda_verb.c b/src/mainboard/msi/ms7e06/hda_verb.c index 90ca604b7a15..51f9a50dbfe9 100644 --- a/src/mainboard/msi/ms7e06/hda_verb.c +++ b/src/mainboard/msi/ms7e06/hda_verb.c @@ -9,7 +9,7 @@ const u32 cim_verb_data[] = { 15, /* Number of entries */ AZALIA_SUBVENDOR(0, 0x14629e06), AZALIA_PIN_CFG(0, 0x11, 0x4037d540), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), @@ -18,10 +18,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x19, 0x02a19040), AZALIA_PIN_CFG(0, 0x1a, 0x0181303f), AZALIA_PIN_CFG(0, 0x1b, 0x02214020), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x402af66b), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* Alderlake HDMI */ 0x80862818, /* Vendor ID */ diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index c1e8beef6982..844231991a93 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -20,11 +20,11 @@ DefinitionBlock( #include <cpu/intel/common/acpi/cpu.asl> // CPX-SP ACPI tables - #include <soc/intel/xeon_sp/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl> // LPC related entries Scope (\_SB.PC00) { - #include <soc/intel/xeon_sp/acpi/pch.asl> + #include <soc/intel/xeon_sp/acpi/gen1/pch.asl> } } diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 6dd7c109b3ca..55a10ad541ba 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -20,6 +20,7 @@ #include <soc/smmrelocate.h> #include <soc/soc_util.h> #include <soc/util.h> +#include <stdio.h> #include <string.h> #include <types.h> diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 06145c4d6dfa..49f20f1e6df9 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,9 +15,9 @@ DefinitionBlock( #include "acpi/platform.asl" #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> - #include <soc/intel/xeon_sp/acpi/uncore.asl> + #include <soc/intel/xeon_sp/acpi/gen1/uncore.asl> Scope (\_SB.PC00) { - #include <soc/intel/xeon_sp/acpi/pch.asl> + #include <soc/intel/xeon_sp/acpi/gen1/pch.asl> } } diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index ac5c92871f88..242ad9d932ed 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -16,7 +16,7 @@ #include <southbridge/amd/common/amd_pci_util.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> #include <AGESA.h> #include "gpio_ftns.h" diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index 5a3f3118d3c0..b40e2b796b3b 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -47,9 +47,6 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "Prodrive Technologies B.V." -config DIMM_SPD_SIZE - default 512 - config UART_FOR_CONSOLE int default 0 diff --git a/src/mainboard/prodrive/atlas/mainboard.c b/src/mainboard/prodrive/atlas/mainboard.c index 0128670d9c13..84888366559c 100644 --- a/src/mainboard/prodrive/atlas/mainboard.c +++ b/src/mainboard/prodrive/atlas/mainboard.c @@ -5,7 +5,7 @@ #include <device/device.h> #include <gpio.h> #include <smbios.h> -#include <string.h> +#include <stdio.h> #include <types.h> #include "gpio.h" diff --git a/src/mainboard/prodrive/atlas/vpd.c b/src/mainboard/prodrive/atlas/vpd.c index ba249a94d7a1..badbc6e3d19c 100644 --- a/src/mainboard/prodrive/atlas/vpd.c +++ b/src/mainboard/prodrive/atlas/vpd.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <stdio.h> #include <string.h> #include <types.h> diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index ea9f6731f7c9..ee73800c40ff 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -170,12 +170,7 @@ chip soc/intel/cannonlake # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. device ref i2c4 hidden end - device ref uart2 hidden # in ACPI mode - chip soc/intel/common/block/uart - register "devid" = "PCI_DID_INTEL_CNP_H_UART2" - device generic 0 hidden end - end - end + device ref uart2 hidden end # in ACPI mode device ref pcie_rp21 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" register "PcieRpEnable[20]" = "1" diff --git a/src/mainboard/prodrive/hermes/hda_verb.c b/src/mainboard/prodrive/hermes/hda_verb.c index cab4fd344b13..d1ad64f570c6 100644 --- a/src/mainboard/prodrive/hermes/hda_verb.c +++ b/src/mainboard/prodrive/hermes/hda_verb.c @@ -12,22 +12,22 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0, 0x1d336700), /* Pin widgets */ - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), /* SPDIF-OUT2 - disabled */ - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), /* digital MIC - disabled */ - AZALIA_PIN_CFG(0, 0x14, 0x01014430), /* PORT D - rear line out */ - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), /* PORT G - disabled */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), /* PORT H - disabled */ - AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), /* PORT B - rear mic in */ - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), /* CD audio - disabled */ - AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), /* BEEPIN */ - AZALIA_PIN_CFG(0, 0x1e, 0x01452160), /* SPDIF-OUT */ - AZALIA_PIN_CFG(0, 0x1f, 0x01c52170), /* SPDIF-IN */ + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), /* SPDIF-OUT2 - disabled */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* Digital MIC - disabled */ + AZALIA_PIN_CFG(0, 0x14, 0x01014430), /* Port D - rear line out */ + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), /* Port G - disabled */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* Port H - disabled */ + AZALIA_PIN_CFG(0, 0x18, 0x01a19c50), /* Port B - rear mic in */ + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), /* CD audio - disabled */ + AZALIA_PIN_CFG(0, 0x1d, 0x4004c601), /* BEEPIN */ + AZALIA_PIN_CFG(0, 0x1e, 0x01452160), /* SPDIF-OUT */ + AZALIA_PIN_CFG(0, 0x1f, 0x01c52170), /* SPDIF-IN */ /* Config for R02 and older */ - AZALIA_PIN_CFG(0, 0x19, 0x02214c40), /* port F - front hp out */ - AZALIA_PIN_CFG(0, 0x1a, 0x901001f0), /* port C - internal speaker */ - AZALIA_PIN_CFG(0, 0x1b, 0x01813c10), /* port E - rear line in/mic - Blue */ - AZALIA_PIN_CFG(0, 0x15, 0x02a19c20), /* port A - audio hdr input */ + AZALIA_PIN_CFG(0, 0x19, 0x02214c40), /* Port F - front hp out */ + AZALIA_PIN_CFG(0, 0x1a, 0x901001f0), /* Port C - internal speaker */ + AZALIA_PIN_CFG(0, 0x1b, 0x01813c10), /* Port E - rear line in/mic - Blue */ + AZALIA_PIN_CFG(0, 0x15, 0x02a19c20), /* Port A - audio hdr input */ /* * VerbTable: CFL Display Audio Codec @@ -67,10 +67,10 @@ const u32 pc_beep_verbs[0] = {}; AZALIA_ARRAY_SIZES; static const u32 r04_verb_data[] = { - AZALIA_PIN_CFG(0, 0x19, 0x02a19c20), /* PORT F - front mic in */ - AZALIA_PIN_CFG(0, 0x1a, 0x01813c51), /* PORT C - rear line in (mic support) */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* PORT E - disabled */ - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), /* PORT A - disabled */ + AZALIA_PIN_CFG(0, 0x19, 0x02a19c20), /* Port F - front mic in */ + AZALIA_PIN_CFG(0, 0x1a, 0x01813c51), /* Port C - rear line in (mic support) */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* Port E - disabled */ + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), /* Port A - disabled */ }; static u32 get_port_c_vref_cfg(uint8_t blue_rear_vref) @@ -95,15 +95,15 @@ static u32 get_port_b_vref_cfg(uint8_t pink_rear_vref) switch (pink_rear_vref) { default: case 0: - return 0x411110f0; /* Disabled (Hi-Z) */ + return 0; /* Disabled (Hi-Z) */ case 1: - return 0x411111f0; /* 50% of LDO out */ + return 1; /* 50% of LDO out */ case 2: - return 0x411114f0; /* 80% of LDO out */ + return 4; /* 80% of LDO out */ case 3: - return 0x411115f0; /* 100% of LDO out */ + return 5; /* 100% of LDO out */ case 4: - return 0x411112f0; /* Ground */ + return 2; /* Ground */ } } @@ -145,7 +145,7 @@ static void mainboard_r0x_configure_alc888(u8 *base, u32 viddid) * persist after codec resets, a custom Realtek driver (ab)uses NID 0x12 * to restore port B Vref after resetting the codec. */ - AZALIA_PIN_CFG(0, 0x12, port_b_vref_cfg), + AZALIA_PIN_CFG(0, 0x12, 0x411110f0 | port_b_vref_cfg << 8), AZALIA_PIN_CFG(0, 0x19, front_mic_cfg), AZALIA_PIN_CFG(0, 0x1b, front_panel_cfg), 0x0205000d, /* Pin 37 vrefo hidden register - used as port C vref */ diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index b0bf0dd98629..6d0da8d41150 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -16,6 +16,7 @@ #include <intelblocks/pmclib.h> #include <smbios.h> #include <soc/pm.h> +#include <stdio.h> #include <string.h> #include <types.h> diff --git a/src/mainboard/prodrive/hermes/smbios.c b/src/mainboard/prodrive/hermes/smbios.c index 923ce8170c3e..2f2869a9d507 100644 --- a/src/mainboard/prodrive/hermes/smbios.c +++ b/src/mainboard/prodrive/hermes/smbios.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <smbios.h> -#include <string.h> +#include <stdio.h> #include <types.h> #include "eeprom.h" diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig index 2389520ef89d..87de08829a8d 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig +++ b/src/mainboard/protectli/vault_cml/Kconfig @@ -1,11 +1,12 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_PROTECTLI_VP4630_VP4650 || BOARD_PROTECTLI_VP4670 +if BOARD_PROTECTLI_VP46XX config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select GFX_GMA_IGNORE_PRESENCE_STRAPS + select SOC_INTEL_COMETLAKE_1_2 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT @@ -15,8 +16,6 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LIBGFXINIT select MEMORY_MAPPED_TPM select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS - select SOC_INTEL_COMETLAKE_1 if BOARD_PROTECTLI_VP4670 - select SOC_INTEL_COMETLAKE_2 if BOARD_PROTECTLI_VP4630_VP4650 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPI_FLASH_MACRONIX select SUPERIO_ITE_IT8784E @@ -25,8 +24,7 @@ config MAINBOARD_DIR default "protectli/vault_cml" config MAINBOARD_PART_NUMBER - default "VP4630/VP4650" if BOARD_PROTECTLI_VP4630_VP4650 - default "VP4670" if BOARD_PROTECTLI_VP4670 + default "VP46XX" config MAINBOARD_FAMILY default "Vault Pro" diff --git a/src/mainboard/protectli/vault_cml/Kconfig.name b/src/mainboard/protectli/vault_cml/Kconfig.name index f0f3257f052c..1aaac81544f1 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig.name +++ b/src/mainboard/protectli/vault_cml/Kconfig.name @@ -1,7 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only -config BOARD_PROTECTLI_VP4630_VP4650 - bool "VP4630/VP4650" - -config BOARD_PROTECTLI_VP4670 - bool "VP4670" +config BOARD_PROTECTLI_VP46XX + bool "VP4630/VP4650/VP4670" diff --git a/src/mainboard/protectli/vault_cml/die.c b/src/mainboard/protectli/vault_cml/die.c index 52b3338799f5..34fa75b1a3a5 100644 --- a/src/mainboard/protectli/vault_cml/die.c +++ b/src/mainboard/protectli/vault_cml/die.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <pc80/i8254.h> -#include <soc/gpio.h> #include <delay.h> #include <gpio.h> diff --git a/src/mainboard/protectli/vault_cml/hda_verb.c b/src/mainboard/protectli/vault_cml/hda_verb.c index d0beefc042b8..7e49e99c1ab2 100644 --- a/src/mainboard/protectli/vault_cml/hda_verb.c +++ b/src/mainboard/protectli/vault_cml/hda_verb.c @@ -8,19 +8,19 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x10ec0662), AZALIA_PIN_CFG(0, 0x11, 0x40000000), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x04214110), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a19120), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40231105), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x8086280b, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/purism/librem_bdw/hda_verb.c b/src/mainboard/purism/librem_bdw/hda_verb.c index 1b031210536f..a3e87aad7b8f 100644 --- a/src/mainboard/purism/librem_bdw/hda_verb.c +++ b/src/mainboard/purism/librem_bdw/hda_verb.c @@ -12,13 +12,13 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0, 0x19910269), AZALIA_PIN_CFG(0, 0x12, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11020), AZALIA_PIN_CFG(0, 0x19, 0x90a70130), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40569d05), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x0421101f), }; diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c index 2fba59aa0856..70b3247c7499 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/hda_verb.c @@ -14,14 +14,14 @@ const u32 cim_verb_data[] = { AZALIA_SUBVENDOR(0, 0x10ec0256), AZALIA_PIN_CFG(0, 0x12, 0x90a60140), /* Front digital mic */ - AZALIA_PIN_CFG(0, 0x13, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x13, AZALIA_PIN_CFG_NC(0)), /* NC */ AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* Internal speakers */ - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), /* NC */ AZALIA_PIN_CFG(0, 0x19, 0x02a11030), /* Jack analog mic */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* NC */ AZALIA_PIN_CFG(0, 0x21, 0x02211020), /* Jack analog out */ /* Hidden SW reset */ diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c index 5a9aead2e72c..4734390cebe6 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/hda_verb.c @@ -10,16 +10,16 @@ const u32 cim_verb_data[] = { AZALIA_RESET(0x1), AZALIA_SUBVENDOR(0, 0x10ec0269), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x14, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_CFG_NC(0)), /* NC */ AZALIA_PIN_CFG(0, 0x15, 0x02211010), /* Jack analog out */ - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), /* NC */ AZALIA_PIN_CFG(0, 0x18, 0x02a11120), /* Jack analog mic, no presence detect */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), /* NC */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), /* NC */ + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), /* NC */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* NC */ 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/purism/librem_jsl/hda_verb.c b/src/mainboard/purism/librem_jsl/hda_verb.c index 5014ec4b3eac..81e950acff1d 100644 --- a/src/mainboard/purism/librem_jsl/hda_verb.c +++ b/src/mainboard/purism/librem_jsl/hda_verb.c @@ -14,11 +14,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x14, 0x90170110), /* FRONT */ AZALIA_PIN_CFG(0, 0x17, 0x40000000), /* N/C */ AZALIA_PIN_CFG(0, 0x18, 0x04a11020), /* MIC1 */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), /* N/C */ - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), /* N/C */ - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), /* N/C */ + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), /* N/C */ + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), /* N/C */ + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), /* N/C */ AZALIA_PIN_CFG(0, 0x1d, 0x40e38105), /* BEEP */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), /* N/C */ + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* N/C */ AZALIA_PIN_CFG(0, 0x21, 0x0421101f), /* HP-OUT */ /* EQ */ diff --git a/src/mainboard/purism/librem_skl/hda_verb.c b/src/mainboard/purism/librem_skl/hda_verb.c index ae76fb3ccad1..28f03626411a 100644 --- a/src/mainboard/purism/librem_skl/hda_verb.c +++ b/src/mainboard/purism/librem_skl/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x04214020), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a19040), AZALIA_PIN_CFG(0, 0x19, 0x90a70130), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40548505), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/raptor-cs/Kconfig b/src/mainboard/raptor-cs/Kconfig new file mode 100644 index 000000000000..3e9f7ade627b --- /dev/null +++ b/src/mainboard/raptor-cs/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_RAPTOR_CS + +choice + prompt "Mainboard model" + +source "src/mainboard/raptor-cs/*/Kconfig.name" + +endchoice + +source "src/mainboard/raptor-cs/*/Kconfig" + +config MAINBOARD_VENDOR + default "Raptor Computing Systems" + +endif # VENDOR_RAPTOR_CS diff --git a/src/mainboard/raptor-cs/Kconfig.name b/src/mainboard/raptor-cs/Kconfig.name new file mode 100644 index 000000000000..d1731095dd1d --- /dev/null +++ b/src/mainboard/raptor-cs/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_RAPTOR_CS + bool "Raptor Computing Systems" diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig b/src/mainboard/raptor-cs/talos-2/Kconfig new file mode 100644 index 000000000000..46513945e082 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/Kconfig @@ -0,0 +1,37 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_RAPTOR_CS_TALOS_2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_POWER9 + select SOC_IBM_POWER9 + select BOARD_ROMSIZE_KB_512 + select SUPERIO_ASPEED_AST2400 + select BOOT_DEVICE_NOT_SPI_FLASH + select MISSING_BOARD_RESET + select HAVE_DEBUG_RAM_SETUP + +config MEMLAYOUT_LD_FILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/memlayout.ld" + +config MAINBOARD_DIR + default "raptor-cs/talos-2" + +config MAINBOARD_PART_NUMBER + default "Talos II" + +config DIMM_MAX + default 8 + +config DIMM_SPD_SIZE + default 512 + +config MAX_CPUS + default 1 + +config DRAM_SIZE_MB + int + default 32768 + +endif # BOARD_RAPTOR_CS_TALOS_2 diff --git a/src/mainboard/raptor-cs/talos-2/Kconfig.name b/src/mainboard/raptor-cs/talos-2/Kconfig.name new file mode 100644 index 000000000000..8e4549af11e9 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_RAPTOR_CS_TALOS_2 + bool "Talos II" diff --git a/src/mainboard/raptor-cs/talos-2/board_info.txt b/src/mainboard/raptor-cs/talos-2/board_info.txt new file mode 100644 index 000000000000..aa2269185bec --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/board_info.txt @@ -0,0 +1,2 @@ +Board name: Raptor CS Talos II +Category: desktop diff --git a/src/mainboard/raptor-cs/talos-2/devicetree.cb b/src/mainboard/raptor-cs/talos-2/devicetree.cb new file mode 100644 index 000000000000..85440064fa47 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/devicetree.cb @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/ibm/power9 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/raptor-cs/talos-2/mainboard.c b/src/mainboard/raptor-cs/talos-2/mainboard.c new file mode 100644 index 000000000000..ef2dbd51bc20 --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/device.h> + +static void mainboard_enable(struct device *dev) +{ + if (!dev) + die("No dev0; die\n"); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/raptor-cs/talos-2/memlayout.ld b/src/mainboard/raptor-cs/talos-2/memlayout.ld new file mode 100644 index 000000000000..c5136b9d14ec --- /dev/null +++ b/src/mainboard/raptor-cs/talos-2/memlayout.ld @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> + +#include <arch/header.ld> + +// TODO: fill in these blanks for Power9. +SECTIONS +{ + DRAM_START(0x0) + BOOTBLOCK(0, 64K) + ROMSTAGE(0x120000, 128K) + STACK(0x140000, 0x3ff00) + PRERAM_CBMEM_CONSOLE(0x180000, 8K) + FMAP_CACHE(0x182000, 2K) + CBFS_MCACHE(0x182800, 8K) + RAMSTAGE(0x200000, 16M) +} diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig b/src/mainboard/razer/blade_stealth_kbl/Kconfig index 7c97676f859f..a527a9d04d7c 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig @@ -1,16 +1,12 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_RAZER_BLADE_STEALTH_KBL - -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_RAZER_BLADE_STEALTH_KBL + bool select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 select SUPERIO_ITE_IT8528E select SOC_INTEL_KABYLAKE select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select MEMORY_MAPPED_TPM - select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LIBGFXINIT select HAVE_SPD_IN_CBFS select DRIVERS_I2C_HID @@ -18,6 +14,32 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select DRIVERS_GENERIC_CBFS_SERIAL +config BOARD_RAZER_BLADE_H2U + select BOARD_RAZER_BLADE_STEALTH_KBL + select MEMORY_MAPPED_TPM + select MAINBOARD_HAS_TPM2 + +config BOARD_RAZER_BLADE_H3Q + select INTEL_GMA_HAVE_VBT + select BOARD_RAZER_BLADE_STEALTH_KBL + +if BOARD_RAZER_BLADE_STEALTH_KBL + +config VARIANT_DIR + default "h2u" if BOARD_RAZER_BLADE_H2U + default "h3q" if BOARD_RAZER_BLADE_H3Q + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_FAMILY + string + default "BLADE_STEALTH" + +config MAINBOARD_PART_NUMBER + default "H2U: RZ09-01962" if BOARD_RAZER_BLADE_H2U + default "H3Q: RZ09-01963/RZ09-01964" if BOARD_RAZER_BLADE_H3Q + # For now no way to choose the correct the available RAM config BOARD_RAZER_BLADE_STEALTH_KBL_16GB bool "16GB RAM (4x MT52L1G32D4PG)" @@ -27,13 +49,6 @@ config VGA_BIOS_ID string default "8086,5916" -config MAINBOARD_FAMILY - string - default "BLADE_STEALTH" - -config MAINBOARD_PART_NUMBER - default "H2U" - config MAINBOARD_VERSION string default "1.0" diff --git a/src/mainboard/razer/blade_stealth_kbl/Kconfig.name b/src/mainboard/razer/blade_stealth_kbl/Kconfig.name index 5ebc0ca9cc3b..ee73459ae511 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Kconfig.name +++ b/src/mainboard/razer/blade_stealth_kbl/Kconfig.name @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only -config BOARD_RAZER_BLADE_STEALTH_KBL - bool "Razer Blade Stealth KabyLake (2016)" +config BOARD_RAZER_BLADE_H2U + bool "Razer Blade Stealth KabyLake (2016, RZ09-01962, 12.5\")" + +config BOARD_RAZER_BLADE_H3Q + bool "Razer Blade Stealth KabyLake (Mid 2017, RZ09-01963/RZ09-10964, 13.3\")" diff --git a/src/mainboard/razer/blade_stealth_kbl/Makefile.mk b/src/mainboard/razer/blade_stealth_kbl/Makefile.mk index 0d4380a6f67c..fca5b055550e 100644 --- a/src/mainboard/razer/blade_stealth_kbl/Makefile.mk +++ b/src/mainboard/razer/blade_stealth_kbl/Makefile.mk @@ -3,6 +3,8 @@ subdirs-y += spd ramstage-y += ramstage.c -ramstage-y += hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/razer/blade_stealth_kbl/board_info.txt b/src/mainboard/razer/blade_stealth_kbl/board_info.txt index 414d880a12b1..6a5e685b7162 100644 --- a/src/mainboard/razer/blade_stealth_kbl/board_info.txt +++ b/src/mainboard/razer/blade_stealth_kbl/board_info.txt @@ -1,5 +1,5 @@ Vendor name: RAZER -Board name: Blade Stealth KabyLake (H2U) +Board name: Blade Stealth KabyLake Category: laptop ROM package: SOIC8 ROM protocol: SPI diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 132316481da1..71051be3b7e1 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -126,24 +126,6 @@ chip soc/intel/skylake register "PcieRpHotPlug[4]" = "1" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */ - [1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */ - [2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ - [3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ - [4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ - [5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ - [6] = USB2_PORT_FLEX(OC2), /* Camera */ - [7] = USB2_PORT_FLEX(OC2), /* Keyboard */ - [8] = USB2_PORT_FLEX(OC2), /* Touchscreen */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */ - [1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */ - [5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */ - }" - # PL1 override 25W # PL2 override 44W register "power_limits_config" = "{ @@ -170,7 +152,18 @@ chip soc/intel/skylake device cpu_cluster 0 on end device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end device ref sa_thermal on end device ref south_xhci on end device ref thermal on end @@ -191,9 +184,6 @@ chip soc/intel/skylake device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end chip superio/ite/it8528e device pnp 6e.1 off end device pnp 6e.2 off end diff --git a/src/mainboard/razer/blade_stealth_kbl/ramstage.c b/src/mainboard/razer/blade_stealth_kbl/ramstage.c index 7c05c6b77d76..5de606d807bc 100644 --- a/src/mainboard/razer/blade_stealth_kbl/ramstage.c +++ b/src/mainboard/razer/blade_stealth_kbl/ramstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/ramstage.h> -#include "gpio.h" +#include <variant/gpio.h> void mainboard_silicon_init_params(FSP_SIL_UPD *params) { diff --git a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h index 74b7c32489d8..2c0a16770eb4 100644 --- a/src/mainboard/razer/blade_stealth_kbl/spd/spd.h +++ b/src/mainboard/razer/blade_stealth_kbl/spd/spd.h @@ -4,7 +4,6 @@ #define MAINBOARD_SPD_H #include <gpio.h> -#include "../gpio.h" void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt new file mode 100644 index 000000000000..ffdbd5133050 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt @@ -0,0 +1,9 @@ +Vendor name: RAZER +Board name: Blade Stealth KabyLake (H2U: RZ09-01962) +Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3698/ +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2016 diff --git a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c index 63641dbdc0e9..6ed0ff334326 100644 --- a/src/mainboard/razer/blade_stealth_kbl/hda_verb.c +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c @@ -11,16 +11,16 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0xb7a60140), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x03a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4075a505), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x03211020), - /* Intel, KabylakeHDMI */ + /* Intel, Kaby Lake HDMI */ 0x8086280b, /* Vendor ID */ 0x80860101, /* Subsystem ID */ 4, /* Number of entries */ diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h index 4f9843268700..4f9843268700 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/include/variant/gpio.h diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb new file mode 100644 index 000000000000..d82147e7ee6d --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb @@ -0,0 +1,31 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC1), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC1), /* Type-A Port (left) */ + [2] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [3] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [4] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [5] = USB2_PORT_MID(OC1), /* TODO Unknown. Maybe USBC? */ + [6] = USB2_PORT_FLEX(OC2), /* Camera */ + [7] = USB2_PORT_FLEX(OC2), /* Keyboard */ + [8] = USB2_PORT_FLEX(OC2), /* Touchscreen */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (left) */ + [1] = USB3_PORT_DEFAULT(OC1), /* Type-A Port (right) */ + [5] = USB3_PORT_DEFAULT(OC1), /* TODO Unknown. Maybe USBC? */ + }" + end + + device ref lpc_espi on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + end +end diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt new file mode 100644 index 000000000000..5c801b5b447b --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt @@ -0,0 +1,9 @@ +Vendor name: RAZER +Board name: Blade Stealth KabyLake (H3Q: RZ09-01963 / RZ09-01964) +Board URL: https://mysupport.razer.com/app/answers/detail/a_id/3694/ +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h3q/data.vbt b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/data.vbt Binary files differnew file mode 100644 index 000000000000..0d163de8b4ef --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/data.vbt diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c new file mode 100644 index 000000000000..e6ac4810a757 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC298 */ + 0x10ec0298, /* Vendor ID */ + 0x1a586753, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1a586753), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4075812d), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + /* Intel, Kaby Lake HDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h new file mode 100644 index 000000000000..1f2397737d34 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/include/variant/gpio.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_A11, 0, DEEP), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A14, 0, DEEP), + PAD_CFG_GPO(GPP_A15, 0, DEEP), + PAD_CFG_GPO(GPP_A16, 0, DEEP), + PAD_CFG_GPO(GPP_A17, 0, DEEP), + PAD_CFG_GPO(GPP_A18, 0, DEEP), + PAD_CFG_GPO(GPP_A19, 0, DEEP), + PAD_CFG_GPO(GPP_A20, 0, DEEP), + PAD_CFG_GPO(GPP_A21, 0, DEEP), + PAD_CFG_GPO(GPP_A22, 0, DEEP), + PAD_CFG_GPO(GPP_A23, 0, DEEP), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B0, 0, DEEP), + PAD_CFG_GPO(GPP_B1, 0, DEEP), + PAD_CFG_GPO(GPP_B2, 0, DEEP), + PAD_CFG_GPO(GPP_B3, 0, DEEP), + PAD_CFG_GPO(GPP_B4, 0, DEEP), + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B8, 0, DEEP), + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B10, 0, DEEP), + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP), + PAD_CFG_GPO(GPP_B15, 0, DEEP), + PAD_CFG_GPO(GPP_B16, 0, DEEP), + PAD_CFG_GPO(GPP_B17, 0, DEEP), + PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + PAD_NC(GPP_B19, NONE), + PAD_CFG_NF(GPP_B20, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B21, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1), + PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPI_APIC_LOW(GPP_C5, DN_20K, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C10, 0, DEEP), + PAD_CFG_GPO(GPP_C11, 0, DEEP), + PAD_CFG_GPO(GPP_C12, 0, DEEP), + PAD_CFG_GPO(GPP_C13, 0, DEEP), + PAD_CFG_GPO(GPP_C14, 0, DEEP), + PAD_CFG_GPO(GPP_C15, 0, DEEP), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C23, 0, DEEP), + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 0, DEEP), + PAD_CFG_GPO(GPP_D1, 0, DEEP), + PAD_CFG_GPO(GPP_D2, 0, DEEP), + PAD_CFG_GPO(GPP_D3, 0, DEEP), + PAD_CFG_GPO(GPP_D4, 0, DEEP), + PAD_CFG_GPO(GPP_D5, 0, DEEP), + PAD_CFG_GPO(GPP_D6, 0, DEEP), + PAD_CFG_GPO(GPP_D7, 0, DEEP), + PAD_CFG_GPO(GPP_D8, 0, DEEP), + PAD_CFG_GPO(GPP_D9, 0, DEEP), + PAD_CFG_GPO(GPP_D10, 0, DEEP), + PAD_CFG_GPO(GPP_D11, 0, DEEP), + PAD_CFG_GPO(GPP_D12, 0, DEEP), + PAD_CFG_GPO(GPP_D13, 0, DEEP), + PAD_CFG_GPO(GPP_D14, 0, DEEP), + PAD_CFG_GPO(GPP_D15, 0, DEEP), + PAD_CFG_GPO(GPP_D16, 0, DEEP), + PAD_CFG_GPO(GPP_D17, 0, DEEP), + PAD_CFG_GPO(GPP_D18, 0, DEEP), + PAD_CFG_GPO(GPP_D19, 0, DEEP), + PAD_CFG_GPO(GPP_D20, 0, DEEP), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_CFG_GPO(GPP_D22, 0, DEEP), + PAD_CFG_GPO(GPP_D23, 0, DEEP), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + PAD_CFG_GPO(GPP_E1, 0, DEEP), + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E3, 0, DEEP), + PAD_CFG_GPO(GPP_E4, 0, DEEP), + PAD_CFG_GPI_SCI(GPP_E5, NONE, PLTRST, EDGE_SINGLE, INVERT), + PAD_CFG_GPO(GPP_E6, 0, DEEP), + PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_E9, 0, DEEP), + PAD_CFG_TERM_GPO(GPP_E10, 1, DN_20K, DEEP), + PAD_CFG_TERM_GPO(GPP_E11, 1, DN_20K, DEEP), + PAD_NC(GPP_E12, NONE), + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_CFG_GPI_SMI(GPP_E15, NONE, DEEP, EDGE_SINGLE, INVERT), + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_E22, 0, DEEP), + PAD_CFG_TERM_GPO(GPP_E23, 0, DN_20K, PLTRST), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 0, DEEP), + PAD_NC(GPD8, NONE), + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_GPO(GPP_F0, 0, DEEP), + PAD_CFG_GPO(GPP_F1, 0, DEEP), + PAD_CFG_GPO(GPP_F2, 0, DEEP), + PAD_CFG_GPO(GPP_F3, 0, DEEP), + PAD_CFG_GPO(GPP_F4, 0, DEEP), + PAD_CFG_GPO(GPP_F5, 0, DEEP), + PAD_CFG_GPO(GPP_F6, 0, DEEP), + PAD_CFG_GPO(GPP_F7, 0, DEEP), + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F10, 0, DEEP), + PAD_CFG_GPO(GPP_F11, 0, DEEP), + PAD_CFG_GPO(GPP_F12, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_F17, 0, DEEP), + PAD_CFG_GPO(GPP_F18, 0, DEEP), + PAD_CFG_GPO(GPP_F19, 0, DEEP), + PAD_CFG_GPO(GPP_F20, 0, DEEP), + PAD_CFG_GPO(GPP_F21, 0, DEEP), + PAD_CFG_GPO(GPP_F22, 0, DEEP), + PAD_CFG_GPO(GPP_F23, 0, DEEP), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 0, DEEP), + PAD_CFG_GPO(GPP_G1, 0, DEEP), + PAD_CFG_GPO(GPP_G2, 0, DEEP), + PAD_CFG_GPO(GPP_G3, 0, DEEP), + PAD_CFG_GPO(GPP_G4, 0, DEEP), + PAD_CFG_GPO(GPP_G5, 0, DEEP), + PAD_CFG_GPO(GPP_G6, 0, DEEP), + PAD_CFG_GPO(GPP_G7, 0, DEEP), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb new file mode 100644 index 000000000000..f7c0ac2593a0 --- /dev/null +++ b/src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb @@ -0,0 +1,23 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + device domain 0 on + device ref south_xhci on + # NOTE: TYPE-C port is controlled by Intel Thunderbolt + + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), /* Type-A Port (right) */ + [1] = USB2_PORT_MID(OC0), /* Type-A Port (left) */ + [5] = USB2_PORT_SHORT(OC2), /* M.2 Slot (Bluetooth) */ + [6] = USB2_PORT_FLEX(OC3), /* Camera */ + [7] = USB2_PORT_FLEX(OC3), /* Keyboard */ + [8] = USB2_PORT_FLEX(OC_SKIP), /* Touchscreen */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* Type-A Port (left) */ + [1] = USB3_PORT_DEFAULT(OC0), /* Type-A Port (right) */ + }" + end + end +end diff --git a/src/mainboard/roda/rk9/hda_verb.c b/src/mainboard/roda/rk9/hda_verb.c index ae98af711d29..37928450ae4e 100644 --- a/src/mainboard/roda/rk9/hda_verb.c +++ b/src/mainboard/roda/rk9/hda_verb.c @@ -11,17 +11,17 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb Table */ /* Pin Complex (NID 0x11), S/PDIF-OUT2: not connected */ - AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x14), LINE_OUT (port D): Speakers */ AZALIA_PIN_CFG(0, 0x14, 0x99130110), /* Pin Complex (NID 0x15), HP_OUT (port A): Head phones */ AZALIA_PIN_CFG(0, 0x15, 0x0121411f), /* Pin Complex (NID 0x16), MONO-OUT: not connected */ - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x18), MIC1 (port B): Microphone */ AZALIA_PIN_CFG(0, 0x18, 0x01a19920), /* Pin Complex (NID 0x19), MIC2 (port F): not connected */ - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1a), LINE1 (port C): Line-In */ AZALIA_PIN_CFG(0, 0x1a, 0x01813121), /* Pin Complex (NID 0x1b), LINE2 (port E): MDC */ @@ -31,9 +31,9 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x1d), PCBEEP */ AZALIA_PIN_CFG(0, 0x1d, 0x4014022d), /* Pin Complex (NID 0x1e), S/PDIF-OUT: not connected */ - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Pin Complex (NID 0x1f), S/PDIF-IN: not connected */ - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0) + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)) }; const u32 pc_beep_verbs[] = { diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 9da9cb88e14b..9f37526806e1 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -26,22 +26,6 @@ chip northbridge/intel/sandybridge register "ec_present" = "1" register "max_mem_clock_mhz" = "800" - register "usb_port_config" = "{ - { 1, 0, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 2, 0x0080 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 3, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end @@ -69,10 +53,25 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - register "xhci_overcurrent_mapping" = "0x00080401" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + { 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */ + { 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */ + { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */ + { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */ + { 1, 0, 8 }, /* P07: GPS USB2 (no OC) */ + { 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */ + { 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */ + { 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */ + { 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */ + { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */ + { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */ + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 5de8f563d6d7..66e3e520381f 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -8,21 +8,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled / Power / OC PIN */ - { 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */ - { 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */ - { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */ - { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */ - { 1, 0, 8 }, /* P07: GPS USB2 (no OC) */ - { 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */ - { 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */ - { 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */ - { 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */ - { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */ - { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */ -}; diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h index 36aa57f2697a..fae6d9527957 100644 --- a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h +++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h @@ -17,23 +17,23 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x01214020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4036a235), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* coreboot specific header */ 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 9dae3fffa638..5c3c72b517d6 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -25,21 +25,6 @@ chip northbridge/intel/sandybridge register "usb3.hs_port_switch_mask" = "0xf" register "usb3.preboot_support" = "1" register "usb3.xhci_streams" = "1" - register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0080 }, - { 1, 4, 0x0080 }, - { 1, 5, 0x0040 }, - { 1, 8, 0x0040 }, - { 1, 8, 0x0080 }, - { 1, 6, 0x0080 }, }" chip cpu/intel/model_206ax device cpu_cluster 0 on end @@ -73,10 +58,25 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "false" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }" - register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */ + { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */ + { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ + { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */ + { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ + { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ + { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */ + { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */ + { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */ + { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */ + { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */ + { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */ + { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ + { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ + }" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 451c4b795b9a..b791cbc77285 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,21 +40,3 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* TODO: Confirm if need to enable peg10 in devicetree */ pei_data->pcie_init = 1; } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* Enabled / Power / OC PIN */ - { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */ - { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */ - { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */ - { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */ - { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */ - { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */ - { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */ - { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */ - { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */ - { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */ - { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */ - { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */ - { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */ - { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */ -}; diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h index 2f4175605040..90eec45a9ad0 100644 --- a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h +++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h @@ -21,19 +21,19 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x18, 0x03a19040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x03813050), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40d6862d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), - AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), /* coreboot specific header */ 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */ diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index a8efd67da447..f5886f8b00e2 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -20,22 +20,6 @@ chip northbridge/intel/sandybridge register "ec_present" = "1" register "max_mem_clock_mhz" = "666" - register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 1, 0x0080 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 0, 4, 0x0000 },}" - device domain 0 on subsystemid 0x1ae0 0xc000 inherit device ref host_bridge on end # host bridge @@ -56,6 +40,22 @@ chip northbridge/intel/sandybridge register "gen1_dec" = "0x003c0a01" register "gen2_dec" = "0x003c0b01" register "gen3_dec" = "0x00fc1601" + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: Port 0 (OC0) */ + { 1, 1, 1 }, /* P1: Port 1 (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 0, 0, -1 }, /* P4: Empty */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */ + { 0, 0, -1 }, /* P9: Empty */ + { 0, 0, -1 }, /* P10: Empty */ + { 1, 0, -1 }, /* P11: Camera (no OC) */ + { 0, 0, -1 }, /* P12-13: Empty */ + { 0, 0, -1 } + }" device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 @@ -102,7 +102,7 @@ chip northbridge/intel/sandybridge end device ref sata1 on end # SATA Controller 1 device ref smbus on - subsystemid 0x04B4 0x18D1 + subsystemid 0x18D1 0x04B4 end # SMBus device ref sata2 off end # SATA Controller 2 device ref thermal on end # Thermal diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 5b355a206b28..b82d4d3411eb 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -108,24 +108,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) memcpy(pei_data->ts_addresses, &tsaddr, sizeof(pei_data->ts_addresses)); } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 1, 0 }, /* P0: Port 0 (OC0) */ - { 1, 1, 1 }, /* P1: Port 1 (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 0, 0, -1 }, /* P4: Empty */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */ - { 0, 0, -1 }, /* P9: Empty */ - { 0, 0, -1 }, /* P10: Empty */ - { 1, 0, -1 }, /* P11: Camera (no OC) */ - { 0, 0, -1 }, /* P12: Empty */ - { 0, 0, -1 }, /* P13: Empty */ -}; - void mb_get_spd_map(struct spd_info *spdi) { spdi->addresses[0] = 0x50; diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index bc24464733d4..4160479b8da8 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -12,22 +12,6 @@ chip northbridge/intel/sandybridge register "spd_addresses" = "{0x50, 0, 0x52, 0}" register "max_mem_clock_mhz" = "666" - register "usb_port_config" = "{ - { 1, 0, 0x0080 }, - { 1, 1, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 0, 0x0040 }, - { 1, 2, 0x0080 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 0, 0, 0x0000 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 1, 4, 0x0040 }, - { 0, 4, 0x0000 }, - { 1, 6, 0x0040 }, - { 1, 5, 0x0040 }, }" - chip cpu/intel/model_206ax device cpu_cluster 0 on end @@ -54,6 +38,23 @@ chip northbridge/intel/sandybridge # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" + register "usb_port_config" = "{ + { 1, 1, 0 }, /* P0: Front port (OC0) */ + { 1, 0, 1 }, /* P1: Back port (OC1) */ + { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ + { 1, 0, -1 }, /* P3: MMC (no OC) */ + { 1, 1, 2 }, /* P4: Front port (OC2) */ + { 0, 0, -1 }, /* P5: Empty */ + { 0, 0, -1 }, /* P6: Empty */ + { 0, 0, -1 }, /* P7: Empty */ + { 1, 0, 4 }, /* P8: Back port (OC4) */ + { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ + { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ + { 0, 0, -1 }, /* P11: Empty */ + { 1, 0, 6 }, /* P12: Back port (OC6) */ + { 1, 0, 5 }, /* P13: Back port (OC5) */ + }" + device ref mei1 on end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 2719e337e2a2..852759ead9e5 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -91,24 +91,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */ } -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power USB oc pin */ - { 1, 1, 0 }, /* P0: Front port (OC0) */ - { 1, 0, 1 }, /* P1: Back port (OC1) */ - { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ - { 1, 0, -1 }, /* P3: MMC (no OC) */ - { 1, 1, 2 }, /* P4: Front port (OC2) */ - { 0, 0, -1 }, /* P5: Empty */ - { 0, 0, -1 }, /* P6: Empty */ - { 0, 0, -1 }, /* P7: Empty */ - { 1, 0, 4 }, /* P8: Back port (OC4) */ - { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ - { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ - { 0, 0, -1 }, /* P11: Empty */ - { 1, 0, 6 }, /* P12: Back port (OC6) */ - { 1, 0, 5 }, /* P13: Back port (OC5) */ -}; - void bootblock_mainboard_early_init(void) { if (CONFIG(DRIVERS_UART_8250IO)) diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 87d1532df994..c44e2f37724a 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -9,6 +9,23 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" + register "spi.opprefixes" = "{ 0x50, 0x06 }" register "spi.ops" = "{{0x01, WRITE_NO_ADDR}, {0x02, WRITE_WITH_ADDR}, diff --git a/src/mainboard/sapphire/pureplatinumh61/early_init.c b/src/mainboard/sapphire/pureplatinumh61/early_init.c index 8749e499251b..b4bc1119f24e 100644 --- a/src/mainboard/sapphire/pureplatinumh61/early_init.c +++ b/src/mainboard/sapphire/pureplatinumh61/early_init.c @@ -8,20 +8,3 @@ void mainboard_pch_lpc_setup(void) { pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, - { 1, 0, 0 }, - { 1, 0, 1 }, - { 1, 0, 1 }, - { 1, 0, 2 }, - { 1, 0, 2 }, - { 1, 0, 3 }, - { 1, 0, 3 }, - { 1, 0, 4 }, - { 1, 0, 4 }, - { 1, 0, 6 }, - { 1, 0, 5 }, - { 1, 0, 5 }, - { 1, 0, 6 }, -}; diff --git a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c index ed7c8b3244a7..f87ab18b9b90 100644 --- a/src/mainboard/sapphire/pureplatinumh61/hda_verb.c +++ b/src/mainboard/sapphire/pureplatinumh61/hda_verb.c @@ -7,8 +7,8 @@ const u32 cim_verb_data[] = { 0x10ec0000, /* Subsystem ID */ 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(2, 0x10ec0000), - AZALIA_PIN_CFG(2, 0x11, 0x411111f0), - AZALIA_PIN_CFG(2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x14, 0x01014c10), AZALIA_PIN_CFG(2, 0x15, 0x01011c12), AZALIA_PIN_CFG(2, 0x16, 0x01016c11), @@ -17,10 +17,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(2, 0x19, 0x02a19c50), AZALIA_PIN_CFG(2, 0x1a, 0x01813c4f), AZALIA_PIN_CFG(2, 0x1b, 0x0321403f), - AZALIA_PIN_CFG(2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(2, 0x1d, 0x4005e601), AZALIA_PIN_CFG(2, 0x1e, 0x0145e130), - AZALIA_PIN_CFG(2, 0x1f, 0x411111f0), + AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)), 0x80862805, /* Codec Vendor / Device ID: Intel */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 4bc9b5f00750..3b8343bfe65d 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -7,21 +7,10 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - device cpu_cluster 0 on end - device domain 0 on - device ref system_agent on end - device ref peg0 off end - device ref peg1 off end - device ref peg2 off end device ref igpu on end device ref dptf on end - device ref ipu off end - device ref gna off end device ref thermal on end - device ref ufs off end - device ref gspi2 off end - device ref ish off end device ref xhci on # USB2 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? @@ -37,20 +26,7 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue end - device ref xdci off end device ref shared_sram on end - device ref cnvi_wifi off end - device ref sdxc off end - device ref i2c0 off end - device ref i2c1 off end - device ref i2c2 off end - device ref i2c3 off end - device ref heci1 on end - device ref heci2 off end - device ref csme_ider off end - device ref csme_ktr off end - device ref heci3 off end - device ref heci4 off end device ref sata on register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" # HDD / SSD @@ -60,14 +36,6 @@ chip soc/intel/cannonlake register "SataPortsDevSlp[0]" = "1" # M.2 register "SataPortsDevSlp[2]" = "1" # HDD / SSD end - device ref i2c4 off end - device ref i2c5 off end - device ref uart2 off end - device ref emmc off end - device ref pcie_rp1 off end - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on device pci 00.0 on end # x1 i219 register "PcieRpEnable[4]" = "1" @@ -87,15 +55,6 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[6]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end - device ref pcie_rp8 off end - device ref pcie_rp9 off end - device ref pcie_rp10 off end - device ref pcie_rp11 off end - device ref pcie_rp12 off end - device ref pcie_rp13 off end - device ref pcie_rp14 off end - device ref pcie_rp15 off end - device ref pcie_rp16 off end device ref pcie_rp17 on register "PcieRpEnable[16]" = "1" register "PcieClkSrcUsage[7]" = "16" @@ -103,28 +62,13 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[16]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end - device ref pcie_rp18 off end - device ref pcie_rp19 off end - device ref pcie_rp20 off end - device ref pcie_rp21 off end - device ref pcie_rp22 off end - device ref pcie_rp23 off end - device ref pcie_rp24 off end - device ref uart0 off end - device ref uart1 off end - device ref gspi0 off end - device ref gspi1 off end device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device ref p2sb hidden end - device ref pmc hidden end device ref hda on end device ref smbus on end - device ref fast_spi on end device ref gbe on end - device ref tracehub off end end end diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index b514d74cf118..d8bad2eb36e0 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -7,21 +7,10 @@ chip soc/intel/cannonlake register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - device cpu_cluster 0 on end - device domain 0 on - device ref system_agent on end - device ref peg0 off end - device ref peg1 off end - device ref peg2 off end device ref igpu on end device ref dptf on end - device ref ipu off end - device ref gna off end device ref thermal on end - device ref ufs off end - device ref gspi2 off end - device ref ish off end device ref xhci on # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Debug @@ -30,10 +19,7 @@ chip soc/intel/cannonlake # USB3 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Debug end - device ref xdci off end device ref shared_sram on end - device ref cnvi_wifi off end - device ref sdxc off end device ref i2c0 on chip drivers/secunet/dmi device i2c 0x57 on end # Serial EEPROM @@ -94,28 +80,11 @@ chip soc/intel/cannonlake }" end end - device ref i2c1 off end - device ref i2c2 off end - device ref i2c3 off end - device ref heci1 on end - device ref heci2 off end - device ref csme_ider off end - device ref csme_ktr off end - device ref heci3 off end - device ref heci4 off end - device ref sata off end - device ref i2c4 off end - device ref i2c5 off end - device ref uart2 off end - device ref emmc off end device ref pcie_rp1 off register "PcieRpEnable[0]" = "0" # Debug (x1) register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcClkReq[2]" = "2" end - device ref pcie_rp2 off end - device ref pcie_rp3 off end - device ref pcie_rp4 off end device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" # CORE (x1) register "PcieClkSrcUsage[4]" = "4" @@ -143,14 +112,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[7]" = "0" end - device ref pcie_rp9 off end - device ref pcie_rp10 off end - device ref pcie_rp11 off end - device ref pcie_rp12 off end - device ref pcie_rp13 off end - device ref pcie_rp14 off end - device ref pcie_rp15 off end - device ref pcie_rp16 off end device ref pcie_rp17 on register "PcieRpEnable[16]" = "1" # NVMe (x4) register "PcieClkSrcUsage[7]" = "16" @@ -158,28 +119,13 @@ chip soc/intel/cannonlake register "PcieRpSlotImplemented[16]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end - device ref pcie_rp18 off end - device ref pcie_rp19 off end - device ref pcie_rp20 off end - device ref pcie_rp21 off end - device ref pcie_rp22 off end - device ref pcie_rp23 off end - device ref pcie_rp24 off end device ref uart0 on end - device ref uart1 off end - device ref gspi0 off end - device ref gspi1 off end device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device ref p2sb hidden end - device ref pmc hidden end device ref hda on end device ref smbus on end - device ref fast_spi on end - device ref gbe off end - device ref tracehub off end end end diff --git a/src/mainboard/siemens/fa_ehl/Makefile.mk b/src/mainboard/siemens/fa_ehl/Makefile.mk index e34eddb9f19a..574d595079fc 100644 --- a/src/mainboard/siemens/fa_ehl/Makefile.mk +++ b/src/mainboard/siemens/fa_ehl/Makefile.mk @@ -1,7 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -subdirs-y += spd - bootblock-y += bootblock.c romstage-y += romstage_fsp_params.c diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h index 585cd6904740..f635aede5cac 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/include/baseboard/variants.h @@ -3,7 +3,7 @@ #ifndef _BASEBOARD_VARIANTS_H_ #define _BASEBOARD_VARIANTS_H_ -#include <soc/gpio.h> +#include <gpio.h> /* * The next set of functions return the gpio table and fill in the number of diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index 43697beab8a8..8fe9b93dd1c0 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -103,9 +103,6 @@ chip soc/intel/elkhartlake register "pse_tsn_phy_irq_edge[0]" = "RISING_EDGE" register "pse_tsn_phy_irq_edge[1]" = "RISING_EDGE" - register "DdiPortAHpd" = "1" - register "DdiPortADdc" = "1" - register "common_soc_config" = "{ .i2c[1] = { .speed = I2C_SPEED_STANDARD, diff --git a/src/mainboard/sifive/hifive-unleashed/devicetree.cb b/src/mainboard/sifive/hifive-unleashed/devicetree.cb index 796c232c2de2..02d8dee58ffe 100644 --- a/src/mainboard/sifive/hifive-unleashed/devicetree.cb +++ b/src/mainboard/sifive/hifive-unleashed/devicetree.cb @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only chip soc/sifive/fu540 - device cpu_cluster 0 on end + device cpu_cluster 0 on ops fu540_cpu_ops end end diff --git a/src/mainboard/starlabs/lite/Kconfig b/src/mainboard/starlabs/lite/Kconfig index 9d928b3801cc..f2c2ea650198 100644 --- a/src/mainboard/starlabs/lite/Kconfig +++ b/src/mainboard/starlabs/lite/Kconfig @@ -49,6 +49,15 @@ config DEVICETREE config EC_GPE_SCI default 0x26 +config EC_STARLABS_BATTERY_MODEL + default "3172120X2-I116CG" + +config EC_STARLABS_BATTERY_TYPE + default "LiP" + +config EC_STARLABS_BATTERY_OEM + default "Apower Electronics" + config EC_VARIANT_DIR default "glk" if BOARD_STARLABS_LITE_GLK default "glkr" if BOARD_STARLABS_LITE_GLKR diff --git a/src/mainboard/starlabs/lite/bootblock.c b/src/mainboard/starlabs/lite/bootblock.c index 91e2e23710cf..80e8b1811a49 100644 --- a/src/mainboard/starlabs/lite/bootblock.c +++ b/src/mainboard/starlabs/lite/bootblock.c @@ -2,7 +2,7 @@ #include <bootblock_common.h> #include <intelblocks/lpc_lib.h> -#include <soc/gpio.h> +#include <gpio.h> #include <variants.h> void bootblock_mainboard_init(void) diff --git a/src/mainboard/starlabs/lite/include/variants.h b/src/mainboard/starlabs/lite/include/variants.h index 0dd41c062ce5..5df05a3b62c9 100644 --- a/src/mainboard/starlabs/lite/include/variants.h +++ b/src/mainboard/starlabs/lite/include/variants.h @@ -3,7 +3,7 @@ #ifndef _BASEBOARD_VARIANTS_H_ #define _BASEBOARD_VARIANTS_H_ -#include <soc/gpio.h> +#include <gpio.h> enum cmos_power_profile { PP_POWER_SAVER = 0, diff --git a/src/mainboard/starlabs/lite/variants/glk/hda_verb.c b/src/mainboard/starlabs/lite/variants/glk/hda_verb.c index 36ac8f091ad3..0e8869c6c1f8 100644 --- a/src/mainboard/starlabs/lite/variants/glk/hda_verb.c +++ b/src/mainboard/starlabs/lite/variants/glk/hda_verb.c @@ -16,16 +16,16 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb-table */ AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x94171110), AZALIA_PIN_CFG(0, 0x15, 0x042b1010), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x93171110), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), 0x00370600, 0x00270600, diff --git a/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c b/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c index f873afa622ca..ebbd4606fe64 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c +++ b/src/mainboard/starlabs/lite/variants/glkr/hda_verb.c @@ -16,15 +16,15 @@ const u32 cim_verb_data[] = { /* Pin Widget Verb-table */ AZALIA_PIN_CFG(0, 0x01, 0x00000000), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x94171110), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x93171110), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x042b1010), 0x00370600, diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index a5ba41913490..480cc5cd61f8 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -30,7 +30,9 @@ config BOARD_STARLABS_LABTOP_KBL config BOARD_STARLABS_LABTOP_CML select BOARD_ROMSIZE_KB_16384 select BOARD_STARLABS_STARBOOK_SERIES + select EC_STARLABS_KBL_LEVELS select EC_STARLABS_MAX_CHARGE + select EC_STARLABS_MERLIN select EC_STARLABS_NEED_ITE_BIN select HAVE_INTEL_PTT select HAVE_SPD_IN_CBFS @@ -117,6 +119,17 @@ config EC_GPE_SCI config EC_STARLABS_ADD_ITE_BIN default y if !BOARD_STARLABS_STARBOOK_RPL +config EC_STARLABS_BATTERY_MODEL + default "AEC3987118-2S1P" if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML + default "597077-3S" + +config EC_STARLABS_BATTERY_TYPE + default "LION" + +config EC_STARLABS_BATTERY_OEM + default "Apower Electronics" if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML + default "GanfengLiEnergy" + config EC_STARLABS_ITE_BIN_PATH string depends on EC_STARLABS_NEED_ITE_BIN diff --git a/src/mainboard/starlabs/starbook/bootblock.c b/src/mainboard/starlabs/starbook/bootblock.c index ca48bb1ab22b..d30b61d3b10a 100644 --- a/src/mainboard/starlabs/starbook/bootblock.c +++ b/src/mainboard/starlabs/starbook/bootblock.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <soc/gpio.h> +#include <gpio.h> #include <variants.h> void bootblock_mainboard_init(void) diff --git a/src/mainboard/starlabs/starbook/hda_verb.c b/src/mainboard/starlabs/starbook/hda_verb.c index 371ab5d5f74e..699ff3410291 100644 --- a/src/mainboard/starlabs/starbook/hda_verb.c +++ b/src/mainboard/starlabs/starbook/hda_verb.c @@ -9,7 +9,7 @@ #define AZALIA_CODEC_ALC269 0x10ec0269 static const u32 override_verb[] = { - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), }; static void disable_microphone(u8 *base) diff --git a/src/mainboard/starlabs/starbook/include/variants.h b/src/mainboard/starlabs/starbook/include/variants.h index 0dd41c062ce5..5df05a3b62c9 100644 --- a/src/mainboard/starlabs/starbook/include/variants.h +++ b/src/mainboard/starlabs/starbook/include/variants.h @@ -3,7 +3,7 @@ #ifndef _BASEBOARD_VARIANTS_H_ #define _BASEBOARD_VARIANTS_H_ -#include <soc/gpio.h> +#include <gpio.h> enum cmos_power_profile { PP_POWER_SAVER = 0, diff --git a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c index c2d10ed324d7..507a0bcf8b4e 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c +++ b/src/mainboard/starlabs/starbook/variants/adl/hda_verb.c @@ -22,10 +22,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x17, 0x40000000), AZALIA_PIN_CFG(0, 0x18, 0x04a19030), AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x042b1010), /* ALC269 Default 1 */ diff --git a/src/mainboard/starlabs/starbook/variants/cml/devtree.c b/src/mainboard/starlabs/starbook/variants/cml/devtree.c index 6985c67d163a..95a5d44ea3c7 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/cml/devtree.c @@ -22,17 +22,17 @@ void devtree_update(void) disable_turbo(); soc_conf->tdp_pl1_override = 15; soc_conf->tdp_pl2_override = 15; - cfg->tcc_offset = 30; + cfg->tcc_offset = 20; break; case PP_BALANCED: soc_conf->tdp_pl1_override = 17; soc_conf->tdp_pl2_override = 20; - cfg->tcc_offset = 25; + cfg->tcc_offset = 15; break; case PP_PERFORMANCE: soc_conf->tdp_pl1_override = 20; soc_conf->tdp_pl2_override = 25; - cfg->tcc_offset = 20; + cfg->tcc_offset = 10; break; } diff --git a/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c b/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c index 76762a509c66..980cd2a09406 100644 --- a/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c +++ b/src/mainboard/starlabs/starbook/variants/cml/hda_verb.c @@ -19,12 +19,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a61120), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90171110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x40700001), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x042b1010), /* Reset to D0 */ diff --git a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c index 898519e87624..38017dc2e9c5 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/devtree.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/devtree.c @@ -17,19 +17,22 @@ void devtree_update(void) struct device *nic_dev = pcidev_on_root(0x1c, 5); /* Update PL1 & PL2 based on CMOS settings */ - switch (get_uint_option("power_profile", 0)) { - case 1: - soc_conf->tdp_pl1_override = 17; - soc_conf->tdp_pl2_override = 20; + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + disable_turbo(); + soc_conf->tdp_pl1_override = 15; + soc_conf->tdp_pl2_override = 15; + cfg->tcc_offset = 20; break; - case 2: - soc_conf->tdp_pl1_override = 20; - soc_conf->tdp_pl2_override = 25; + case PP_BALANCED: + soc_conf->tdp_pl1_override = 17; + soc_conf->tdp_pl2_override = 20; + cfg->tcc_offset = 15; break; - default: - disable_turbo(); - soc_conf->tdp_pl1_override = 15; - soc_conf->tdp_pl2_override = 15; + case PP_PERFORMANCE: + soc_conf->tdp_pl1_override = 20; + soc_conf->tdp_pl2_override = 25; + cfg->tcc_offset = 10; break; } diff --git a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c index d1e928eb1ab2..30d7c14ef546 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <option.h> #include <soc/romstage.h> #include <spd_bin.h> #include <string.h> diff --git a/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c index c2d10ed324d7..507a0bcf8b4e 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/hda_verb.c @@ -22,10 +22,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x17, 0x40000000), AZALIA_PIN_CFG(0, 0x18, 0x04a19030), AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x042b1010), /* ALC269 Default 1 */ diff --git a/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c index 7903d96259bc..71b96231e59a 100644 --- a/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c +++ b/src/mainboard/starlabs/starbook/variants/tgl/hda_verb.c @@ -19,12 +19,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a61120), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90171110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x19, 0x04ab1020), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x40700001), - AZALIA_PIN_CFG(0, 0x1d, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x042b1010), /* Reset to D0 */ diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index f5183819d179..acaae83182a0 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -26,6 +26,22 @@ chip northbridge/intel/sandybridge register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" device ref xhci on end # xHCI device ref mei1 on end # MEI #1 diff --git a/src/mainboard/supermicro/x9sae/hda_verb.c b/src/mainboard/supermicro/x9sae/hda_verb.c index 5feb74172ff4..255ecf9a8537 100644 --- a/src/mainboard/supermicro/x9sae/hda_verb.c +++ b/src/mainboard/supermicro/x9sae/hda_verb.c @@ -8,16 +8,16 @@ const u32 cim_verb_data[] = { 15, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x15d90644), AZALIA_PIN_CFG(0, 0x11, 0x18561120), - AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x14, 0x01014010), AZALIA_PIN_CFG(0, 0x15, 0x01011012), AZALIA_PIN_CFG(0, 0x16, 0x01016011), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x01a19840), AZALIA_PIN_CFG(0, 0x19, 0x02a19841), AZALIA_PIN_CFG(0, 0x1a, 0x0181344f), AZALIA_PIN_CFG(0, 0x1b, 0x0221401f), - AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x4007e619), AZALIA_PIN_CFG(0, 0x1e, 0x01452130), AZALIA_PIN_CFG(0, 0x1f, 0x01c41150), diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index 203a7a64ee6b..7240d6dbd435 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -17,6 +17,24 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + + register "usb_port_config" = "{ + { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ + { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ + { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ + { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ + { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ + { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ + { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ + { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ + { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ + { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ + { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ + { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ + { 1, 0, 5 }, + { 1, 0, 6 } + }" + device ref mei1 off end # Management Engine Interface 1 device ref mei2 off end # Management Engine Interface 2 device ref me_ide_r off end # Management Engine IDE-R diff --git a/src/mainboard/system76/addw1/cmos.layout b/src/mainboard/system76/addw1/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/addw1/cmos.layout +++ b/src/mainboard/system76/addw1/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/addw1/devicetree.cb b/src/mainboard/system76/addw1/devicetree.cb index 529767c56833..16827ddb6f41 100644 --- a/src/mainboard/system76/addw1/devicetree.cb +++ b/src/mainboard/system76/addw1/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c index aedd2853fde8..340d97d2f0e3 100644 --- a/src/mainboard/system76/addw1/variants/addw1/hda_verb.c +++ b/src/mainboard/system76/addw1/variants/addw1/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D) AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A) - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // CENTER/LFE (Port-G) - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // SIDE (Port-H) + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), // CENTER/LFE (Port-G) + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), // SIDE (Port-H) AZALIA_PIN_CFG(0, 0x18, 0x04a11040), // MIC1 (Port-B) - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // MIC2 (Port-F) - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // LINE1 (Port-C) + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // LINE1 (Port-C) AZALIA_PIN_CFG(0, 0x1b, 0x90170110), // LINE2 (Port-E) AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), // PCBEEP AZALIA_PIN_CFG(0, 0x1e, 0x04451150), // S/PDIF-OUT diff --git a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb index fa327fd1ad45..b1fab297f75e 100644 --- a/src/mainboard/system76/addw1/variants/addw1/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw1/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c index 8175c9bb4a76..54ff866b50c5 100644 --- a/src/mainboard/system76/addw1/variants/addw2/hda_verb.c +++ b/src/mainboard/system76/addw1/variants/addw2/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), // DMIC AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D) AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A) - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // CENTER/LFE (Port-G) - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // SIDE (Port-H) + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), // CENTER/LFE (Port-G) + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), // SIDE (Port-H) AZALIA_PIN_CFG(0, 0x18, 0x04a11040), // MIC1 (Port-B) - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // MIC2 (Port-F) - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // LINE1 (Port-C) + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // LINE1 (Port-C) AZALIA_PIN_CFG(0, 0x1b, 0x90170110), // LINE2 (Port-E) AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), // PCBEEP AZALIA_PIN_CFG(0, 0x1e, 0x04451150), // S/PDIF-OUT diff --git a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb index 40e2128db3d4..3b9c5627cf96 100644 --- a/src/mainboard/system76/addw1/variants/addw2/overridetree.cb +++ b/src/mainboard/system76/addw1/variants/addw2/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index 5213cfeaac84..3d364f14828d 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -103,9 +103,6 @@ config CONSOLE_POST config D3COLD_SUPPORT default n -config DIMM_SPD_SIZE - default 512 - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/system76/adl/cmos.layout b/src/mainboard/system76/adl/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/adl/cmos.layout +++ b/src/mainboard/system76/adl/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/adl/devicetree.cb b/src/mainboard/system76/adl/devicetree.cb index 9a7841506c89..9a7a14963aaf 100644 --- a/src/mainboard/system76/adl/devicetree.cb +++ b/src/mainboard/system76/adl/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/adl/variants/darp8/hda_verb.c b/src/mainboard/system76/adl/variants/darp8/hda_verb.c index df2f8195dc41..cbfee1ff5d06 100644 --- a/src/mainboard/system76/adl/variants/darp8/hda_verb.c +++ b/src/mainboard/system76/adl/variants/darp8/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/adl/variants/darp8/overridetree.cb b/src/mainboard/system76/adl/variants/darp8/overridetree.cb index 73d016f17dc9..7a7e14ee9963 100644 --- a/src/mainboard/system76/adl/variants/darp8/overridetree.cb +++ b/src/mainboard/system76/adl/variants/darp8/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 20, diff --git a/src/mainboard/system76/adl/variants/galp6/hda_verb.c b/src/mainboard/system76/adl/variants/galp6/hda_verb.c index 4f2892570e36..8679812a0c1b 100644 --- a/src/mainboard/system76/adl/variants/galp6/hda_verb.c +++ b/src/mainboard/system76/adl/variants/galp6/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/adl/variants/galp6/overridetree.cb b/src/mainboard/system76/adl/variants/galp6/overridetree.cb index a0a0ad26cfe7..79c614e761f2 100644 --- a/src/mainboard/system76/adl/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl/variants/galp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ .tdp_pl1_override = 28, diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c index 337f469b0b25..804214331445 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c +++ b/src/mainboard/system76/adl/variants/gaze17-3050/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb index 960ead6e5cb6..603879bb8bd5 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # FIVR configuration # Read EXT_RAIL_CONFIG to determine bitmaps diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c index f28070ca9dd9..4a17c369f68d 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb index 74b87ee60e15..a9c614e42442 100644 --- a/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb +++ b/src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # FIVR configuration # Read EXT_RAIL_CONFIG to determine bitmaps diff --git a/src/mainboard/system76/adl/variants/lemp11/hda_verb.c b/src/mainboard/system76/adl/variants/lemp11/hda_verb.c index 7db57e72bbf0..699031759e69 100644 --- a/src/mainboard/system76/adl/variants/lemp11/hda_verb.c +++ b/src/mainboard/system76/adl/variants/lemp11/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb index 1e652483a9a5..10c6bfcf314b 100644 --- a/src/mainboard/system76/adl/variants/lemp11/overridetree.cb +++ b/src/mainboard/system76/adl/variants/lemp11/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/system76/adl/variants/oryp10/hda_verb.c b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c index 3e1ec904250b..60f0266a2307 100644 --- a/src/mainboard/system76/adl/variants/oryp10/hda_verb.c +++ b/src/mainboard/system76/adl/variants/oryp10/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), AZALIA_PIN_CFG(0, 0x1e, 0x04451150), diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb index efebe7af91d7..09f07b6cced2 100644 --- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/adl/variants/oryp9/hda_verb.c b/src/mainboard/system76/adl/variants/oryp9/hda_verb.c index 31d93a956109..d9915c619d40 100644 --- a/src/mainboard/system76/adl/variants/oryp9/hda_verb.c +++ b/src/mainboard/system76/adl/variants/oryp9/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), AZALIA_PIN_CFG(0, 0x1e, 0x04451150), diff --git a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb index 2f79c9edeb66..4ca81ab12b75 100644 --- a/src/mainboard/system76/adl/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl/variants/oryp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/bonw14/cmos.layout b/src/mainboard/system76/bonw14/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/bonw14/cmos.layout +++ b/src/mainboard/system76/bonw14/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb index d79aa7665927..aa7d1abb5e40 100644 --- a/src/mainboard/system76/bonw14/devicetree.cb +++ b/src/mainboard/system76/bonw14/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/bonw14/hda_verb.c b/src/mainboard/system76/bonw14/hda_verb.c index dfe3187ce4a4..5b6c4f4c5c04 100644 --- a/src/mainboard/system76/bonw14/hda_verb.c +++ b/src/mainboard/system76/bonw14/hda_verb.c @@ -11,12 +11,12 @@ const u32 cim_verb_data[] = { AZALIA_RESET(1), AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x40000000), - AZALIA_PIN_CFG(0, 0x15, 0x411111f0), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x4094022d), AZALIA_PIN_CFG(0, 0x1e, 0x04451120), diff --git a/src/mainboard/system76/cml-u/cmos.layout b/src/mainboard/system76/cml-u/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/cml-u/cmos.layout +++ b/src/mainboard/system76/cml-u/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index 90c5b719b00d..07c56b4b9f3c 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ /* Touchpad */ diff --git a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c index 95f9d4317147..59dc7b846524 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/darp6/hda_verb.c @@ -13,11 +13,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x02a11050), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41738205), AZALIA_PIN_CFG(0, 0x1e, 0x02451130), diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index b34976201c4f..17b1ba14f803 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1404 inherit diff --git a/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c b/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c index 2030d0034e7f..b96f726f7618 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/galp4/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x02a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41738205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index bbfc2ea20887..9c747cf18053 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1403 inherit diff --git a/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c index 1b9386d3881d..5a520ed459a4 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c +++ b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x01a1913c), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41748245), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Intel GPU HDMI */ 0x8086280b, /* Vendor ID */ diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb index 164774a42db5..2279cb33cbf0 100644 --- a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1401 inherit diff --git a/src/mainboard/system76/gaze15/cmos.layout b/src/mainboard/system76/gaze15/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/gaze15/cmos.layout +++ b/src/mainboard/system76/gaze15/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 4ae412d15564..f80c45c0bae5 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c index 6bc881bfcc3f..fe08d03dd523 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c +++ b/src/mainboard/system76/gaze15/variants/gaze14/hda_verb.c @@ -15,10 +15,10 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x17, 0x40000000), AZALIA_PIN_CFG(0, 0x18, 0x02a11030), AZALIA_PIN_CFG(0, 0x19, 0x02a1103f), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f00001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb index 0cfd040a737a..e94d703a19c6 100644 --- a/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb +++ b/src/mainboard/system76/gaze15/variants/gaze14/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c index 761386a06462..d6c3f28a8f25 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c +++ b/src/mainboard/system76/gaze15/variants/gaze15/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x02a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41738205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb index 9f64b5f4ca02..02275df10b63 100644 --- a/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb +++ b/src/mainboard/system76/gaze15/variants/gaze15/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Serial I/O register "SerialIoDevMode" = "{ diff --git a/src/mainboard/system76/kbl-u/cmos.layout b/src/mainboard/system76/kbl-u/cmos.layout index 4e9a300ebf3a..7aec087ea39f 100644 --- a/src/mainboard/system76/kbl-u/cmos.layout +++ b/src/mainboard/system76/kbl-u/cmos.layout @@ -12,7 +12,10 @@ entries 400 8 r 0 century 412 4 e 6 debug_level -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -32,4 +35,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 3b84d7fdbff3..da3327ac4c23 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" diff --git a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c index 208107ce36c5..f2ff8bd336cd 100644 --- a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c @@ -14,11 +14,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x02211010), AZALIA_PIN_CFG(0, 0x17, 0x40000000), AZALIA_PIN_CFG(0, 0x18, 0x02a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Intel, KabylakeHDMI */ 0x8086280b, /* Vendor ID */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb index 9e042a335bbe..8fb495bec994 100644 --- a/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp2/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1303 inherit diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c index 2e43bef9b7c3..affce10c387d 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c @@ -14,11 +14,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x02211010), AZALIA_PIN_CFG(0, 0x17, 0x40000000), AZALIA_PIN_CFG(0, 0x18, 0x02a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Intel, KabylakeHDMI */ 0x8086280b, /* Vendor ID */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb index 134fbec7a7d8..5cc90b269d3a 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1413 inherit diff --git a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c index de588d5d4e06..66222e1a9cd2 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c +++ b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c @@ -14,11 +14,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x15, 0x02211010), AZALIA_PIN_CFG(0, 0x17, 0x40000000), AZALIA_PIN_CFG(0, 0x18, 0x02a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Intel, KabylakeHDMI */ 0x8086280b, /* Vendor ID */ 0x80860101, /* Subsystem ID */ diff --git a/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb b/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb index 8a61f28069cb..d18dfa449e55 100644 --- a/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb +++ b/src/mainboard/system76/kbl-u/variants/galp3/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/skylake device domain 0 on subsystemid 0x1558 0x1313 inherit diff --git a/src/mainboard/system76/oryp5/cmos.layout b/src/mainboard/system76/oryp5/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/oryp5/cmos.layout +++ b/src/mainboard/system76/oryp5/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index f17862f4af98..ae521655cce4 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/oryp5/hda_verb.c b/src/mainboard/system76/oryp5/hda_verb.c index 575c83947452..3f63cb3bc56c 100644 --- a/src/mainboard/system76/oryp5/hda_verb.c +++ b/src/mainboard/system76/oryp5/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60140), // DMIC AZALIA_PIN_CFG(0, 0x14, 0x0421101f), // FRONT (Port-D) AZALIA_PIN_CFG(0, 0x15, 0x40000000), // SURR (Port-A) - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), // CENTER/LFE (Port-G) - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), // SIDE (Port-H) + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), // CENTER/LFE (Port-G) + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), // SIDE (Port-H) AZALIA_PIN_CFG(0, 0x18, 0x04a11050), // MIC1 (Port-B) - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), // MIC2 (Port-F) - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), // LINE1 (Port-C) + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), // MIC2 (Port-F) + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), // LINE1 (Port-C) AZALIA_PIN_CFG(0, 0x1b, 0x90170110), // LINE2 (Port-E) AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), // PCBEEP AZALIA_PIN_CFG(0, 0x1e, 0x04451130), // S/PDIF-OUT diff --git a/src/mainboard/system76/oryp6/cmos.layout b/src/mainboard/system76/oryp6/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/oryp6/cmos.layout +++ b/src/mainboard/system76/oryp6/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index c0c1b4a12a1a..abf68b9e1603 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c index 2f30d40bbef5..f9f6746c5559 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c +++ b/src/mainboard/system76/oryp6/variants/oryp6/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), AZALIA_PIN_CFG(0, 0x1e, 0x04451150), diff --git a/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb index 3d6355e6b036..3b2748f69f0b 100644 --- a/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb +++ b/src/mainboard/system76/oryp6/variants/oryp6/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x50d3 inherit diff --git a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c index d251b33db838..c46b63e60de9 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c +++ b/src/mainboard/system76/oryp6/variants/oryp7/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), AZALIA_PIN_CFG(0, 0x1e, 0x04451150), diff --git a/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb index 3be1b157f16d..b9bb816b8989 100644 --- a/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb +++ b/src/mainboard/system76/oryp6/variants/oryp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x65e5 inherit diff --git a/src/mainboard/system76/rpl/Kconfig b/src/mainboard/system76/rpl/Kconfig index 2a850ae0894d..20a09b609258 100644 --- a/src/mainboard/system76/rpl/Kconfig +++ b/src/mainboard/system76/rpl/Kconfig @@ -32,6 +32,12 @@ config BOARD_SYSTEM76_ADDW3 select PCIEXP_HOTPLUG select SOC_INTEL_ALDERLAKE_PCH_S +config BOARD_SYSTEM76_ADDW4 + select BOARD_SYSTEM76_RPL_COMMON + select EC_SYSTEM76_EC_DGPU + select PCIEXP_HOTPLUG + select SOC_INTEL_ALDERLAKE_PCH_S + config BOARD_SYSTEM76_BONW15 select BOARD_SYSTEM76_RPL_COMMON select EC_SYSTEM76_EC_DGPU @@ -65,6 +71,13 @@ config BOARD_SYSTEM76_ORYP11 select SOC_INTEL_ALDERLAKE_PCH_P select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES +config BOARD_SYSTEM76_ORYP12 + select BOARD_SYSTEM76_RPL_COMMON + select DRIVERS_I2C_TAS5825M + select EC_SYSTEM76_EC_DGPU + select PCIEXP_HOTPLUG + select SOC_INTEL_ALDERLAKE_PCH_S + config BOARD_SYSTEM76_SERW13 select BOARD_SYSTEM76_RPL_COMMON select EC_SYSTEM76_EC_DGPU @@ -78,12 +91,14 @@ config MAINBOARD_DIR config VARIANT_DIR default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 default "gaze18" if BOARD_SYSTEM76_GAZE18 default "lemp12" if BOARD_SYSTEM76_LEMP12 default "oryp11" if BOARD_SYSTEM76_ORYP11 + default "oryp12" if BOARD_SYSTEM76_ORYP12 default "serw13" if BOARD_SYSTEM76_SERW13 config OVERRIDE_DEVICETREE @@ -91,32 +106,36 @@ config OVERRIDE_DEVICETREE config MAINBOARD_PART_NUMBER default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 default "gaze18" if BOARD_SYSTEM76_GAZE18 default "lemp12" if BOARD_SYSTEM76_LEMP12 default "oryp11" if BOARD_SYSTEM76_ORYP11 + default "oryp12" if BOARD_SYSTEM76_ORYP12 default "serw13" if BOARD_SYSTEM76_SERW13 config MAINBOARD_SMBIOS_PRODUCT_NAME - default "Adder WS" if BOARD_SYSTEM76_ADDW3 + default "Adder WS" if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 default "Bonobo WS" if BOARD_SYSTEM76_BONW15 default "Darter Pro" if BOARD_SYSTEM76_DARP9 default "Galago Pro" if BOARD_SYSTEM76_GALP7 default "Gazelle" if BOARD_SYSTEM76_GAZE18 default "Lemur Pro" if BOARD_SYSTEM76_LEMP12 - default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 + default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 default "Serval WS" if BOARD_SYSTEM76_SERW13 config MAINBOARD_VERSION default "addw3" if BOARD_SYSTEM76_ADDW3 + default "addw4" if BOARD_SYSTEM76_ADDW4 default "bonw15" if BOARD_SYSTEM76_BONW15 default "darp9" if BOARD_SYSTEM76_DARP9 default "galp7" if BOARD_SYSTEM76_GALP7 default "gaze18" if BOARD_SYSTEM76_GAZE18 default "lemp12" if BOARD_SYSTEM76_LEMP12 default "oryp11" if BOARD_SYSTEM76_ORYP11 + default "oryp12" if BOARD_SYSTEM76_ORYP12 default "serw13" if BOARD_SYSTEM76_SERW13 config CONSOLE_POST @@ -125,9 +144,6 @@ config CONSOLE_POST config D3COLD_SUPPORT default n -config DIMM_SPD_SIZE - default 512 - config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index da5d400d8c2a..41842651f16c 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -3,6 +3,9 @@ config BOARD_SYSTEM76_ADDW3 bool "addw3" +config BOARD_SYSTEM76_ADDW4 + bool "addw4" + config BOARD_SYSTEM76_BONW15 bool "bonw15" @@ -21,5 +24,8 @@ config BOARD_SYSTEM76_LEMP12 config BOARD_SYSTEM76_ORYP11 bool "oryp11" +config BOARD_SYSTEM76_ORYP12 + bool "oryp12" + config BOARD_SYSTEM76_SERW13 bool "serw13" diff --git a/src/mainboard/system76/rpl/Makefile.mk b/src/mainboard/system76/rpl/Makefile.mk index cf92eb2b437e..2c8dfba322e5 100644 --- a/src/mainboard/system76/rpl/Makefile.mk +++ b/src/mainboard/system76/rpl/Makefile.mk @@ -10,5 +10,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD diff --git a/src/mainboard/system76/rpl/cmos.layout b/src/mainboard/system76/rpl/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/rpl/cmos.layout +++ b/src/mainboard/system76/rpl/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/rpl/devicetree.cb b/src/mainboard/system76/rpl/devicetree.cb index d389d2175bf7..749ce5344b93 100644 --- a/src/mainboard/system76/rpl/devicetree.cb +++ b/src/mainboard/system76/rpl/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "common_soc_config" = "{ // Touchpad I2C bus @@ -53,7 +55,7 @@ chip soc/intel/alderlake register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 # FIXME: DevSlp breaks S0ix - #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + #register "sata_ports_dev_slp[1]" = "1" end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel diff --git a/src/mainboard/system76/rpl/variants/addw3/hda_verb.c b/src/mainboard/system76/rpl/variants/addw3/hda_verb.c index a10716b5c43b..08f3aff23190 100644 --- a/src/mainboard/system76/rpl/variants/addw3/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/addw3/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb index 9b8d4533f192..24c272c746da 100644 --- a/src/mainboard/system76/rpl/variants/addw3/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/addw3/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/rpl/variants/addw4/board.fmd b/src/mainboard/system76/rpl/variants/addw4/board.fmd new file mode 100644 index 000000000000..b2615d1e1717 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 3944K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/addw4/board_info.txt b/src/mainboard/system76/rpl/variants/addw4/board_info.txt new file mode 100644 index 000000000000..01f9c506880d --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/board_info.txt @@ -0,0 +1,2 @@ +Board name: addw4 +Release year: 2024 diff --git a/src/mainboard/system76/rpl/variants/addw4/data.vbt b/src/mainboard/system76/rpl/variants/addw4/data.vbt Binary files differnew file mode 100644 index 000000000000..40fdfb28fe03 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/data.vbt diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio.c b/src/mainboard/system76/rpl/variants/addw4/gpio.c new file mode 100644 index 000000000000..471212b8883f --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/gpio.c @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVVDD_EN_R + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, NONE), + PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE# + PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT# + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3 + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal freq strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS confidentiality strap + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // I2C2_SDA (Pantone) + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // I2C2_SCL (Pantone) + PAD_NC(GPP_C5, NONE), // eSPI disable strap + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // SMD_7411 + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // SMC_7411 + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_NC(GPP_C9, NONE), + PAD_CFG_GPO(GPP_C10, 0, DEEP), // TEST_R (ANX7411) + PAD_CFG_GPO(GPP_C11, 0, DEEP), // PCH_TEST_R_2 (ANX7411) + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_2 + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_2 + // GPP_C20 (UART2_RXD) configured in bootblock + // GPP_C21 (UART2_TXD) configured in bootblock + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP + PAD_NC(GPP_D4, NONE), + PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N + // GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + // GPP_D12 (SSD2_CLKREQ#) configured by FSP + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI# + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3# + PAD_NC(GPP_E13, NONE), + PAD_NC(GPP_E14, NONE), + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // M.2_SSD_SATA_DET_N + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD_SATA_DEVSLP + PAD_NC(GPP_F6, NONE), + _PAD_CFG_STRUCT(GPP_F7, 0x80100100, 0x0000), // 7411_INTP_OUT + PAD_NC(GPP_F8, NONE), + // GPP_F9 (DGPU_PWR_EN) configured in bootblock + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // Recovery strap + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N + _PAD_CFG_STRUCT(GPP_F16, 0x80100100, 0x0000), // INTP_OUT + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP# + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_CFG_GPO(GPP_G0, 0, DEEP), // Board ID 2 + PAD_CFG_GPO(GPP_G1, 0, DEEP), // Board ID 3 + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPI(GPP_G3, NONE, DEEP), // MB detect GN20/GN21 + PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Board ID 1 + PAD_NC(GPP_G5, NONE), + PAD_CFG_GPI(GPP_G6, NONE, DEEP), // MB detect G-SYNC + PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MB detect 230W/180W adapter + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP + PAD_CFG_GPO(GPP_H1, 0, DEEP), // Pantone detect + PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_GPIO_WAKE_N + // GPP_H3 (NC) configured by FSP + // GPP_H4 (SSD1_SATA_CLKREQ#) configured by FSP + // GPP_H5 (WLAN_CLKREQ#) configured by FSP + // GPP_H6 (NC) configured by FSP + // GPP_H7 (LAN_CLKREQ#) configured by FSP + // GPP_H8 (PEG_CLKREQ#) configured by FSP + // GPP_H9 (SSD3_CLKREQ#) configured by FSP + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT strap + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_CFG_GPO(GPP_H18, 0, DEEP), // 1.8V VCCPSPI strap + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // DP_HPD + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // HDMI_HPD + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // USB_OC4# + PAD_CFG_GPI(GPP_I12, NONE, DEEP), // USB_OC5# + PAD_CFG_GPI(GPP_I13, NONE, DEEP), // USB_OC6# + PAD_CFG_GPI(GPP_I14, NONE, DEEP), // USB_OC7# + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_CFG_GPO(GPP_I18, 0, DEEP), // No reboot strap + PAD_NC(GPP_I19, NONE), + PAD_NC(GPP_I20, NONE), + PAD_NC(GPP_I21, NONE), + PAD_CFG_GPO(GPP_I22, 0, DEEP), // Boot BIOS strap + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R / Xtal freq strap + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R / M.2 CNV modes strap + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU + PAD_NC(GPP_J9, NONE), + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + /* ------- GPIO Group GPP_K ------- */ + PAD_NC(GPP_K0, NONE), + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_NC(GPP_K3, NONE), + PAD_NC(GPP_K4, NONE), + PAD_NC(GPP_K5, NONE), + // GPP_K6 not in schematics + // GPP_K7 not in schematics + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_K10 not in schematics + PAD_NC(GPP_K11, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD + PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_R10, NONE), + PAD_NC(GPP_R11, NONE), + PAD_NC(GPP_R12, NONE), + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + // GPP_R16 (DGPU_RST#_PCH) configured in bootblock + PAD_NC(GPP_R17, NONE), + PAD_NC(GPP_R18, NONE), + PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI# + PAD_NC(GPP_R20, NONE), + PAD_NC(GPP_R21, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/addw4/gpio_early.c b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c new file mode 100644 index 000000000000..b6914ad71649 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/addw4/hda_verb.c b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c new file mode 100644 index 000000000000..3850d3411e43 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/hda_verb.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x15580353, /* Subsystem ID */ + 35, /* Number of entries */ + + 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, + + AZALIA_SUBVENDOR(0, 0x15580353), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b, + 0x0205004a, 0x02042010, 0x02050038, 0x02047909, + 0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82, + 0x05350000, 0x0534201a, 0x05350000, 0x0534201a, + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, + 0x05350003, 0x05341ec4, 0x05350004, 0x05340000, + 0x05450000, 0x05442000, 0x0545001d, 0x05440800, + 0x0545001e, 0x05440800, 0x05450003, 0x05441ec4, + 0x05450004, 0x05440000, 0x05350000, 0x0534a01a, + 0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135, + 0x02050040, 0x02048800, 0x05a50001, 0x05a4001f, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, + 0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390, + 0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00, + 0x00170500, 0x00170500, 0x05a50004, 0x05a40113, + 0x02050008, 0x02046a8c, 0x02050076, 0x0204f000, + 0x0205000e, 0x020465c0, 0x02050033, 0x02048580, + 0x02050069, 0x0204fda8, 0x02050068, 0x02040000, + 0x02050003, 0x02040002, 0x02050069, 0x02040000, + 0x02050068, 0x02040001, 0x0205002e, 0x0204290e, + 0x02050010, 0x02040020, 0x02050010, 0x02040020, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/addw4/overridetree.cb b/src/mainboard/system76/rpl/variants/addw4/overridetree.cb new file mode 100644 index 000000000000..c29aea9ecb78 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/overridetree.cb @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + # Support 5600 MT/s memory + register "max_dram_speed_mts" = "5600" + + device domain 0 on + subsystemid 0x1558 0x0353 inherit + + device ref xhci on + register "usb2_ports" = "{ + /* Port reset messaging cannot be used, + * so do not use USB2_PORT_TYPE_C for these */ + [0] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */ + [1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC2 */ + [2] = USB2_PORT_MID(OC_SKIP), /* J_USB2 */ + [3] = USB2_PORT_MID(OC_SKIP), /* J_USB1 (Audio board) */ + [6] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */ + [7] = USB2_PORT_MID(OC_SKIP), /* Camera */ + [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB2 */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB1 (Audio board) */ + }" + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + + device ref pcie5_0 on + # DGPU + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 14, + .clk_req = 14, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + + device ref pcie_rp3 on + # GLAN + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 13, + .clk_req = 13, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + device pci 00.0 on end # Realtek RTL8111H + end + device ref pcie_rp8 on + # WLAN + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 11, + .clk_req = 11, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp13 on + # J_SSD1 + register "pch_pcie_rp[PCH_RP(13)]" = "{ + .clk_src = 10, + .clk_req = 10, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp21 on + # J_SSD2 + register "pch_pcie_rp[PCH_RP(21)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp25 on + # J_SSD3 + register "pch_pcie_rp[PCH_RP(25)]" = "{ + .clk_src = 15, + .clk_req = 15, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + end +end diff --git a/src/mainboard/system76/rpl/variants/addw4/romstage.c b/src/mainboard/system76/rpl/variants/addw4/romstage.c new file mode 100644 index 000000000000..fe9103240cda --- /dev/null +++ b/src/mainboard/system76/rpl/variants/addw4/romstage.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + .ddr_config = { + .dq_pins_interleaved = true, + }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to hybrid graphics + mupd->FspmConfig.PrimaryDisplay = 4; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c b/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c index c1f031cc950f..d5537b4a7e21 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/bonw15/hda_verb.c @@ -14,11 +14,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), AZALIA_PIN_CFG(0, 0x1e, 0x04451150), diff --git a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb index fde40f62454b..a1191a54342d 100644 --- a/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/bonw15/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/rpl/variants/darp9/hda_verb.c b/src/mainboard/system76/rpl/variants/darp9/hda_verb.c index 2c8d619f126d..57961ee2d2e6 100644 --- a/src/mainboard/system76/rpl/variants/darp9/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/darp9/hda_verb.c @@ -13,12 +13,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), 0x02050038, 0x02047901, 0x02050007, 0x02040202, 0x02050008, 0x02046a0e, 0x0205001b, 0x02040a4b, diff --git a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb index c3bc2bddaba9..3dc27864fe01 100644 --- a/src/mainboard/system76/rpl/variants/darp9/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/darp9/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{ .tdp_pl1_override = 20, @@ -14,6 +16,11 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD2_RST# + register "srcclk_pin" = "0" # SSD2_CLKREQ# + device generic 0 on end + end end device ref pcie4_1 on # CPU RP#3 x4, Clock 4 (SSD1) @@ -22,6 +29,11 @@ chip soc/intel/alderlake .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST# + register "srcclk_pin" = "4" # SSD1_CLKREQ# + device generic 0 on end + end end device ref tbt_pcie_rp0 on end device ref tcss_xhci on diff --git a/src/mainboard/system76/rpl/variants/galp7/hda_verb.c b/src/mainboard/system76/rpl/variants/galp7/hda_verb.c index 4f2892570e36..8679812a0c1b 100644 --- a/src/mainboard/system76/rpl/variants/galp7/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/galp7/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/rpl/variants/galp7/overridetree.cb b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb index 0c0aec307135..cc060e44b184 100644 --- a/src/mainboard/system76/rpl/variants/galp7/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/galp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_682_642_482_45W_CORE]" = "{ .tdp_pl1_override = 45, diff --git a/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c b/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c index 82f047d238b7..743cfb72c8c7 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/gaze18/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb index 4c115950d025..636d57cadde5 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake device domain 0 on subsystemid 0x1558 0x5630 inherit diff --git a/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c b/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c index 12fddf42f807..410d44cf5844 100644 --- a/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/lemp12/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb index 34950cc3c62f..c84628b6accc 100644 --- a/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/lemp12/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake register "power_limits_config[RPL_P_282_242_142_15W_CORE]" = "{ .tdp_pl1_override = 15, diff --git a/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c index 15d12f43bba0..368e83e4fe69 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/oryp11/hda_verb.c @@ -14,14 +14,14 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60120), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11030), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), // ALC1318 smart amp 0x05b50000, 0x05b43530, 0x05750002, 0x05741400, diff --git a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb index d337a572a5dc..57bc59468cbd 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake device domain 0 on subsystemid 0x1558 0x66a2 inherit diff --git a/src/mainboard/system76/rpl/variants/oryp12/board.fmd b/src/mainboard/system76/rpl/variants/oryp12/board.fmd new file mode 100644 index 000000000000..b2615d1e1717 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/board.fmd @@ -0,0 +1,12 @@ +FLASH 32M { + SI_DESC 4K + SI_ME 3944K + SI_BIOS@16M 16M { + RW_MRC_CACHE 64K + SMMSTORE(PRESERVE) 256K + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/system76/rpl/variants/oryp12/board_info.txt b/src/mainboard/system76/rpl/variants/oryp12/board_info.txt new file mode 100644 index 000000000000..0d0df61818c0 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp12 +Release year: 2024 diff --git a/src/mainboard/system76/rpl/variants/oryp12/data.vbt b/src/mainboard/system76/rpl/variants/oryp12/data.vbt Binary files differnew file mode 100644 index 000000000000..da4235ee3080 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/data.vbt diff --git a/src/mainboard/system76/rpl/variants/oryp12/gpio.c b/src/mainboard/system76/rpl/variants/oryp12/gpio.c new file mode 100644 index 000000000000..becce0500646 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/gpio.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW_N + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_NC(GPD2, NONE), + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), // SLP_A# (test) + PAD_NC(GPD7, NONE), // GPD_7 (strap) + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5# (test) + PAD_NC(GPD11, NONE), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0 + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // PIRQ#_TPM + PAD_CFG_GPI(GPP_B1, NONE, DEEP), + PAD_CFG_GPI(GPP_B2, NONE, DEEP), //CNVI_WAKE# + PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), // M2_SSD2_RST# + PAD_NC(GPP_B8, NONE), // M2_SSD1_RST# + PAD_NC(GPP_B9, NONE), // M2_SSD1_PWR_EN + PAD_NC(GPP_B10, NONE), // M2_SSD2_PWR_EN + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_CFG_GPO(GPP_B15, 0, DEEP), // PS8461_SW (XXX: NC) + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT# + PAD_CFG_GPO(GPP_B19, 1, DEEP), // PCH_WLAN_EN (XXX: NC) + PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3 + _PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000), // GPP_B21_TBT_WAKE# + PAD_CFG_GPO(GPP_B22, 0, DEEP), // LAN_PLT_RST# + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal frequency bit 1 strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // PCH_PORT80_LED + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // GPPB_I2C2_SDA + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // GPPB_I2C2_SCL + PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C_5_SML0ALERT_N + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // I2C_SDA_AMP + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // I2C_SCL_AMP + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL + // GPP_C20 (UART2_RXD) configured in bootblock + // GPP_C21 (UART2_TXD) configured in bootblock + PAD_CFG_GPO(GPP_C22, 0, DEEP), + PAD_CFG_GPO(GPP_C23, 0, DEEP), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP + PAD_NC(GPP_D4, NONE), // GPP_D4_SML1CLK + PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N + // GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP + PAD_NC(GPP_D7, NONE), // M.2_BT_PCMIN + PAD_NC(GPP_D8, NONE), // M.2_BT_PCMCLK + PAD_NC(GPP_D9, NONE), // GPP_D9_SML0CLK + PAD_NC(GPP_D10, NONE), // GPP_D10_SML0DATA + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), // GPP_D15_SML1DATA + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI# + PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI# + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_NC(GPP_E8, NONE), + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // GPP_E_9_USB_OC0_N + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // GPP_E_10_USB_OC1_N + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // GPP_E_11_USB_OC2_N + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // GPP_E_12_USB_OC3_N + PAD_NC(GPP_E13, NONE), + PAD_NC(GPP_E14, NONE), + PAD_CFG_GPO(GPP_E15, 1, DEEP), // ROM_I2C_EN + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_CFG_GPO(GPP_F2, 1, DEEP), // GPP_F2_TBT_RST# + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI(GPP_F5, NONE, DEEP), // GPIO4_GC6_NVVDD_EN_R + PAD_NC(GPP_F6, NONE), // GPU_EVENT# + PAD_NC(GPP_F7, NONE), + PAD_CFG_GPI(GPP_F8, NONE, PLTRST), // GC6_FB_EN_PCH + // GPP_F9 (DGPU_PWR_EN) configured in bootblock + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // GPP_F10 + PAD_NC(GPP_F11, NONE), // CARD_RTD3_RST# + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_FW_WP# + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPI(GPP_G3, NONE, DEEP), // L: W/Pantone, H: W/O Pantone + PAD_CFG_GPI(GPP_G4, NONE, DEEP), // L: BID_X2, H: BID_X6/X4 + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // GPP_G_5_SLP_DRAM_N + PAD_CFG_GPI(GPP_G6, NONE, DEEP), + PAD_CFG_GPI(GPP_G7, NONE, DEEP), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP + PAD_NC(GPP_H1, NONE), + PAD_CFG_GPI(GPP_H2, NONE, DEEP), // LAN_GPIO_WAKE_N + // GPP_H3 (PEX_SSD2_CLKREQ#) configured by FSP + // GPP_H4 (PEX_SSD1_CLKREQ#) configured by FSP + // GPP_H5 (WLAN_CLKREQ#) configured by FSP + // GPP_H6 (CARD_CLKREQ#) configured by FSP + // GPP_H7 (LAN_CLKREQ#) configured by FSP + // GPP_H8 (PEG_CLKREQ#) configured by FSP + // GPP_H9 (TBT_CLKREQ#) configured by FSP + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_CFG_GPO(GPP_H12, 0, DEEP), // L: MAFS, H: SAFS + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT: L: disabled, H: enabled + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), // M2_WLAN_RST# + PAD_CFG_GPO(GPP_H18, 0, DEEP), // VCCSPI: L: 3.3V, H: 1.8V + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_CFG_GPO(GPP_H21, 0, DEEP), // TBT_MRESET_PCH + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // CPU_DP_B_HPD + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), // HDMI_HPD + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), // CPU_DP_D_HPD + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), // G_DP_A_HPD_L + PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // GPP_I_11_USB_OC4_N + PAD_CFG_GPI(GPP_I12, NONE, DEEP), // GPP_I_12_USB_OC5_N + PAD_CFG_GPI(GPP_I13, NONE, DEEP), // GPP_I_13_USB_OC6_N + PAD_CFG_GPI(GPP_I14, NONE, DEEP), // GPP_I_14_USB_OC7_N + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_CFG_GPO(GPP_I18, 0, DEEP), // No Reboot: L: disable H: enable + PAD_NC(GPP_I19, NONE), + PAD_NC(GPP_I20, NONE), + PAD_NC(GPP_I21, NONE), + PAD_CFG_GPO(GPP_I22, 0, DEEP), // BIOS fetch routing: + // L: SPI (MAF) or eSPI Flash Ch (SAF) + // H: eSPI Peripheral Ch + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE_N + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU + PAD_NC(GPP_J9, NONE), + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + /* ------- GPIO Group GPP_K ------- */ + _PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000), // TBCIO_PLUG_EVENT# + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_CFG_GPO(GPP_K3, 1, PLTRST), // TBT_RTD3_PWR_EN_R + PAD_CFG_TERM_GPO(GPP_K4, 0, UP_20K, DEEP), // TBT_FORCE_PWR_R + PAD_NC(GPP_K5, NONE), + // GPP_K6 not in schematics + // GPP_K7 not in schematics + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_K10 not in schematics + PAD_NC(GPP_K11, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST# + PAD_CFG_GPO(GPP_R5, 0, DEEP), // PCH_MUTE (XXX: SMART_AMP_EN) + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // PCH_EDP_HPD + PAD_NC(GPP_R10, NONE), + PAD_NC(GPP_R11, NONE), + PAD_NC(GPP_R12, NONE), + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + // GPP_R16 (DGPU_RST#_PCH) configured in bootblock + PAD_NC(GPP_R17, NONE), + PAD_NC(GPP_R18, NONE), + PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI# + PAD_NC(GPP_R20, NONE), + PAD_NC(GPP_R21, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/oryp12/gpio_early.c b/src/mainboard/system76/rpl/variants/oryp12/gpio_early.c new file mode 100644 index 000000000000..b6914ad71649 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/rpl/variants/oryp12/hda_verb.c b/src/mainboard/system76/rpl/variants/oryp12/hda_verb.c new file mode 100644 index 000000000000..9bd1e6da4898 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x155866a6, /* Subsystem ID */ + 24, /* Number of entries */ + + 0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb, + + AZALIA_SUBVENDOR(0, 0x155866a6), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60120), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40a7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x05b50000, 0x05b43530, 0x05750002, 0x05741400, + 0x02050058, 0x02048ed1, 0x02050063, 0x0204e430, + 0x02050016, 0x02048020, 0x02050016, 0x02048020, + 0x02050043, 0x02043005, 0x02050058, 0x02048ed1, + 0x02050063, 0x0204e430, 0x05b50000, 0x05b43530, + 0x05750002, 0x05741400, 0x05b5000a, 0x05b45520, + 0x02050042, 0x020486cb, 0x0143b000, 0x01470740, + 0x02050036, 0x02042a6a, 0x02050008, 0x0204800b, + 0x02050007, 0x020403c3, 0x02050007, 0x020403c3, + 0x0205001b, 0x02044002, 0x0205001b, 0x02044002, +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/rpl/variants/oryp12/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp12/overridetree.cb new file mode 100644 index 000000000000..54f42bee32bb --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/overridetree.cb @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + # Support 5600 MT/s memory + register "max_dram_speed_mts" = "5600" + + device domain 0 on + subsystemid 0x1558 0x66a6 inherit + + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // J_AUD1 + [2] = USB2_PORT_MID(OC_SKIP), // J_TYPEC2 + [5] = USB2_PORT_MID(OC_SKIP), // J_USB1 + [7] = USB2_PORT_MID(OC_SKIP), // Camera + [8] = USB2_PORT_MID(OC_SKIP), // J_TYPEC1 (TBT) + [13] = USB2_PORT_MID(OC_SKIP), // Bluetooth + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // J_AUD1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // J_USB1 + [3] = USB3_PORT_DEFAULT(OC_SKIP), // J_TYPEC2 + }" + end + + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on + # Thunderbolt + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c2 on + # Pantone + register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref i2c3 on + # TAS5825M smart amp + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end # (8bit address: 0x9c) + end + end + + device ref pcie5_0 on + # GPU + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_src = 14, + .clk_req = 14, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp3 on + # GLAN + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 13, + .clk_req = 13, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp5 on + # CARD + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 12, + .clk_req = 12, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG, + }" + end + device ref pcie_rp8 on + # WLAN + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 11, + .clk_req = 11, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp9 on + # SSD1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 10, + .clk_req = 10, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp13 on + # SSD2 + register "pch_pcie_rp[PCH_RP(13)]" = "{ + .clk_src = 9, + .clk_req = 9, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp25 on + # TBT + # XXX: AER causes UnsupReq warnings + register "pch_pcie_rp[PCH_RP(25)]" = "{ + .clk_src = 15, + .clk_req = 15, + .flags = PCIE_RP_LTR | PCIE_RP_HOTPLUG, + }" + end + end +end diff --git a/src/mainboard/system76/rpl/variants/oryp12/romstage.c b/src/mainboard/system76/rpl/variants/oryp12/romstage.c new file mode 100644 index 000000000000..fe9103240cda --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/romstage.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .ect = true, + .LpDdrDqDqsReTraining = 1, + .ddr_config = { + .dq_pins_interleaved = true, + }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + // Set primary display to hybrid graphics + mupd->FspmConfig.PrimaryDisplay = 4; + + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/system76/rpl/variants/oryp12/tas5825m.c b/src/mainboard/system76/rpl/variants/oryp12/tas5825m.c new file mode 100644 index 000000000000..45dfb38b3884 --- /dev/null +++ b/src/mainboard/system76/rpl/variants/oryp12/tas5825m.c @@ -0,0 +1,1053 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <delay.h> +#include <drivers/i2c/tas5825m/tas5825m.h> + +int tas5825m_setup(struct device *dev, int id) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x7F, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x7F, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x28, 0x7A, 0x27, + 0x00, 0x28, 0x7A, 0x27, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x01, 0x24, 0x02, 0xCB, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x09, 0xC6, 0x4C, 0xCF, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x05, 0xA9, 0xDF, 0x7B, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE0, 0x03, 0x27, 0xF0, 0x3F, 0xF9, 0xB1, + 0x07, 0xE0, 0x03, 0x27, 0x0F, 0xBF, 0xC1, 0x46, + 0xF8, 0x3F, 0xB4, 0xA8, 0x07, 0xE8, 0x73, 0x5B, + 0xF0, 0x2F, 0x19, 0x4B, 0x07, 0xE8, 0x73, 0x5B, + 0x0F, 0xD0, 0xA1, 0x62, 0xF8, 0x2E, 0xD3, 0xF8, + 0x07, 0xE8, 0x65, 0x1C, 0xF0, 0x4C, 0x95, 0x0B, + 0x07, 0xCC, 0x6D, 0xBC, 0x0F, 0xB3, 0x6A, 0xF5, + 0xF8, 0x4B, 0x2D, 0x28, 0x08, 0x1D, 0xB8, 0xB2, + 0xF0, 0x12, 0x40, 0x2B, 0x07, 0xD1, 0x74, 0x3E, + 0x0F, 0xEE, 0x30, 0x8F, 0xF8, 0x11, 0x43, 0xC9, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE0, 0x03, 0x27, + 0xF0, 0x3F, 0xF9, 0xB1, 0x07, 0xE0, 0x03, 0x27, + 0x0F, 0xBF, 0xC1, 0x46, 0xF8, 0x3F, 0xB4, 0xA8, + 0x07, 0xE8, 0x73, 0x5B, 0xF0, 0x2F, 0x19, 0x4B, + 0x07, 0xE8, 0x73, 0x5B, 0x0F, 0xD0, 0xA1, 0x62, + 0xF8, 0x2E, 0xD3, 0xF8, 0x07, 0xE8, 0x65, 0x1C, + 0xF0, 0x4C, 0x95, 0x0B, 0x07, 0xCC, 0x6D, 0xBC, + 0x0F, 0xB3, 0x6A, 0xF5, 0xF8, 0x4B, 0x2D, 0x28, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x1D, 0xB8, 0xB2, 0xF0, 0x12, 0x40, 0x2B, + 0x07, 0xD1, 0x74, 0x3E, 0x0F, 0xEE, 0x30, 0x8F, + 0xF8, 0x11, 0x43, 0xC9, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x88, 0xF4, 0xB0, 0xFF, 0x02, 0x86, 0x19, + 0x00, 0x75, 0xF1, 0x4C, 0x0F, 0xE2, 0x49, 0x11, + 0xF8, 0x1C, 0x4A, 0xDB, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x30); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/system76/rpl/variants/serw13/hda_verb.c b/src/mainboard/system76/rpl/variants/serw13/hda_verb.c index 573e2288b1fc..191eadf1b69e 100644 --- a/src/mainboard/system76/rpl/variants/serw13/hda_verb.c +++ b/src/mainboard/system76/rpl/variants/serw13/hda_verb.c @@ -14,11 +14,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), AZALIA_PIN_CFG(0, 0x1e, 0x04451150), diff --git a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb index b261d5923c8f..cc89764c7fc6 100644 --- a/src/mainboard/system76/rpl/variants/serw13/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/serw13/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/alderlake # Support 5600 MT/s memory register "max_dram_speed_mts" = "5600" diff --git a/src/mainboard/system76/tgl-h/cmos.layout b/src/mainboard/system76/tgl-h/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/tgl-h/cmos.layout +++ b/src/mainboard/system76/tgl-h/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb index 353a96d329d7..11b85ced1570 100644 --- a/src/mainboard/system76/tgl-h/devicetree.cb +++ b/src/mainboard/system76/tgl-h/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt b/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt Binary files differindex 297522723cbb..ff4bbb6b844a 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c index 35c27a150f70..e5804fa5117b 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x02a11040), AZALIA_PIN_CFG(0, 0x1d, 0x41700001), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb index ad90eabfee01..6ac474d0d198 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake device domain 0 on subsystemid 0x1558 0x5015 inherit diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt b/src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt Binary files differindex 2531c7aed7a1..5ff5bd561ff9 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c index 491e32b2b170..3399a2d02c1a 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c @@ -12,12 +12,12 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1a, 0x02a11040), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41789c6d), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x21, 0x02211020), }; diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb index bfbc5c5090e1..b4b62faa62d8 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake device domain 0 on subsystemid 0x1558 0x50e1 inherit diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/data.vbt b/src/mainboard/system76/tgl-h/variants/oryp8/data.vbt Binary files differindex 5641c17f76d8..4165da8df51e 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/data.vbt +++ b/src/mainboard/system76/tgl-h/variants/oryp8/data.vbt diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c b/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c index 2a32f017c331..2cdfe5d19925 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c +++ b/src/mainboard/system76/tgl-h/variants/oryp8/hda_verb.c @@ -12,11 +12,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x12, 0x90a60130), AZALIA_PIN_CFG(0, 0x14, 0x0421101f), AZALIA_PIN_CFG(0, 0x15, 0x40000000), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x04a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1b, 0x90170110), AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), AZALIA_PIN_CFG(0, 0x1e, 0x04451150), diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb index a09cf30cad2b..0967154c6b53 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb +++ b/src/mainboard/system76/tgl-h/variants/oryp8/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/cmos.layout b/src/mainboard/system76/tgl-u/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/tgl-u/cmos.layout +++ b/src/mainboard/system76/tgl-u/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/tgl-u/devicetree.cb b/src/mainboard/system76/tgl-u/devicetree.cb index f056da7715e4..ae80a324e257 100644 --- a/src/mainboard/system76/tgl-u/devicetree.cb +++ b/src/mainboard/system76/tgl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake register "common_soc_config" = "{ // Touchpad I2C bus diff --git a/src/mainboard/system76/tgl-u/variants/darp7/data.vbt b/src/mainboard/system76/tgl-u/variants/darp7/data.vbt Binary files differindex e3b164fd1d4e..bb4090132296 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/data.vbt +++ b/src/mainboard/system76/tgl-u/variants/darp7/data.vbt diff --git a/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c b/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c index 53a47bdb471b..bcb14c6b629f 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/darp7/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb index a35dc52ab975..b263c5ab7318 100644 --- a/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/variants/galp5/data.vbt b/src/mainboard/system76/tgl-u/variants/galp5/data.vbt Binary files differindex e3b164fd1d4e..bb4090132296 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/data.vbt +++ b/src/mainboard/system76/tgl-u/variants/galp5/data.vbt diff --git a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c index c0afb196dca3..bf192c0b5783 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/galp5/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41748245), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb index 075a2e44ab16..7cfc62bb3dc3 100644 --- a/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/galp5/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/data.vbt b/src/mainboard/system76/tgl-u/variants/lemp10/data.vbt Binary files differindex 7c29ceda6249..2b1005bbe372 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/data.vbt +++ b/src/mainboard/system76/tgl-u/variants/lemp10/data.vbt diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c index 43a0ee5aed63..52fbda572a86 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c +++ b/src/mainboard/system76/tgl-u/variants/lemp10/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), - AZALIA_PIN_CFG(0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41748245), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), }; const u32 pc_beep_verbs[] = {}; diff --git a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb index ce4507900ee1..a4e30523676d 100644 --- a/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb +++ b/src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/tigerlake # Power limits register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ diff --git a/src/mainboard/system76/whl-u/cmos.layout b/src/mainboard/system76/whl-u/cmos.layout index 0513315c33a4..b3df3808ccb7 100644 --- a/src/mainboard/system76/whl-u/cmos.layout +++ b/src/mainboard/system76/whl-u/cmos.layout @@ -14,7 +14,10 @@ entries 412 4 e 6 debug_level 416 1 e 2 me_state 417 3 h 0 me_state_counter -904 80 h 0 ramtop + +# CMOS_VSTART_ramtop +800 80 r 0 ramtop + 984 16 h 0 check_sum enumerations @@ -37,4 +40,4 @@ enumerations checksums -checksum 408 983 984 +checksum 408 799 984 diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index 0899f624ec19..6607f45ae93b 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake # Lock Down register "common_soc_config" = "{ diff --git a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c index 3372f9c490b7..89cbd72bc129 100644 --- a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c +++ b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c @@ -13,11 +13,11 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x02a11050), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x41738205), AZALIA_PIN_CFG(0, 0x1e, 0x02451130), diff --git a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb index b9c9de7c2b4e..c72111ae12dc 100644 --- a/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb +++ b/src/mainboard/system76/whl-u/variants/darp5/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1325 inherit diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c index 03f2f8c2b363..451f938e72ec 100644 --- a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c +++ b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c @@ -13,13 +13,13 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x13, 0x40000000), AZALIA_PIN_CFG(0, 0x14, 0x90170110), AZALIA_PIN_CFG(0, 0x15, 0x02211020), - AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x18, 0x02a11040), - AZALIA_PIN_CFG(0, 0x19, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), - AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1d, 0x40738205), - AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), /* Intel GPU HDMI */ 0x8086280b, /* Vendor ID */ diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb b/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb index 022be95787b9..4556940d3e47 100644 --- a/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb +++ b/src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb @@ -1,3 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1323 inherit |