diff options
Diffstat (limited to 'src/mainboard')
60 files changed, 96 insertions, 158 deletions
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c index 1381dfa35263..4b9f5813717e 100644 --- a/src/mainboard/advansus/a785e-i/mainboard.c +++ b/src/mainboard/advansus/a785e-i/mainboard.c @@ -21,7 +21,7 @@ #include <cpu/amd/mtrr.h> #include <southbridge/amd/common/amd_defs.h> #include <device/pci_def.h> -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/rs780/rs780.h> /* GPIO6. */ static void enable_int_gfx(void) diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index d9b9570d062e..58d36ae62928 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -24,8 +24,8 @@ #include "hudson.h" #include <stdlib.h> #include <string.h> -#include "northbridge/amd/pi/dimmSpd.h" -#include "northbridge/amd/pi/agesawrapper.h" +#include <northbridge/amd/pi/dimmSpd.h> +#include <northbridge/amd/pi/agesawrapper.h> #include <boardid.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); diff --git a/src/mainboard/amd/bettong/mptable.c b/src/mainboard/amd/bettong/mptable.c index c50c254a6a08..5a06fe7020e1 100644 --- a/src/mainboard/amd/bettong/mptable.c +++ b/src/mainboard/amd/bettong/mptable.c @@ -22,7 +22,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/pi/hudson/hudson.h" +#include <southbridge/amd/pi/hudson/hudson.h> #include <southbridge/amd/common/amd_pci_util.h> static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c index 3fa240573949..572405d56d00 100644 --- a/src/mainboard/amd/bimini_fam10/mainboard.c +++ b/src/mainboard/amd/bimini_fam10/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/sb800/sb800.h> -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/rs780/rs780.h> /* GPIO6. */ static void enable_int_gfx(void) diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c index a4a26e026c25..9c357f9750df 100644 --- a/src/mainboard/amd/mahogany_fam10/mainboard.c +++ b/src/mainboard/amd/mahogany_fam10/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> /* * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 89881f770ce7..443f55155b5e 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> @@ -22,7 +21,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index bbbeb62eb16c..e916a24f9ddd 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> @@ -22,7 +21,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[0x54] = { 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 355cff6e0954..06a49d4018d0 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> @@ -22,7 +21,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[] = { 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c index 5e112158c277..d4baf8534c27 100644 --- a/src/mainboard/amd/tilapia_fam10/mainboard.c +++ b/src/mainboard/amd/tilapia_fam10/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/sb700/sb700.h> -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index b7c2565e81b6..727dad387812 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -17,8 +17,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/nvs.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include <pc80/mc146818rtc.h> #include <delay.h> diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index b9cfa2023af3..d189ae287c74 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -14,20 +14,13 @@ #include <stdint.h> #include <string.h> #include <lib.h> -#include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <arch/acpi.h> -#include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include <southbridge/intel/common/gpio.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <cbfs.h> void pch_enable_lpc(void) diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c index 645fd0800ce0..050d6c50b38f 100644 --- a/src/mainboard/asrock/b75pro3-m/romstage.c +++ b/src/mainboard/asrock/b75pro3-m/romstage.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "northbridge/intel/sandybridge/raminit_native.h" +#include <northbridge/intel/sandybridge/raminit_native.h> #include <superio/nuvoton/nct6776/nct6776.h> #include <superio/nuvoton/common/nuvoton.h> diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index cf987cacd73a..04bd0541533c 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> @@ -22,7 +21,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[0x54] = { diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index cf45d947746e..a66900b68e3d 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -21,7 +21,7 @@ #include <device/pci.h> #include <stdint.h> #include <string.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[] = { diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c index 87acc5674c6e..8a017a0b4995 100644 --- a/src/mainboard/asus/m4a78-em/mainboard.c +++ b/src/mainboard/asus/m4a78-em/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> void set_pcie_dereset(void) { diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 5acce5196978..23ead56fce84 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c index 75f231e74b18..2eef74ffca5b 100644 --- a/src/mainboard/asus/m5a88-v/mainboard.c +++ b/src/mainboard/asus/m5a88-v/mainboard.c @@ -17,11 +17,9 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <southbridge/amd/common/amd_defs.h> #include <device/pci_def.h> -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/rs780/rs780.h> /* GPIO6. */ static void enable_int_gfx(void) diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 32459a5e8f5b..304a0f4e7d66 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include "southbridge/intel/i82371eb/i82371eb.h" +#include <southbridge/intel/i82371eb/i82371eb.h> #define SUPERIO_PNP_BASE 0x3F0 #define SUPERIO_SHOW_UARTA diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 5ef6bdba507d..8ddbf28418f7 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "southbridge/intel/i82371eb/i82371eb.h" +#include <southbridge/intel/i82371eb/i82371eb.h> #define SUPERIO_PNP_BASE 0x3F0 #define SUPERIO_SHOW_UARTA diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c index ca4cde65ddcd..3aa5829c9cac 100644 --- a/src/mainboard/asus/p5gc-mx/acpi_tables.c +++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c @@ -15,7 +15,7 @@ #include <types.h> -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 79564a288fe0..67536336b5e7 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -17,11 +17,9 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <southbridge/amd/common/amd_defs.h> #include <device/pci_def.h> -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/rs780/rs780.h> /* GPIO6. */ static void enable_int_gfx(void) diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 993d078999e7..e2ce482cefef 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -45,7 +45,7 @@ #include "spd.h" #include <reset.h> #include <southbridge/amd/rs780/rs780.h> -#include "southbridge/amd/sb800/early_setup.c" +#include <southbridge/amd/sb800/early_setup.c> #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index 89881f770ce7..443f55155b5e 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> @@ -22,7 +21,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 58a78d0f90c4..7e59d95cc98b 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -16,7 +16,7 @@ #include <stdint.h> #include <lib.h> #include <arch/io.h> -#include "northbridge/intel/sandybridge/raminit_native.h" +#include <northbridge/intel/sandybridge/raminit_native.h> #include <superio/smsc/sio1007/chip.h> #define SIO_PORT 0x164e diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 995fa690564c..83d25d75c3cd 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -15,7 +15,6 @@ #include <types.h> #include <string.h> -#include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> @@ -26,7 +25,7 @@ #include "../qemu-i440fx/fw_cfg.h" #include "../qemu-i440fx/acpi.h" -#include "southbridge/intel/i82801ix/nvs.h" +#include <southbridge/intel/i82801ix/nvs.h> void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index f84060540eed..9458b8fd6f16 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -25,7 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> #include "mainboard.h" void acpi_create_gnvs(global_nvs_t *gnvs) diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 2d1a0cd8f5e3..5a82044661a8 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -17,8 +17,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/i82801gx.h" -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/i82801gx/nvs.h> #include <southbridge/intel/common/gpio.h> #include <ec/acpi/ec.h> #include "ec_oem.c" diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 8fbc591c86c9..4c9799a510a7 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> void set_pcie_dereset(void) { diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 8f1dd0a397f4..de90fda029ec 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index bfd083497e6a..6b0e22949254 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -18,12 +18,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> /* * ma78gm-us2h uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index cf987cacd73a..04bd0541533c 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> @@ -22,7 +21,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[0x54] = { diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c index 98d5ef477009..2197f2d6fa97 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c +++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c @@ -23,9 +23,9 @@ #include <device/pnp_def.h> #include <superio/nuvoton/npcd378/npcd378.h> #include <superio/nuvoton/common/nuvoton.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c index b0ffef71f2c9..ad1fdd57616b 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c +++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c @@ -17,12 +17,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> /* TODO - Need to find GPIO for PCIE slot. * Kino uses GPIO ? as PCIe slot reset, GPIO? as GFX slot reset. We need to diff --git a/src/mainboard/intel/cougar_canyon2/acpi_tables.c b/src/mainboard/intel/cougar_canyon2/acpi_tables.c index 3de6d3ed27ba..406184f384ac 100644 --- a/src/mainboard/intel/cougar_canyon2/acpi_tables.c +++ b/src/mainboard/intel/cougar_canyon2/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> #include <cbmem.h> -#include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> @@ -24,8 +23,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <southbridge/intel/fsp_bd82x6x/nvs.h> -#include "southbridge/intel/fsp_bd82x6x/nvs.h" #include "thermal.h" static global_nvs_t *gnvs_; diff --git a/src/mainboard/intel/cougar_canyon2/gpio.h b/src/mainboard/intel/cougar_canyon2/gpio.h index c839a12c3d73..b4e3915e7059 100644 --- a/src/mainboard/intel/cougar_canyon2/gpio.h +++ b/src/mainboard/intel/cougar_canyon2/gpio.h @@ -17,7 +17,7 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H -#include "southbridge/intel/fsp_bd82x6x/gpio.h" +#include <southbridge/intel/fsp_bd82x6x/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio0 = GPIO_MODE_GPIO, /* SINAI */ diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index f33415741fb0..c4be4d50fda7 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -22,7 +22,7 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/raminit_native.h" +#include <northbridge/intel/sandybridge/raminit_native.h> #include "superio.h" #include "thermal.h" diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c index d80fb4c34315..666bba63e3c2 100644 --- a/src/mainboard/intel/dg41wv/acpi_tables.c +++ b/src/mainboard/intel/dg41wv/acpi_tables.c @@ -16,8 +16,7 @@ #include <string.h> #include <stdint.h> - -#include "southbridge/intel/i82801gx/nvs.h" +#include <southbridge/intel/i82801gx/nvs.h> void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 3ef993a3d7da..92ded3c6daf4 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> #include <cbmem.h> -#include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> @@ -25,8 +24,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> -#include "southbridge/intel/bd82x6x/nvs.h" #include "thermal.h" static global_nvs_t *gnvs_; diff --git a/src/mainboard/intel/stargo2/gpio.h b/src/mainboard/intel/stargo2/gpio.h index 25ecfeb151d1..675580b10a28 100644 --- a/src/mainboard/intel/stargo2/gpio.h +++ b/src/mainboard/intel/stargo2/gpio.h @@ -17,7 +17,7 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H -#include "southbridge/intel/fsp_i89xx/gpio.h" +#include <southbridge/intel/fsp_i89xx/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c index 9585832ebe3d..066bd2edff74 100644 --- a/src/mainboard/jetway/pa78vm5/mainboard.c +++ b/src/mainboard/jetway/pa78vm5/mainboard.c @@ -18,12 +18,10 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/rs780/rs780.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/rs780/rs780.h> /* * the board uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index b83eeaec73e7..7e002d4715cf 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -17,20 +17,15 @@ #include <string.h> #include <cbfs.h> #include <lib.h> -#include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <arch/acpi.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> #include "ec.h" #define SPD_LEN 256 diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c index feced93a3f7b..2893d398f3ca 100644 --- a/src/mainboard/lenovo/t400/acpi_tables.c +++ b/src/mainboard/lenovo/t400/acpi_tables.c @@ -15,7 +15,6 @@ */ #include <string.h> -#include <console/console.h> #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -24,8 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> - -#include "southbridge/intel/i82801ix/nvs.h" +#include <southbridge/intel/i82801ix/nvs.h> void acpi_create_gnvs(global_nvs_t *gnvs) { diff --git a/src/mainboard/lenovo/t400/dock.c b/src/mainboard/lenovo/t400/dock.c index 74711e1227cc..0c6db0b5a142 100644 --- a/src/mainboard/lenovo/t400/dock.c +++ b/src/mainboard/lenovo/t400/dock.c @@ -25,7 +25,7 @@ #include "dock.h" #include <superio/nsc/pc87382/pc87382.h> -#include "southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #include "ec/lenovo/h8/h8.h" #include <ec/acpi/ec.h> diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 0e24b95c24df..05dd65ef3ee1 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <arch/io.h> #include <delay.h> @@ -22,7 +21,7 @@ #include <superio/nsc/pc87384/pc87384.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> #define DLPC_CONTROL 0x164c diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index efb0ac43e968..7707d624c8cd 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -17,8 +17,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/nvs.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include <ec/acpi/ec.h> #include "dock.h" #include "smi.h" diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c index 43a0fc8c838b..2893d398f3ca 100644 --- a/src/mainboard/lenovo/x200/acpi_tables.c +++ b/src/mainboard/lenovo/x200/acpi_tables.c @@ -15,7 +15,6 @@ */ #include <string.h> -#include <console/console.h> #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -24,8 +23,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <southbridge/intel/i82801ix/nvs.h> -#include "southbridge/intel/i82801ix/nvs.h" void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/x200/dock.c index 836ff35c0768..5bf2cd3ee69b 100644 --- a/src/mainboard/lenovo/x200/dock.c +++ b/src/mainboard/lenovo/x200/dock.c @@ -22,7 +22,7 @@ #include <device/pci.h> #include <delay.h> #include "dock.h" -#include "southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #include "ec/lenovo/h8/h8.h" #include <ec/acpi/ec.h> diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index 1941ac60f85d..a11c7202bd24 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -22,7 +22,7 @@ #include <device/pci.h> #include <delay.h> #include "dock.h" -#include "southbridge/intel/ibexpeak/pch.h" +#include <southbridge/intel/ibexpeak/pch.h> #include "ec/lenovo/h8/h8.h" #include <ec/acpi/ec.h> diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index f00ae0dcdc5b..93cc2b73dc2a 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -17,9 +17,9 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/ibexpeak/nvs.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/nvs.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> #include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index c2bed9a087da..5b49498a849a 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -20,7 +20,7 @@ #include <delay.h> #include <arch/io.h> #include "dock.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nsc/pc87392/pc87392.h> static void dlpc_write_register(int reg, int value) diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c index b9f0a577a02b..c66474dcc85b 100644 --- a/src/mainboard/lenovo/x60/smihandler.c +++ b/src/mainboard/lenovo/x60/smihandler.c @@ -17,8 +17,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/nvs.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include <ec/acpi/ec.h> #include <pc80/mc146818rtc.h> #include <ec/lenovo/h8/h8.h> diff --git a/src/mainboard/lenovo/z61t/dock.c b/src/mainboard/lenovo/z61t/dock.c index 0e24b95c24df..05dd65ef3ee1 100644 --- a/src/mainboard/lenovo/z61t/dock.c +++ b/src/mainboard/lenovo/z61t/dock.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <device/device.h> #include <arch/io.h> #include <delay.h> @@ -22,7 +21,7 @@ #include <superio/nsc/pc87384/pc87384.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> #define DLPC_CONTROL 0x164c diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c index ef5cfc64a2d5..d98a80957b52 100644 --- a/src/mainboard/lenovo/z61t/smihandler.c +++ b/src/mainboard/lenovo/z61t/smihandler.c @@ -17,8 +17,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/i82801gx/nvs.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/nvs.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include <ec/acpi/ec.h> #include "dock.h" #include "smi.h" diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index cf45d947746e..a66900b68e3d 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -21,7 +21,7 @@ #include <device/pci.h> #include <stdint.h> #include <string.h> -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <southbridge/amd/agesa/hudson/hudson.h> u8 picr_data[] = { diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index eeb55dfdaa61..e94b61b310a9 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -17,9 +17,9 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include "southbridge/intel/ibexpeak/nvs.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/nvs.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> #include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/pcengines/alix2d/irq_tables.c b/src/mainboard/pcengines/alix2d/irq_tables.c index b90903f46fe6..5b3ae208b512 100644 --- a/src/mainboard/pcengines/alix2d/irq_tables.c +++ b/src/mainboard/pcengines/alix2d/irq_tables.c @@ -14,9 +14,8 @@ */ #include <arch/pirq_routing.h> -#include <console/console.h> #include <arch/io.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> /* Platform IRQs */ #define PIRQA 11 diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c index 1540d735dfc0..b67378455937 100644 --- a/src/mainboard/roda/rk9/acpi_tables.c +++ b/src/mainboard/roda/rk9/acpi_tables.c @@ -15,7 +15,6 @@ */ #include <string.h> -#include <console/console.h> #include <arch/io.h> #include <arch/ioapic.h> #include <arch/acpi.h> @@ -24,8 +23,8 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <southbridge/intel/i82801ix/nvs.h> -#include "southbridge/intel/i82801ix/nvs.h" void acpi_create_gnvs(global_nvs_t *gnvs) { memset((void *)gnvs, 0, sizeof(*gnvs)); diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 65922f3d9259..06fa0fd4f195 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> #include <cbmem.h> -#include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> @@ -28,8 +27,8 @@ #if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif +#include <southbridge/intel/bd82x6x/nvs.h> -#include "southbridge/intel/bd82x6x/nvs.h" #include "thermal.h" static global_nvs_t *gnvs_; diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index c5ecbea4bb78..a518d188923f 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -16,7 +16,6 @@ #include <types.h> #include <string.h> #include <cbmem.h> -#include <console/console.h> #include <arch/acpi.h> #include <arch/ioapic.h> #include <arch/acpigen.h> @@ -25,8 +24,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <southbridge/intel/bd82x6x/nvs.h> -#include "southbridge/intel/bd82x6x/nvs.h" #include "thermal.h" static global_nvs_t *gnvs_; diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index a20a1f758b97..da825a9dc174 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -17,21 +17,14 @@ #include <stdint.h> #include <string.h> #include <lib.h> -#include <timestamp.h> #include <arch/byteorder.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <arch/acpi.h> -#include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include <southbridge/intel/common/gpio.h> -#include <arch/cpu.h> -#include <cpu/x86/msr.h> -#include <delay.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + void pch_enable_lpc(void) { |