6 files changed, 8 insertions, 53 deletions
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index b4c2ea89b1ef..9561dfa93f74 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -75,6 +75,9 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
 
 			device pci 19.0 on end # LAN
 			device pci 1a.0 on # UHCI
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 1b763188e8ca..e8215654e1f4 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -14,16 +14,12 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
 #include <console/console.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <southbridge/intel/common/gpio.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include "dock.h"
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-
 static void hybrid_graphics_init(sysinfo_t *sysinfo)
 {
 	bool peg, igd;
@@ -36,20 +32,6 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
 
 static int dock_err;
 
-void mb_setup_lpc(void)
-{
-	/* Set up SuperIO LPC forwards */
-
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
-	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
-}
-
 void mb_setup_superio(void)
 {
 	/* Minimal setup to detect dock */
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb
index 2ed4308cfab6..4efcc255ec1c 100644
--- a/src/mainboard/lenovo/x200/devicetree.cb
+++ b/src/mainboard/lenovo/x200/devicetree.cb
@@ -79,6 +79,9 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
 			register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen3_dec" = "0x001c1681"
 
 			device pci 19.0 on end # LAN
 			device pci 1a.0 on # UHCI
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index 4382bc084d3e..41be94f35747 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -14,25 +14,9 @@
  * GNU General Public License for more details.
  */
 
-#include <device/pci_ops.h>
 #include <southbridge/intel/common/gpio.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
-
-void mb_setup_lpc(void)
-{
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
-	pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
-	pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
-}
-
 void get_mb_spd_addrmap(u8 *spd_addrmap)
 {
 	spd_addrmap[0] = 0x50;
diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb
index 43001712076d..ddb2ad72a9d3 100644
--- a/src/mainboard/roda/rk9/devicetree.cb
+++ b/src/mainboard/roda/rk9/devicetree.cb
@@ -67,6 +67,8 @@ chip northbridge/intel/gm45
 			# Maybe we should set less for Mini PCIe.
 			register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }"
 
+			register "gen1_dec" = "0x000c0601"
+
 			device pci 19.0 off end # LAN
 			device pci 1a.0 on # UHCI
 				ioapic_irq 2 INTA 0x10
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 497828b58a43..b37b5c5f635e 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -16,27 +16,11 @@
 
 #include <arch/io.h>
 #include <device/pnp_ops.h>
-#include <device/pci_ops.h>
-#include <southbridge/intel/common/gpio.h>
-#include <southbridge/intel/i82801ix/i82801ix.h>
 #include <northbridge/intel/gm45/gm45.h>
 #include <superio/smsc/lpc47n227/lpc47n227.h>
 
-#define LPC_DEV PCI_DEV(0, 0x1f, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
 
-void mb_setup_lpc(void)
-{
-	/* Set up SuperIO LPC forwards */
-
-	/* Configure serial IRQs.*/
-	pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
-	/* Map COMa on 0x3f8, COMb on 0x2f8. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
-	/* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */
-	pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
-}
-
 void mb_setup_superio(void)
 {
 	/* Original settings:
@@ -71,9 +55,6 @@ void mb_setup_superio(void)
 	/* Exit configuration state. */
 	pnp_exit_conf_state(sio);
 
-	/* Enable decoding of 0x600-0x60f through lpc. */
-	pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
-
 	/* Set GPIO output values: */
 	outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
 	outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */