diff options
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3')
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 7 | ||||
-rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 4 |
3 files changed, 9 insertions, 7 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 34b13ea306ca..6b312945863f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -16,6 +16,7 @@ #include <inttypes.h> #include <console/console.h> +#include <cpu/x86/cr.h> #include <string.h> #include <arch/cpu.h> #include <cpu/amd/msr.h> @@ -405,7 +406,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat, u32 dev; u32 addr; u8 valid; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u32 index_reg; uint32_t TestAddr; @@ -1617,7 +1618,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, u8 _Wrap32Dis = 0, _SSE2 = 0; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint8_t dct; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index a6faf90e0c8b..032152c39d26 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -22,6 +22,7 @@ #include <arch/cpu.h> #include <inttypes.h> #include <console/console.h> +#include <cpu/x86/cr.h> #include <string.h> #include <cpu/x86/msr.h> #include <cpu/amd/msr.h> @@ -612,7 +613,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; msr_t msr; - u32 cr4; + CRx_TYPE cr4; uint32_t dword; uint8_t dimm; @@ -1186,7 +1187,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end, ch; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; @@ -1583,7 +1584,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, u32 index_reg; u32 ch_start, ch_end; u32 msr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; uint32_t dword; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c index e7b7883f131c..ec9b8e432748 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c @@ -21,7 +21,7 @@ #include <inttypes.h> #include <console/console.h> #include <cpu/amd/msr.h> - +#include <cpu/x86/cr.h> #include "mct_d.h" #include "mct_d_gcc.h" @@ -119,7 +119,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat, u32 PatternBuffer[60]; /* FIXME: why not 48 + 4 */ u32 Margin; u32 addr; - u32 cr4; + CRx_TYPE cr4; u32 lo, hi; u8 valid; |