11 files changed, 11 insertions, 11 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index c6a20fab9d27..009db8021581 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -21,7 +21,7 @@
 #include <program_loading.h>
 #include "e7505.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	pci_devfn_t mch = PCI_DEV(0, 0, 0);
 	uintptr_t tolm;
diff --git a/src/northbridge/intel/fsp_rangeley/memmap.c b/src/northbridge/intel/fsp_rangeley/memmap.c
index da9ed71a67f3..275ddd3ac1fd 100644
--- a/src/northbridge/intel/fsp_rangeley/memmap.c
+++ b/src/northbridge/intel/fsp_rangeley/memmap.c
@@ -36,7 +36,7 @@ static uintptr_t smm_region_start(void)
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) (smm_region_start() - FSP_RESERVE_MEMORY_SIZE);
 }
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 7479a7834acb..d34820eb3dfc 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -117,7 +117,7 @@ static size_t northbridge_get_tseg_size(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c
index 007a67d4b392..74d9292c14a0 100644
--- a/src/northbridge/intel/haswell/memmap.c
+++ b/src/northbridge/intel/haswell/memmap.c
@@ -34,7 +34,7 @@ static uintptr_t smm_region_start(void)
 	return tom & ~((1 << 20) - 1);
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *)smm_region_start();
 }
diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c
index 75a6c7e243bc..d260af6f32e9 100644
--- a/src/northbridge/intel/i440bx/memmap.c
+++ b/src/northbridge/intel/i440bx/memmap.c
@@ -23,7 +23,7 @@
 #include <program_loading.h>
 #include "i440bx.h"
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	/* Base of TSEG is top of usable DRAM */
 	/*
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c
index 8207d06a5579..000ac7e682cf 100644
--- a/src/northbridge/intel/i945/memmap.c
+++ b/src/northbridge/intel/i945/memmap.c
@@ -71,7 +71,7 @@ static size_t northbridge_get_tseg_size(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c
index 1c17b0d9b589..5de4b80acf1f 100644
--- a/src/northbridge/intel/nehalem/memmap.c
+++ b/src/northbridge/intel/nehalem/memmap.c
@@ -42,7 +42,7 @@ static size_t northbridge_get_tseg_size(void)
 	return CONFIG_SMM_TSEG_SIZE;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }
diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index b4fef6bc76ad..0aa70cdb3470 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -132,7 +132,7 @@ static uintptr_t northbridge_get_tseg_base(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 67de34459bf2..99888fa2ae6d 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -31,7 +31,7 @@ static uintptr_t smm_region_start(void)
 	return tom;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	return (void *) smm_region_start();
 }
diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c
index 41e491200bdb..1924ddf678a3 100644
--- a/src/northbridge/intel/x4x/memmap.c
+++ b/src/northbridge/intel/x4x/memmap.c
@@ -128,7 +128,7 @@ static uintptr_t northbridge_get_tseg_base(void)
  * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t top_of_ram = ALIGN_DOWN(northbridge_get_tseg_base(), 4*MiB);
 	return (void *) top_of_ram;
diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c
index d11dc65fd60e..3121d7406ec5 100644
--- a/src/northbridge/via/vx900/memmap.c
+++ b/src/northbridge/via/vx900/memmap.c
@@ -120,7 +120,7 @@ u32 vx900_get_tolm(void)
 	return (pci_read_config16(MCU, 0x84) & 0xfff0) >> 4;
 }
 
-void *cbmem_top(void)
+void *cbmem_top_chipset(void)
 {
 	uintptr_t tolm;
 	uintptr_t fb_size;