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Diffstat (limited to 'src/soc/amd/common/block/include/amdblocks/amd_pci_util.h')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/amd_pci_util.h27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
index 081741ad285b..b9cd1406c943 100644
--- a/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
+++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_util.h
@@ -31,7 +31,34 @@ void write_pci_cfg_irqs(void);
void write_pci_int_table(void);
const struct irq_idx_name *sb_get_apic_reg_association(size_t *size);
+enum pci_routing_swizzle {
+ PCI_SWIZZLE_ABCD = 0,
+ PCI_SWIZZLE_BCDA,
+ PCI_SWIZZLE_CDAB,
+ PCI_SWIZZLE_DABC,
+};
+
+/**
+ * Each PCI bridge has its INTx lines routed to one of the GNB IO-APIC PCI
+ * groups. Each group has 4 interrupts. The INTx lines can be swizzled before
+ * being routed to the IO-APIC. If the IO-APIC redirection entry is masked, the
+ * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IO-APIC.
+ **/
+struct pci_routing_info {
+ uint8_t devfn;
+ uint8_t group;
+ uint8_t swizzle;
+ uint8_t irq;
+} __packed;
+
/* Implemented by the SoC */
void populate_pirq_data(void);
+/* Implemented by the SoC */
+const struct pci_routing_info *get_pci_routing_table(size_t *entries);
+
+const struct pci_routing_info *get_pci_routing_info(unsigned int devfn);
+
+unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin);
+
#endif /* AMD_BLOCK_PCI_UTIL_H */