9 files changed, 17 insertions, 20 deletions

diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 13acf86adadd..9bcd78698bcd 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
 #include <acpi/acpigen.h>
 #include <device/mmio.h>
 #include <arch/smp/mpspec.h>
@@ -57,7 +58,7 @@ static acpi_cstate_t cstate_map[] = {
 	}
 };
 
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
 {
 	/* Set unknown wake source */
 	gnvs->pm1i = -1;
diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h
index fc8f8aba4c26..98b8283fe427 100644
--- a/src/soc/intel/baytrail/include/soc/acpi.h
+++ b/src/soc/intel/baytrail/include/soc/acpi.h
@@ -7,6 +7,5 @@
 #include <soc/nvs.h>
 
 unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
 
 #endif /* _BAYTRAIL_ACPI_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index cc70f78b2a8a..cdffc75768f6 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -7,7 +7,7 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #include <soc/device_nvs.h>
 
-typedef struct global_nvs_t {
+struct __packed global_nvs {
 	/* Miscellaneous */
 	u16	osys; /* 0x00 - Operating System */
 	u8	smif; /* 0x02 - SMI function call ("TRAP") */
@@ -53,12 +53,8 @@ typedef struct global_nvs_t {
 
 	/* Baytrail LPSS (0x1000) */
 	device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
 
-void acpi_create_gnvs(global_nvs_t *gnvs);
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
 
 #endif /* _BAYTRAIL_NVS_H_ */
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 78638de816ff..3a12a4b5a8f8 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -50,7 +50,7 @@ static void lpe_enable_acpi_mode(struct device *dev)
 			    LPE_PCICFGCTR1_ACPI_INT_EN),
 		REG_SCRIPT_END
 	};
-	global_nvs_t *gnvs;
+	struct global_nvs *gnvs;
 
 	/* Find ACPI NVS to update BARs */
 	gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index d5c3e4de3149..cdf78b7314e3 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -28,7 +28,7 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg,
 		REG_SCRIPT_END
 	};
 	struct resource *bar;
-	global_nvs_t *gnvs;
+	struct global_nvs *gnvs;
 
 	/* Find ACPI NVS to update BARs */
 	gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index d27a17dcd145..995fe20679c6 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -117,7 +117,7 @@ static void fill_in_pattrs(void)
 }
 
 /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
-static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
+static void s3_save_acpi_wake_source(struct global_nvs *gnvs)
 {
 	struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
 	uint16_t pm1;
@@ -144,14 +144,14 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
 
 static void s3_resume_prepare(void)
 {
-	global_nvs_t *gnvs;
+	struct global_nvs *gnvs;
 
-	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
 	if (gnvs == NULL)
 		return;
 
 	if (!acpi_is_wakeup_s3())
-		memset(gnvs, 0, sizeof(global_nvs_t));
+		memset(gnvs, 0, sizeof(struct global_nvs));
 	else
 		s3_save_acpi_wake_source(gnvs);
 }
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 455f243184f6..f178e83d28e9 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -81,7 +81,7 @@ void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
 		REG_SCRIPT_END
 	};
 	struct resource *bar;
-	global_nvs_t *gnvs;
+	struct global_nvs *gnvs;
 
 	/* Find ACPI NVS to update BARs */
 	gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 91eb6f561d06..2a56f84949e0 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -19,7 +19,7 @@
 #include <soc/nvs.h>
 
 /* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
 static int smm_initialized;
 
 int southbridge_io_trap_handler(int smif)
@@ -44,7 +44,7 @@ void southbridge_smi_set_eos(void)
 	enable_smi(EOS);
 }
 
-global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
 {
 	return gnvs;
 }
@@ -330,7 +330,7 @@ static void southbridge_smi_apmc(void)
 		state = smi_apmc_find_state_save(reg8);
 		if (state) {
 			/* EBX in the state save contains the GNVS pointer */
-			gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+			gnvs = (struct global_nvs *)((uint32_t)state->rbx);
 			smm_initialized = 1;
 			printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
 		}
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 679c04d49187..38f51ff52123 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -5,6 +5,7 @@
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
 #include <bootstate.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -482,7 +483,7 @@ void southcluster_enable_dev(struct device *dev)
 
 static void southcluster_inject_dsdt(const struct device *device)
 {
-	global_nvs_t *gnvs;
+	struct global_nvs *gnvs;
 
 	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 	if (!gnvs) {